- CS6303 Computer Architecture
- 2-Lecture Notes Lesson3 2
- Arithmetic Building Blocks
- Floating Point to Fixed
- Perkuliahan 8 - Organisasi Sistem Komputer - Aritmatika Komputer
- 101823204-CAR-66-Module-5-5-Logic-Circuit.pptx
- Final Floating Array Multiplier 1
- Floating Point Conversions
- Untitled
- ch04
- 1.a New Reversible Design of Bcd Adder1
- Numerical Computation Guide and What every scientist should know about floating point arithmetic.pdf
- HFFFFFFFFFFFFFFFFFFFFFFFFFFF.odt
- IJARECE-VOL-2-ISSUE-11-872-874
- Coreutils Linux
- Ch1_SQ_Ans
- 689 Chiang
- Optimization and Implementation of Parallel Squarer
- Number system
- CO unit 1-2.docx
- vanspronsen projectthreemi unitplan
- FIRST PT MATH 6
- Using Library Modules
- Design of Carry Select Adder for Image Processing
- 73.Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers
- Px c 3890582
- CQ3
- ffgf
- SERIES PROGRAMMABLE CONTROLLERS.pdf
- Vtu 10mca13 Fco
- 1997 Perfect Reconstruction Circular Convolution Filter Banks and Their Application to the Implementation of Bandlimited Discrete Wavelet Transforms
- 1977 New Algorithms for Digital Convolution
- 1975 Number Theoretic Transforms to Implement Fast Digital Convolution
- bsnl bill 2016-2017
- 1974 Fast One-Dimensional Digital Convolution by Multidimensional Techniques
- 1974 Fast Convolution Using Fermat Number Transforms With Applications to Digital Filtering
- 1982 Sequential Convolution Techniques for Image Filtering
- 1990 Parallel Implementation of the Convolution Method in Image Reconstruction
- My Name is Vipin Kumar
- idonotknow
- 000154774
- 1984 Implementation of Cellular-Logic Operators Using 3 3 Convolution and Table Lookup Hardware
- 1996 Lossless Acceleration of Fractal Image Compression by Fast Convolution
- 22-EncodingPartitioning
- Brief Profile Format-RKB
- 1987 New 2n Dct Algorithms Suitable for Vlsi Implementation
- Contacts No
- 2013Jan25Docomo300RsSurbhi
- Cocu Rrr Icu Llar
- Latex Tutorial
- Assignment for Electronics I Year I Sem
- ercv16-07-2014
- 1994 a Fast Thresholded Linear Convolution Representation of Morphological Operations
- 2005 Low Power N-bit Adders and Multiplier Using Lowest-number-Of-transistor 1-Bit Adders
- 2013 VHDL Modeling of Booth Radix-4 Floating Point Multiplier for VLSI Designers Library
- Chapter_4single Stage IC Amplifier(for IT Class)
- File 0001
- Examples of Block Diagram Reduction
- Assignment-2 Control System
- 2014 IJRET- International Journal of Research in Engineering and Technology

]

[ISSN: 2231-4946]

**Performance Comparison of Fast Multipliers Implemented on Variable Precision Floating Point Multiplication Algorithm
**

Neelima Koppala1, Rohit Sreerama2, Paidi Satish2

1,2

**Sree Vidyanikethan Engineering College, Tirupathi
**

koppalaneelima@gmail.com

Abstract:- The multiplication is the basic arithmetic operation in any typical processor. The multiplication process requires more hardware resources and processing time when compared with addition and subtraction. The accuracy of a multiplication mostly relies on the precision of the multiplication; a variable precision multiplier will have more accuracy than single or double precision multipliers. In this paper, a variable precision floating point multiplier is considered and total architecture for the variable precision multiplier is proposed also four different multipliers are implemented using the variable precision algorithm. The comparative study on performance analysis like delay characteristics and area is done for the considered multipliers. The best multiplier to be used for the variable precision algorithm is proposed. Keywords:- Array Multiplier, Carry Save Multiplier, Modified Booth Multiplier, Vedic Multiplier, Variable Precision, Floating Point Multiplication, Speed, Accuracy.

will have the accuracy and speed which is desired in any processors. This paper is organised as follows section 2 recalls the variable precision floating point number representation format and the existing variable precision algorithm, section 3 describes the functionality of various multipliers used in the paper, section 4 describes the proposed architecture for the variable precision floating point multiplier, section 5 gives the results of comparative study of the various multipliers implemented on variable precision floating point multiplier, section 6 concluded the paper followed by references. II. EXISTING VARIABLE PRECISION FLOATING POINT MULTIPLIER ALGORITHM In this section existing variable precision floating point multiplier is described. The variable precision floating point multiplier is based on the variable precision floating point number representation format [1]. The format for variable precision floating point is shown in the figure 1. The variable precision representation is different when compared with the single or double precision that is proposed by IEEE 754 format. The variable precision floating point representation will have a sign bit (S), a type field (T), a length field (L), 16 bit exponent and significant word which varies from F(0) to F(L) [1]. The sign bit is either positive or negative depending on the value. If the value of sign bit is 1 then the number is negative, if the sign bit is 0 then the number is positive. The type field consists of two bits, it represents the type of number. Depending on the value of type field the number is considered as normalized, infinite, zero or NaN. The length field is of five bit length, it shows the number of m bit words present in the significant. The words in the significant are stored in the format of most significant F (0) to least significant F (L) [1]. The existing variable precision floating multiplier is based on the algorithm which can be implemented easily on any hardware [1]. In this algorithm only mantissas are considered. The algorithm reduces the

I. INTRODUCTION The computation speed of the computers has increased dramatically during the last decade. This increase in the speed is due to the development of VLSI technology which enabled the integration of millions of transistors on single chip [1]. Even the computational speed has increased the accuracy of the systems is not increased to that extent. Without accuracy, errors can easily occur in any system. The accuracy of a multiplication mostly relies on the precision of the multiplication; a variable precision floating point multiplier will have more accuracy than single or double precision multipliers [1]. The multiplication is the most fundamental operation in any arithmetic logic unit. Also the multipliers will take much more time for execution, so the need for speed multiplier with accuracy is desired. Many fast multipliers like array multiplier, booth multiplier etc., are proposed to increase the speed of the multiplication operation. The fast multipliers plays key role in VLSI high speed processor [2]. To design a best processor we need to consider both the accuracy and speed of operation. So a variable precision floating point multiplier when implemented with fast multipliers

56 | P a g e

To generate the product terms an array of AND gates are used before the adder array. in array multiplier worst case delay would be (2n+1) td [3]-[4]. Fig 2:. B. This algorithm only uses the memory of (n x 2m) bits instead of (n2 x 2m) bits that are used in the classic multiplication. as shown in the following figure 3. Depending on the value of the m the size of the multiplier and the memory are considered [1]. Carry Save Multiplier. The purpose of the encoding is to scan the triplet of bits of the multiplier and define the operation to be performed on the multiplicand. al. In this technique the number of partial products are reduced by one half regardless of the inputs [6]. The fast multipliers play a key Role in VLSI high speed processors. Array Multiplier Array multiplier is an efficient layout of a combinational multiplier. There are mn partial products that are produced in parallel by a set of mn AND gates. can be generalized to any radix. When large numbers are 57 | P a g e . usually called the Modified Booth algorithm. consider two binary numbers A and B. C. The four different fast multipliers that are considered in this paper are Array Multiplier. For the simultaneous addition of all the product terms the array is used in the multiplier [3]-[4]. The Recoding is performed in two steps: encoding and selection. Fig 1:. By employing array of full adders and half adders the multiplication of two binary numbers is carried out in the array multiplier.Koppala et.Implementation of Modified Booth Algorithm. Fig 3:. In the carry save multiplier the partial products are generated in parallel and the carry save adder are used to sum all the partial products which results in faster array multiplier [5]. The modified booth algorithm is fast but the hardware complexity increases [6]. Nikhilam Sutra means “all from 9 and last from 10”. Due to this the array multiplier is fast multiplier but the hardware complexity is more for the array multiplier [4]. D. n half-adders and n2 AND gates. Modified Booth Algorithm A Modification of the Booth algorithm a triplet of bits is scanned instead of two bits. Carry Save Multiplier The carry save multipliers are much more similar to the array multipliers [5]. The booth algorithm. Vedic Multiplier and Modified Booth Multiplier. Also. Nikhilam sutra is one of the Vedic methods of multiplication [7]. FUNCTIONALITY OF EXISTING FAST MULTIPLIERS In this section four fast multiplier are considered and their functionality is explained.Variable Precision Format. The power consumption of the array multiplier is more and also the delay is more.Array Multiplier. The figure 2 shows the array multiplier. III. memory that is used to store the partial products that are generated during computation in classic multiplication method by adding the partial products as soon as they are computed. Vedic Multiplication Vedic multiplication is one of the fastest multiplication method that was followed in ancient mathematics. For a n x n bit multiplier requires n (n-2) full adders. A. This algorithm splits the operands A and B and the result into m bits. In array multiplier. of m and n bits.

lesser the complexity of the multiplication [7]. RESULTS The comparative study is made on four fast multipliers implemented on variable precision floating point multiplier that are considered in the paper.120ns 56. of bonded IOBs 128 out of 232 55% 128 out of 232 55% 128 out of 232 55% 128 out of 232 55% PROPOSED ARCHITECTURE FOR VARIABLE PRECISION FLOATING POINT MULTIPLIER In this section architecture for variable precision floating point multiplier is proposed.963ns 55. No. of 4 input LUTs 1501 out of 9312 16% 1424 out of 9312 15% 1139 out of 9312 12% 712 out of 9312 16% Fig 4:. Of Slices 838 out of 4656 17% 794 out of 4656 17% 598 out of 4656 12% 384 out of 4656 17% No. a comparative study is made on the performance of all the multipliers when implemented on the variable precision floating point multiplier. TABLE 1:. The figure 5 shows the architecture of the variable precision floating point multiplier. The XILINX ISE 10.010ns No. The FPGA family selected is Spartan 3E XC3S500E.Performance Comparison of Fast Multipliers Implemented on Variable Precision Floating Point Multiplication Algorithm involved the nikhilam sutra is the most efficient method to consider. Fig 5:.854ns 54. All the additions are carried out using carry look ahead adder circuits. TABLE 2:. The compliment of the large number from its nearest base is calculated to perform the multiplication operation on it. The simulation result for the total architecture is shown in the figure 6. combinational path delay 59. The length field is obtained by adding the length field of both the input operands. The exponent is obtained by the 16 bit adder/substractor. The nikhilam sutra implementation is shown in the figure 4.Proposed Architecture for Variable Precision Floating Point Multiplier 58 | P a g e . V.COMPARISION RESULTS OF FAST MULTIPLIERS IMPLEMENTED ON VARIABLE PRECISION FLOATING POINT MULTIPLIER Type of Multiplier Array Multiplier Carry Save Multiplier Vedic Multiplier Modified Booth Multiplier Max. All the above four fast multipliers are considered in the paper. The coading is done in VERILOG HDL. The type field is obtained from the control unit. The total architecture is based on the variable precision floating point representation.COMPARISION RESULTS OF FAST MULTIPLIERS IMPLEMENTED ON VARIABLE PRECISION FLOATING POINT MULTIPLIER. Type of Multiplier Array Multiplier Carry Save Multiplier Vedic Multiplier Modified Booth Multiplier No. IV. The delay characteristics and the area are calculated and tabulated. The sign bit of the result R that is SR is obtained by the XOR operation of the sign bit of both operands A and B. of MULT18X18SIOs ---20 out of 20 100% The table 1 and table 2 shows the comparision results.Example of Nikhilam Sutra. So larger the original number. Depending on the type of the input operands the type of the result is obtained [8]. The significand is obtained from the multipliation of both the significands of input operands.1 is used to simulate and synthesis.

“An Algorithm for variable precision based floating point multiplication”.cs. So we can conclude that depending upon the requirement of the processor either vedic multiplier or modified booth multiplier can be used with the variable precision floating point algorithm.edu/ IEEE-754. IEEE Transactions Volume: 47. 2011 International Conference Page(s): 254 . “Design and evaluation of decimal array multipliers” Signals.J.. page no238-242. 2010 The 2nd International Conference Page(s): 862 – 865 IEEE-754 Reference Material http://babbage. A. “A novel low power. Rao. al. R. Jaberipur.Simulation Result of Total Architecture of Variable Precision Floating Point Multiplier.797 vol.S. T. Paidi Satish.K.2 [2] [3] [4] [5] 59 | P a g e . AIM 2012.Naganathan. Prasad.Koppala et. Hollopeter “A compact carry-save multiplier architecture and its applications” Circuits and Systems.qc. Gorgin. N. Vaidya.J. “A fast parallel multiplier-accumulator using the modified Booth algorithm” Circuits and Systems II: Analog and Digital Signal Processing. A. H. Parhami..908 Kumar. Subbaiah. The comparative results concludes that the vedic multiplier will have less delay when compaed with other multipliers and modified booth algorithm will occupy less area when compared with other multipliers. Raghunath. REFERENCES [1] Rohit Sreerama.. R.. Systems and Computers. Vlsi And Signal Processing. M. Mondal. “Low power ALU design by ancient mathematics” Computer and Automation Engineering (ICCAE). Communication.cuny. Y.. 1997.. G. N. CONCLUSION In this paper four different fast multipliers are implemented using the variable precision floating point algorithm and design utility and path delays are compared..old/References. 2009 Conference Record of the Forty-Third Asilomar Conference Page(s): 1782 – 1786.. The total architecture for variable precision floating point multiplier unit which follows the variable precision format is proposed.257.pg 263266.. F. Farrokh. D. Page(s): 902. low area array multiplier design for DSP applications” Signal Processing.. Ravi. T. Masci. proc International Conference on Advances in Information Technology and Mobile Communication. Raman. [6] [7] [8] Elguibaly. K Neelima. VI. Dandekar “Performance Comparison of Multipliers for Power-Speed Trade-off in VLSI Design” Recent Advances In Networking. K. Rambaud. F. The simulation and synthesis results are analysed using XILINX ISE. S. Computing and Networking Technologies (ICSCCN). B.xhtml Fig 6:. Proceedings of the 40th Midwest Symposium Page(s): 794 . Sumit R..

- CS6303 Computer ArchitectureUploaded byalac_john
- 2-Lecture Notes Lesson3 2Uploaded bykstu1112
- Arithmetic Building BlocksUploaded byVenkateshwarlu Pillala
- Floating Point to FixedUploaded bycnt2ssk
- Perkuliahan 8 - Organisasi Sistem Komputer - Aritmatika KomputerUploaded byFauziah Husnaa
- 101823204-CAR-66-Module-5-5-Logic-Circuit.pptxUploaded byJAYACHANDRAN
- Final Floating Array Multiplier 1Uploaded byJaswant Singh
- Floating Point ConversionsUploaded byAtul Srivastava
- UntitledUploaded bymanish_2239
- ch04Uploaded byprasannakumar_7
- 1.a New Reversible Design of Bcd Adder1Uploaded byAkanksha Gupta
- Numerical Computation Guide and What every scientist should know about floating point arithmetic.pdfUploaded bywbdsdvyo
- HFFFFFFFFFFFFFFFFFFFFFFFFFFF.odtUploaded byAnonymous ZRrrG6
- IJARECE-VOL-2-ISSUE-11-872-874Uploaded byhkakashi93
- Coreutils LinuxUploaded byunIimited
- Ch1_SQ_AnsUploaded byapi-3700944
- 689 ChiangUploaded byChuang James
- Optimization and Implementation of Parallel SquarerUploaded byInternational Journal of Research in Engineering and Technology
- Number systemUploaded byM
- CO unit 1-2.docxUploaded byAravinder Reddy Suram
- vanspronsen projectthreemi unitplanUploaded byapi-239505795
- FIRST PT MATH 6Uploaded byvincevillamora2k11
- Using Library ModulesUploaded byJuan Rafael Villen Pulido
- Design of Carry Select Adder for Image ProcessingUploaded byInternational Journal of Innovative Science and Research Technology
- 73.Radix-4 and Radix-8 Booth Encoded Multi-Modulus MultipliersUploaded byAshok Siva Kumar Poojala
- Px c 3890582Uploaded byYermakov Vadim Ivanovich
- CQ3Uploaded bySmita R. S.
- ffgfUploaded bykalicharan13
- SERIES PROGRAMMABLE CONTROLLERS.pdfUploaded byTam Dang
- Vtu 10mca13 FcoUploaded byಮುರಳಿ ಟಿ ಎಸ್

- 1997 Perfect Reconstruction Circular Convolution Filter Banks and Their Application to the Implementation of Bandlimited Discrete Wavelet TransformsUploaded byRajesh Bathija
- 1977 New Algorithms for Digital ConvolutionUploaded byRajesh Bathija
- 1975 Number Theoretic Transforms to Implement Fast Digital ConvolutionUploaded byRajesh Bathija
- bsnl bill 2016-2017Uploaded byRajesh Bathija
- 1974 Fast One-Dimensional Digital Convolution by Multidimensional TechniquesUploaded byRajesh Bathija
- 1974 Fast Convolution Using Fermat Number Transforms With Applications to Digital FilteringUploaded byRajesh Bathija
- 1982 Sequential Convolution Techniques for Image FilteringUploaded byRajesh Bathija
- 1990 Parallel Implementation of the Convolution Method in Image ReconstructionUploaded byRajesh Bathija
- My Name is Vipin KumarUploaded byRajesh Bathija
- idonotknowUploaded byRajesh Bathija
- 000154774Uploaded byRajesh Bathija
- 1984 Implementation of Cellular-Logic Operators Using 3 3 Convolution and Table Lookup HardwareUploaded byRajesh Bathija
- 1996 Lossless Acceleration of Fractal Image Compression by Fast ConvolutionUploaded byRajesh Bathija
- 22-EncodingPartitioningUploaded byRajesh Bathija
- Brief Profile Format-RKBUploaded byRajesh Bathija
- 1987 New 2n Dct Algorithms Suitable for Vlsi ImplementationUploaded byRajesh Bathija
- Contacts NoUploaded byRajesh Bathija
- 2013Jan25Docomo300RsSurbhiUploaded byRajesh Bathija
- Cocu Rrr Icu LlarUploaded byRajesh Bathija
- Latex TutorialUploaded byRajesh Bathija
- Assignment for Electronics I Year I SemUploaded byRajesh Bathija
- ercv16-07-2014Uploaded byRajesh Bathija
- 1994 a Fast Thresholded Linear Convolution Representation of Morphological OperationsUploaded byRajesh Bathija
- 2005 Low Power N-bit Adders and Multiplier Using Lowest-number-Of-transistor 1-Bit AddersUploaded byRajesh Bathija
- 2013 VHDL Modeling of Booth Radix-4 Floating Point Multiplier for VLSI Designers LibraryUploaded byRajesh Bathija
- Chapter_4single Stage IC Amplifier(for IT Class)Uploaded byRajesh Bathija
- File 0001Uploaded byRajesh Bathija
- Examples of Block Diagram ReductionUploaded byRajesh Bathija
- Assignment-2 Control SystemUploaded byRajesh Bathija
- 2014 IJRET- International Journal of Research in Engineering and TechnologyUploaded byRajesh Bathija