CS2253 - COMPUTER ORGANIZATION AND ARCHITECTURE UNIT I BASIC STRUCTURE OF COMPUTERS 1. What ! "a"h# $#$%&'( The small and fast RAM units are called as caches.when the execution of an instruction calls for data located in the main memory,the data are fetched and a copy is placed in the cache. Later if the same data is required it is read directly from the cache. 2. What ! th# )*+"t %+ %) ALU( Most of the computer operations (arithmetic and logic are performed in AL!. The data required for the operation is "rought "y the processor and the operation is performed "y the AL!. #. What ! th# )*+"t %+ %) CU( The control unit acts as the ner$e center,that coordinates all the computer operations. %t issues timing signals that go$erns the data transfer. &. What a&# ,a! " %-#&at %+! %) a "%$-*t#&( The "asic operations are R'A( and )R%T'. *. What a&# th# &#. !t#&! .#+#&a//' "%+ta +#0 + th# -&%"#!!%&(      MAR+Memory Address Register M(R+Memory (ata Register %R+%nstruction Register R,+Rn+-eneral purpose Registers ./+.rogram /ounter • • • • 3. 1etch (ecode 'xecute 2tore

0. What a&# th# !t#-! + #1#"*t +. a -&%.&a$(

D#) +# +t#&&*-t a+0 ISR( An interrupt is a request from an %45 de$ice for ser$ice "y the processor. The processor pro$ides the requested ser$ice "y executing the interrupt ser$ice routine.

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D#) +# B*!( What a&# th# 0 ))#&#+t ,*!#! + a CPU( A group of lines that ser$es as a connecting path for se$eral de$ices is called a "us. The different "uses in a /.! are address "us, data "us and control "us.


What ! th# *!# %) ,*))#& &#. !t#&( The "uffer register is used to a$oid speed mismatch "etween the %45 de$ice and the processor.

8,. C%$-a&# ! +./# ,*! !t&*"t*&# a+0 $*/t -/# ,*! !t&*"t*&#( A system that contains only one "us(i.e only one transfer at a time is called as a single "us structure. A system is called as multiple "us structure if it contains multiple "uses. 88. What ! S'!t#$ S%)t2a&#( G 3# a+ #1a$-/#( %t is a collection of programs that are executed as needed to perform functions such as • • Recei$ing and interpreting user commands 'ntering and editing application programs and storing them as files

in secondary storage de$ices. E14 Assem"ler, Lin9er, /ompiler etc 82. What ! A--/ "at %+ S%)t2a&#( G 3# a+ #1a$-/#( Application programs are usually written in a high+le$el programming language, in which the programmer specifies mathematical or text+processing operations. These operations are descri"ed in a format that is independent of the particular computer used to execute the program. E14 /, /::, ;A<A 8#. What ! a "%$- /#&( A system software program called a compiler translates the high+le$el language program into a suita"le machine language program containing instructions such as the Add and Load instructions. 8&. What ! t#1t #0 t%&( %t is used for entering and editing application programs. The user of this program interacti$ely executes command that allow statements of a source program entered at a 9ey"oard to "e accumulated in a file. 8*. D !"*!! a,%*t OS a! !'!t#$ !%)t2a&#(

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What ! #/a-!#0 t $# %) "%$-*t#& !'!t#$( The total time to execute the total program is called elapsed time. 80.. W& t# 0%2+ th# . %t depends on the hardware in$ol$ed in the execution of indi$idual machine instructions.&a$( The period during which the processor is acti$e is called processor time of a program.( The o$erlapping of execution of successi$e instructions is called pipelining. This pattern of concurrent execution is called multiprogramming or multitas9ing. What ! . The name little endian is used when lower "yte addresses are Department of Information Technology @ SVS College of Engineering Page 3 . 83. %& $*/t ta!5 +. What ! $*/t -&%.( The operating system manages the concurrent execution of se$eral application programs to ma9e the "est possi"le uses of computer resources. 22.52 is a large program. D#) +# "/%"5 &at#( The cloc9 rate is gi$en "y. The 52 routines perform the tas9s required to assign computer resources to indi$idual application programs.. where .'t# a00&#!!a. R=84.-#/ + +. 2. #+0 a+ a+0 / tt/# #+0 a+ )%&$at( The name "ig endian is used when lower "yte addresses are used for the more significant "ytes of the word. or actually a collection of routines. 86. the dis9 and the printer.&a$$ +.a! " -#&)%&$a+"# #6*at %+( T=>?24R T=processor time >=no of instructions 2=no of steps R=cloc9 rate 28. %t is affected "y the speed of the processor. that is used to control the sharing of and interaction among $arious computer units as they execute application programs. What ! . . 2#. What ! -&%"#!!%& t $# %) a -&%. What ! . 87./# $#$%&'( The assignment of successi$e addresses to successi$e "yte locations in the memory is called "yte addressa"le memory. is the length of one cloc9 cycle.

20.used for the less significant "ytes of the word. What ! . This is accomplished "y recording the required information in indi$idual "its.!( • • • • >(>egati$e @ (@ero <(o$erflow /(/arry The different ways in which the location of an operand is specified in instruction are referred to as addressing modes. 27. $%0#. Department of Information Technology @ SVS College of Engineering Page 4 . This new address is called as "ranch target. 2&.#t( As a result of "ranch instructions . 26. the processor fetches and executes the instruction at a new address called "ranch target. $%0#!( The $arious addressing modes are         A"solute addressing mode Register addressing mode %ndirect addressing mode %ndex addressing mode %mmediate addressing mode Relati$e addressing mode Autoincrement addressing mode Autodecrement addressing mode an 23. 2*. What a&# th# 3a& %*! a00&#!! +. instead of the instruction at the location that follows the "ranch instruction in sequential address order. D#) +# a00&#!! +.&a+"h ta&. What a&# "%+0 t %+ "%0# )/a.!( The processor 9eep trac9 of information a"out the results of $arious operations for use "y su"sequent conditional "ranch instructions. What a&# th# "%$$%+/' *!#0 "%+0 t %+ "%0# )/a. What ! a -% +t#&( The register or memory location that contains the address of an operand is called a pointer. which is called condition code flags.

D#) +# 0#3 "# +t#&)a"#.# !*--%&t#0 .!.RD./ Three+address instruction+ A(( Ri. #2.R9 39.#(  Assem"ly language is con$erted to Machine language using assem"ler which is time consuming when compared with machine language. What a&# th# )%*& ..*! ! .' a+ +!t&*"t %+ !#t(  (ata transfers "etween the memory and the processor registers  Arithmetic and logic operations on data  .a! " t'-#! %) %-#&at %+! that +##0 t% .rogram sequencing and control  %45 transfers. What a&# / $ tat %+ %) a!!#$. 'gA 2!M 'B! 2.#. 0 &#"t %+a/ a+0 a00&#!! .*! ! *+ 0 &#"t %+a/ + $%!t $ "&%-&%"#!!%&!( The data "us is "idirectional "ecause the data "us has to transfer data "etween the /. ##.*a. Wh' ! 0ata . Department of Information Technology @ SVS College of Engineering Page 5 . What ! a!!#$. hence it is unidirectional.! and memory % 4 5 de$ice./#& 0 &#"t 3#( Assem"ler directi$es are not instructions that will "e executed . The "uffer registers (ATA%> and (ATA5!T and the status flags 2%> and 25!T are part of circuitry commonly 9nown as a de$ice interface. whereas the address "us is used to send out memory addresses from the /. 35. %t simply informs the assem"ler that the name 2!M should "e replaced "y the $alue 2.  %t is difficult to sol$e the complex pro"lems.. @ero+address instruction + L5A( 5ne+address instruction + A(( A Two+address instruction + M5<' C. #8.a00&#!!8 %+#-a00&#!!8 t2%-a00&#!! a+0 th&##-a00&#!! +!t&*"t %+!. such statements are called as assem"ler directi$es./' /a+. G 3# a+ #1a$-/# #a"h %) 7#&%.. where$er it appears in the program.

*. queue may 2. &. on a 1%15 "asis. A set of instructions that performs a tas9 is called a program. #. 3. N% 8.#t2##+ Sta"5 a+0 >*#*#. A single pointer is needed to 9eep trac9 of Two pointers are needed to 9eep trac9 of top of the stac9. computer. $%0#!( The information con$eyed "y the addressing mode is to specify the location of an operand in an instruction. A set of sym"olic names and rules has to "e followed. 2ince one end is fixed stac9 does not )ithout further control. !sually stac9 grow in the direction of The queue grows in the direction of decreasing memory addresses. data are added at the "ac9 and from the top of stac9. The processor fetches the instruction that ma9e up the program from the memory. 3<. 3=.. What ! th# +)%&$at %+ "%+3#'#0 . remo$ed from the front. D ))#&#+"# . 1unctional !nits of a computer • %nput !nit Department of Information Technology @ SVS College of Engineering Page 6 . PART B 8. E1-/a + th# $-%&ta+"# %) +t#&&*-t + "%$-*t#& !'!t#$.' a00&#!! +. Sta"5 5ne end of the stac9 is fixed ( the "ottom >*#*# Coth ehds of queue mo$e to higher while the other end rises and falls as data addresses as data are added at the "ac9 and are pushed and popped. 3:. What ! $#a+t . and di$erts its execution to some other program called interrupt ser$ice routine. %nterrupt "rea9s the normal execution of instruction. data are added to and retrie$ed %n queue. mo$e through the memory of the continuously mo$e through the memory of computer from one end to the other. S/. (ata are stored in and retrie$ed from a (ata are stored and retrie$ed from a queue stac9 on a L%15 "asis. one at a time and perform the desired tas9. the two ends of the queue. increasing address in the memory.&a$ "%+"#-t( D !"*!!. retrie$ed from the front of the queue. !sually the program is stored in the memory. %n stac9.' th# !t%&#0 -&%. 0. An interrupt is a request from a input 4 output de$ice for ser$ice "y the processor.

Department of Information Technology @ SVS College of Engineering Page . 'xplain how the processor is interfaced with the memory • • • Casic operations 1igA/onnection "etween processor and the memory 1igure 'xplanation System software is a collection of program that is executed as needed to perform function.• • • • • • • • • • • • • • • • 5utput unit Memory Arithmetic and logic unit /ontrol unit 2. 'xplain %nstruction set and %nstruction 2equencing Register Transfer >otation Assem"ly Language >otation Casic %nstruction types #. Write short notes on Software. 'xplain the Addressing modes %mmediate Addressing (irect addressing %ndirect Addressing Register Addressing Register %ndirect Addressing %ndex Addressing Relati$e Addressing Auto increment mode Auto decrement mode &. • Application software 5. It is also responsible for the co-ordination of all activities in a computing system.

. The control signal used for this purpose is 9nown as Memory+1unction+/ompleted (M1/ . &.. )hen edge+triggered flip flops are not used. and the interconnecting "us are /ollecti$ely referred to as the datapath. To accommodate the $aria"ility in response time. Department of Information Technology @ SVS College of Engineering Page ! . This is 9nown as multiphase cloc9ing. The registers. two or more cloc9 signals may "e needed to guarantee proper transfer of data. 5. UNIT-II BASIC PROCESSING UNITS 1.• • • Compiler ext editor !perating system. #. What ! WMFC. .' .. the AL!. D#) +# MFC. Na$# t2% !-#" a/ -*&-%!# &#. 0. What ! $#a+ . !t#&!.rocessor cloc9 is defined as the time periods in which all 5perations and data transfers within the processor ta9e place. D#) +# -&%"#!!%& "/%"5. %ndex register 2tac9 pointer 2. D#) +# 0ata-ath. )M1/ is the control signal that causes the processorEs control circuitry to wait for the arri$al of the M1/ signal.&a+"h +!t&*"t %+. the processor waits until it recei$es an indication that the requested read operation has "een completed. What ! 5+%2+ a! $*/t -ha!# "/%"5 +.

7. <. 80. What a&# th# t2% a--&%a"h#! *!#0 )%& . What ! "%+t&%/ 2%&0( A control word is a word whose indi$idual "its represent the $arious control signals. A controller that uses this approach can operate at high speed. %t has little flexi"ility and the complexity of the instruction set it can implement is limited. 82.#+#&at +.+a/!. D#) +# $ "&%&%*t +# a+0 $ "&% +!t&*"t %+. !t#& %*t-*t "%+t&%/ ! . such as M1/ and interrupt requests What a&# th# )a"t%&! 0#t#&$ +# th# "%+t&%/ ! ./ with the "ranch target address. Gardwired control Microprogrammed control • • • • /ontents of the control step counter /ontents of the instruction register /ontents of the condition code flags 'xternal input signals.+a/! + -&%-#& !#6*#+"#(   8. th# "%+t&%/ ! . This address is usually o"tained "y adding an offset F. Na$# !%$# &#.A "ranch instruction is an instruction which replaces the contents of the . 19. D#) +# &#. which is gi$en in the "ranch instruction./. to the updated $alue of the . and the indi$idual control words in this microroutine are referred to as microinstructions. Department of Information Technology @ SVS College of Engineering Page " . 8#. The location following a "ranch instruction is called a "ranch delay slot..&a$$#0 "%+t&%/( Microprogrammed control is a scheme in which control signals are generated "y a program similar to machine language programs. What a&# th# )#at*&#! %) th# ha&02 &#0 "%+t&%/. 15. What ! $ "&%-&%. !t#& ) /#. A sequence of control words corresponding to the control sequence of a machine instruction constitutes the microroutine for that instruction. What ! "%+t&%/ !t%&#( The microroutines for all instructions in the instruction set of a computer are stored in a special memory called the control store.+a/!( 11. All general purpose registers are com"ined into a single "loc9 called the register file.

28. E1-/a + .#! %) ha&0 2 &#0 "%+t&%/ a+0 $ "&% -&%.#! a+0 0 !a03a+ta. D#) +# #$*/at %+. is to ha$e the preceding "ranch microinstructions specify the address 83. and T'M.a+ 7at %+ a+0 h%& 7%+ta/ %&. 5perate at high speed H%& 7%+ta/ %&. R2out.a"5 %) $ "&%-&%. t#"h+ 6*#. C%$-a&# 3#&t "a/ %&.out. What ! 3#&t "a/ %&. Department of Information Technology @ SVS College of Engineering Page 1# .&a$$#0 "%+t&%/( A03a+ta. 'mulation allows us to replace o"solete equipment with more up to date machines. 5perating speed is low. 83. 5perating speed is high. 87. and then use an 5R gate to change the least significant "it of this address to 8if the direct addressing mode is in$ol$ed.(for eg is performed to fetch the operand from the memory. R. What a&# th# a03a+ta. R8out. This is 9nown as the "it+5ring technique for modifying "ranch addresses. What ! th# 0&a2. R#out. the minimally encoded scheme in which many resources can "e controlled with a single microinstruction is called a horiHontal organiHation. 2pecify only a small #. -i$en a computer with a certain instruction set. M(Rout. 2@. @out.out.#! %) Ha&02 &#0 C%+t&%/ i.a+ 7at %+ a+0 h%& 7%+ta/ %&.a+ 7at %+ 8.. %f the direct mode is specified.a+ 7at %+ Minimally encoded schemes Many resources can "e controlled. 5n the other hand./out. 1<. 'mulation facilitates transitions to new computer systems with minimal disruption. this fetch must "e "ypassed "y "ranching immediately to location 838. %f the indirect mode is specified in the instruction. 5ffsetout. it is possi"le to define additional machine instructions and implement them with extra microroutines.a+ 7at %+. The most efficient way to "ypass microinstruction 83. t-OR +. 22. then the microinstruction in the location 83. Gighly encoded schemes 2.&a$$#0 "%+t&%/( %t leads to a slower operating speed "ecause of the time it ta9es to fetch microinstructions from the control store.a+ 7at %+( Gighly encoded schemes that use compact codes to specify only a small num"er of control functions in each microinstruction are referred to as a $ertical organiHation. ?#&t "a/ %&.

i. 3.diagram for hardwired control unit. ii. • • • • • • • +ardwired control unit consists of combinational circuits to generate various control signals.#! %) $ "&% -&%.&a$$#0 "%+t&%/ D !a03a+ta. Gigh flexi"ility 2lower operating speed.  %eatures of three bus structures.loc. Explain the Multiple bus organization  "ultiple bus organi'ation has more than one bus to connect the registers and A() of a processor. Control unit organi'ation . .  Circuit diagram * three bus organi'ation of the data path.of encoding and decoding A complete processor Advantages and disadvantages. ii.#! %) Ha&02 &#0 C%+t&%/ A03a+ta. /ontrol signals are generated "y a program itself.#! %) $ "&% -&%.xample se$uence of control signals &etailed bloc. 9. Little flexi"ility /omplexity of the instruction set can implement is limited.ii. PART B D !a03a+ta. E1-/a + #1#"*t %+ %) a "%$-/#t# +!t&*"t %+ • 1igure Page 11 Department of Information Technology @ SVS College of Engineering .  "icro instructions  "icro instructions se$uencing  %low chart of a microprogram for the Add src# &dst instruction  Advantages and disadvantages. 2. i. Explain hardwired control. Draw and explain the micro programmed control unit. 'ach state of this counter corresponds to one control step.  "icro programmed control# in which control signals are generated by a program similar to machine language programs.&a$$#0 "%+t&%/ 1. i.

    1etchA read the instruction from the memory. The solutions for data haHards are i. iii. A data haHard is any condition in which either the source or the destination operands of an instruction are not a$aila"le at the time expected in the pipeline. What ! !t&*"t*&a/ ha7a&0( Department of Information Technology @ SVS College of Engineering Page 12 . :. 9.• 2ample instruction UNIT III PIPELINING PART A 1. 2. execute unit. and the write unit are idle are called stalls. (ecodeA decode the instruction and fetch the source operand. They are also referred to as "u""les in the pipeline.-#/ + +. What a&# +!t&*"t %+ ha7a&0!( The pipeline may also "e stalled "ecause of a delay in the a$aila"ility of an instruction. What ! P -#/ + +. What ! 0ata ha7a&0( What a&# th# !%/*t %+!( Any condition that causes the pipeline to stall is called a haHard. this may "e a result of a miss in the cache. 5. 'xecuteA perform the operation specified "y the instruction. 3. 5perand forwarding Gandling data haHard "y software To stall. 1or example.. 5$erlapping the execution of successi$e instruction. ii. 2uch haHards are often called control haHards or instruction haHards. requiring the instruction to e fetched from the main memory. What a&# "a//#0 !ta//!( The periods in which the decode unit. Na$# th# )%*& !t#-! + . )riteA store the result in the destination location.

<. 11.. Any approach that has this characteristic is called static "ranch prediction. =. They are 9nown as superscalar processors. What ! !a 0 t% . Another approach in which the prediction decision may change depending on execution history is called dynamic "ranch prediction. What a&# "%+0 t %+ "%0#!( %n many processors.2tructural haHard is the situation when two instructions require the use of a gi$en hardware resource at the same time. What ! "a//#0 !tat " a+0 0'+a$ " . 12.&a+"h -&#0 "t %+( The "ranch prediction decision is always the same e$ery time a gi$en instruction is executed. What ! $-&#" !# a+0 -&#" !# #1"#-t %+( 2ituation in which one or more of the succeeding instructions ha$e "een executed to completion is called imprecise exception. 2peculati$e execution means that instructions are executed "efore the processor is certain that they are in the correct execution sequence. This is called a precise exception. 2ituation in which all su"sequent instructions that may ha$e "een partially executed are discarded. and the processor is said to use multiple issue. the instruction is said to ha$e a side effect. 13. This technique is referred to as "ranch folding.( The instruction fetch unit executes the "ranch instruction concurrently with the execution of other instructions. What a&# !*-#&!"a/a& -&%"#!!%&!( 2e$eral instructions start execution in the same cloc9 cycle. 2uch processors are capa"le of achie$ing an instruction execution throughput of more than one instruction per cycle. .&a+"h )%/0 +.# ! 0# #))#"t( )hen a location other than one explicitly named in an instruction as a destination operand is affected. 8. the condition code flags are stored in the processor status register. 8&. so that they can "e tested "y su"sequent conditional "ranch instructions to change the flow of program execution.. The most common case in which this haHard may arise is in access to memory. What ! . They are either set or cleared "y many instructions. D#) +# !-#"*/at 3# #1#"*t %+. What ! a 0#a0/%"5( Department of Information Technology @ SVS College of Engineering Page 13 .

A and C. use a shared resource.ipelining • • • • • • • • • • • • • • Casic concepts 1our steps Role of cache memory GaHards instruction pipelining .ipelining stall #. 'xplain .A deadloc9 is a situation that can arise when two units. 2. 'xplain influence on instruction set Addressing modes /omplex addressing mode (isad$antages of complex addressing mode /ondition code (ata path and control consideration Page 14 Department of Information Technology @ SVS College of Engineering . At the same time. unit C has "een assigned a resource that unit A needs. 'xplain (ata haHards (efinition 'xample 5perand forwarding Gandling data haHards in software &. %f this happens. !nit A is waiting for the resource it needs. unit C is waiting for unit A to finish "efore it can release that resource. neither unit can complete its tas9. • • • )nconditional branch Instruction $ueue and prefetching Conditional branches. Explain Instruction hazard • Instruction ha'ard occurs normally due to branch instruction since the branch condition and the branch address are not available in time to fetch the next instruction on the next cloc-. 2uppose that unit C cannot complete its tas9 until unit A completes its tas9. which is "eing held "y unit ". PART B 1. At the same time.

What a&# th# Cha&a"t#& !t "! %) !#$ "%+0*"t%& RAM $#$%& #!( · · · · • • • • • • • They are a$aila"le in a wide range of speeds. &. They replaced the expensi$e magnetic core memories. D#) +# !tat " $#$%& #!( Memories that consists of circuits capa"le of retaining their state as long as power is applied is called 2tatic memories. D#) +# $#$%&' a""#!! t $#( The time required to access one word is called the memory access time 5r %t is the time that elapses "etween the initiation of an operation and the completion of that operation. #.UNIT I? MEMORY SYSTEM 8. They are of high cost. They are used for implementing memories. Their cycle time range from 8. %t is a special memory control circuit used for implementing the mapping of the $irtual address space onto the physical memory.. 2. D#) +# M#$%&' Lat#+"'( Department of Information Technology @ SVS College of Engineering Page 15 . 6. 'g. What ! MMU( MM! is the Memory Management !nit. Less density. Refresh circuitry is needed. What a&# th# Cha&a"t#& !t "! %) SRAM!( 3. 0.ns. They are $olatile. *.ns to less than 8. Gigh density. The time "etween two successi$e read operations. D#) +# $#$%&' "'"/# t $#( %t is the minimum time delay required "etween the initiation of two successi$e memory operations. 2RAMs are fast. What a&# th# Cha&a"t#& !t "! %) DRAM!( Low cost.

What a&# a!'+"h&%+%*! DRAM!( %n asynchronous (RAMs. (%MMs are (ual %n+line Memory Modules. %t also sends R4) and /2 signals to the memory. )hen used with (RAM chips . Gigh density Page 16 Department of Information Technology @ SVS College of Engineering . 88. the timing of the memory de$ice is controlled asynchronously. %t is used for performing multiplexing of address "its.%t is used to refer to the amount of time it ta9es to transfer a word of data to or from the memory. 8. D ))#&#+t at# !tat " RAM a+0 0'+a$ " RAM( S/. What a&# !'+"h&%+%*! DRAM!( 2ynchronous (RAMs are those whose operation is directly synchroniHed with a cloc9 signal. They require se$eral transistors Low density D'+a$ " RAM They are slow They are less expensi$e They donot retain their state indefinitely They require less num"er of transistors.N% 8 2 # & * Stat " RAM They are fast They are $ery expensi$e They retain their state indefinitely. 8&. such memories are asynchronous (RAMs .%t pro$ides RA2+ /A2 timing. A specialised memory controller circuit pro$ides the necessary control signals RA2 and /A2 that go$ern the timing. which do not ha$e self refreshing capa"ility . What a&# SIMM! a+0 DIMM!( 2%MMs are 2ingle %n+line Memory Modules./# 0ata &at# SDRAM!( (ou"le data rates 2(RAMs are those which can transfer data on "oth edges of the cloc9 and their "andwidth is essentially dou"led for long "urst transfers. What ! $#$%&' C%+t&%//#&( A memory controller is a circuit which is interposed "etween the processor and the dynamic memory. 8#. 82.The processor must ta9e into account the delay in the response of the memory. What ! 0%*. 2uch modules are an assem"ly of se$eral memory chips on a separate small "oard that plugs $ertically into a single soc9et on the mother"oard. the memory controller has to pro$ide all the information needed to control the refreshing process. 7..

86.R5M cell. I There are no separate address lines. D#) +# )/a!h $#$%&'( Department of Information Technology @ SVS College of Engineering . 80. These chips use cell arrays "ased on the standard (RAM technology. and the remainder of the program is accessed relati$ely infrequently. What a&# th# )#at*&#! %) PROM( o o o o They are programmed directly "y the user. Ram"us requires specially designed memory chips. 87. What a&# RIMM!( R(RAM chips can "e assem"led in to larger modules called R%MMs.. %t in$ol$es only reading of stored data. 28. I %t has 86 data lines intended to transfer two "ytes of data at a time. What ! /%"a/ t' %) &#)#&#+"#( Analysis of programs shows that many instructions in localiHed areas of the program are executed repeatedly during some time period.. %t is an approach similar to ''.8*. %t can hold upto 80 R(RAMs. What a&# RDRAM!( R(RAMs are Ram"us (RAMs. This is referred to as locality of reference. What a&# th# !-#" a/ )#at*&#! %) D &#"t RDRAM!( I %t is a two channel Ram"us. /ircuitry needed to interface to the Ram"us channel is included on the chip. 1aster Less expensi$e More flexi"le.R5M technology. 22. What a&# th# t2% a!-#"t! %) /%"a/ t' %) &#)#&#+"#( D#) +# th#$. Multiple "an9s of cell arrays are used to access more than one word at atime. D#) +# ROM( %t is a non+$olatile memory. Two aspects of locality of reference are • temporal Page 1 2. A flash cell is "ased on a single transistor controlled "y trapped charge Dust li9e an ''. 2uch chips are 9nown as R(RAMs. 83..

2*.+. What ! 2& t#-. This approach is called load through or early restart and it reduces the processorEs waiting period . What ! 2& t# th&%*. t#"h+ 6*#(    (irect mapping Associati$e mapping 2et Associati$e mapping 26.• spatial Temporal aspect is that a recently executed instruction is li9ely to "e executed again $ery soon.a"5 %& "%-' . What a&# th# t2% 2a'! + 2h "h th# !'!t#$ *! +.h -&%t%"%/( 1or a write operation using write through protocol during 2& t# h tA the cache location and the main memory location are updated simultaneously. when the "loc9 containing this mar9ed word is to "e remo$ed from the cache to ma9e room for a new "loc9. 2&. 20. The num"er of hits stated as a fraction of all attempted access is called as hit rate.a"5 -&%t%"%/( 1or a write operation using this protocol during W& t# h tA the technique is to update only the cache location and to mar9 it as updated with an associated flag "it. and then the desired word in the cache is o$erwritten with the new information. What ! a h t( D#) +# h t &at#( A successful access to data in cache memory is called hit. o )rite+"ac9 or copy "ac9 technique. The main memory location of the word is updated later. W& t# $ !!A the "loc9 containing the addressed word is first "rought into the cache.h %& #a&/' &#!ta&t( )hen a read miss occurs for a system with cache the required word may "e sent to the processor as soon as it is read from the main memory instead of loading in to the cache. 2& t# $ !! A the information is written directly to the main memory. often called the dirty or modified "it. 23. 2#. "a"h# "a+ -&%"##0 )%& a 2& t# %-#&at %+( o )rite through technique. What a&# th# t'-#! %) $a-. What ! /%a0-th&%*. The spatial aspect is that instructions in close proximity to a recently executed instruction are also to "e executed soon. Department of Information Technology @ SVS College of Engineering Page 1! .

What ! th# )%&$*/a )%& "a/"*/at +. Rotational delay or latency is the amount of time that elapses after the head is positioned o$er the correct trac9 until the starting position of the addressed sector passes under the read4write head. 2ee9 time is the time required to mo$e the read4write head to the proper trac9. What ! 3 &t*a/ $#$%&' t#"h+ 6*#( Techniques that automatically mo$e program and data "loc9s into the physical main memory when they are required for execution are called as $irtual memory technique. 826 F 6 = 8.' th# -&%"#!!%& + a !'!t#$ 2 th t2% /#3#/! %) "a"h#!( ta$e =h8c8(8+h8 h2c2:(8+h8 (8+h2 M where h8=hit rate in L8 cache h2=hit rate in L2 cache /8=Time to access information in the L8 cache.2& "ytes. PART B Department of Information Technology @ SVS College of Engineering Page 1" . /2=Time to access information in the L2 cache.'t#!.# a""#!! t $# #1-#& #+"#0 .2& "ytes. Gence to ha$e memory capacity of 2.' th# -&%"#!!%&( ta$e=hc :(8+h M )here h =Git rate M=miss penalty /=Time to access information in the cache.&6 "ytes we need two 826 F 6 RAM chip. #. #8. 5ne 826 F 6 chip can store 8. th# a3#&a. th# a3#&a. D#) +# $ !! &at#( D#) +# $ !! -#+a/t'( %t is the num"er of misses stated as a fraction of attempted accesses. D#) +# a""#!! t $# )%& $a. 39. H%2 $a+' 12< A < RAM "h -! a&# +##0#0 t% -&%3 0# a $#$%&' "a-a" t' %) 2@9< ..# a""#!! t $# #1-#& #+"#0 .27. The extra time needed to "ring the desired information into the cache.+#t " 0 !5!( The sum of see9 time and rotational delay is called as access time for dis9s. What ! th# )%&$*/a )%& "a/"*/at +. ##. #2.

'xplain the internal organiHation of "it cells in a memory chip %nternal organiHation of memory chip 2tatic memories Asynchronous (RAM 2ynchronous (RAM UNIT ? INPUT B OUTPUT ORGANIZATION PART A Department of Information Technology @ SVS College of Engineering Page 2# . (iscuss a"out different types different types of R5M • • • • • • • • • • • • • • • • • • • • • %ntroduction R5M . 'xplain cache memory %ntroduction Mapping function (irect mapping Associati$e mapping 2et Associati$e mapping Replacement Algorithms #. 'xplain <irtual memory <irtual memory organiHation Ad$antages of $irtual memory Address translation &.R5M '.R5M ''. siHe.R5M 1lash memory 2. (iscuss speed. cost Memory hierarchy fig 'xplanation *.8.

t&at %+( Department of Information Technology @ SVS College of Engineering Page 21 %45 de$ice . Then the. What ! DMA( Transfer of a "loc9 of data directly "etween an external de$ice and main memory. without continuous inter$ention "y the processor is called (MA. 7. What a&# th# 3a& %*! $#"ha+ !$! )%& $-/#$#+t +. This technique is 9nown as cycle stealing. 0. What a&# 3#"t%&#0 +t#&&*-t!( To reduce the time in$ol$ed in the polling process.*! a&.( )ith this technique each program runs for a short period called a time slice. IBO %-#&at %+!(  . processor can immediately start executing the corresponding %2R. What ! t $# !/ " +. Wh#+ th# -& 3 /#. What ! . 3. What ! DMA "%+t&%//#&( (MA transfers are performed "y a control circuit that is part of the interface.&a$ "%+t&%//#0 IBO( %n program controlled %45 .# #1"#-t %+ a& !#!( An attempt to execute a pri$ileged instruction while in the user mode leads to a special type of interrupt called a pri$ilege exception. This circuit is 9nown as (MA controller. 2.( The processor originates most memory access cycles and the (MA controller can "e said to steal memory cycles from the processor. the processor repeatedly chec9s a status flag to achie$e the required synchroniHation "etween the processor and an input and output de$ice. 8.8. 6. a de$ice requesting an interrupt may identify itself directly to the processor. *.rogram controlled %45  %nterrupts  (MA &.the arrangement is called memory mapped %45. The schemes "ased on this approach are called $ectored interrupts. What ! -&%.. What ! "'"/# !t#a/ +. #. What ! $#$%&' $a--#0 IBO( )hen the %45 de$ices share the same address space. then another program runs for its time slice and so on.

Department of Information Technology @ SVS College of Engineering Page 22 . 88.*!( %n this. 8*.&%*t +# a+0 I+t#&&*-t S#&3 "# R%*t +#( 2u"routine or the su"program is the routine which could "e called "y another su"routine or main routine under program control.. What a&# th# %. What a&# th# )*+"t %+! %) t'. o .*!( %n this. What ! a!'+"h&%+%*! .$ide a storage "uffer for at least one word of data. all de$ices do not deri$e timing information from a common cloc9 line. %t uses handsha9e "etween the master and the sla$e.erforms any format con$ersion. 1. What a&# th# th&## t'-#! %) .#t2##+ !*.  /ontains status flags that can "e accessed "y the processor to determine whether the "uffer is full or empty.  /ontains address decoding circuitry."a/ IBO +t#&)a"#(  .C#"t 3#! %) USB( o 2imple o Low cost o 'asy to use o 2upports wide range of data transfer characteristics. Wh' 0% 2# +##0 DMA( (MA is used to transfer the "loc9 of data directly "etween an external de$ice and the main memory without the continuous inter$ention "y the processor. What ! !'+"h&%+%*! . What ! th# 0 ))#&#+"# .lug and play mode of operation 8#. %nterrupt 2er$ice Routine is called automatically on the occurrence of an interrupt which is predefined.*!#!( o Address "us o (ata "us o /ontrol "us 82.  -enerates the appropriate timing signals.  .%t is the process "y which the next de$ice "ecomes the "us master is selected and "us mastership is transferred to it. all de$ices deri$e timing information from a common cloc9 line. 8&.

21. de$ice or writes data through latch to output de$ice addressed.*!( The disad$antage of "us is that it creates a communication "ottlenec9. when a print command is gi$en. )hen the /.! is in$oled only at the "eginning and end of the transfer.1<. the processor identifies the request and transfer the control %nterrupt 2er$ice Routine (%2R to perform the tas9 and its resumes "ac9 with the useful tas9 whereas.# %) . What ! th# 0 !a03a+ta. %nterrupt Request CPU I / O SYSTEM %nterrupt Ac9 2@. 1or example. the command contains address of the de$ice. PART B 1.! wishes to read or write a "loc9 a data. Write notes on (i DM! Department of Information Technology @ SVS College of Engineering Page 23 . H%2 0%#! th# -&%"#!!%& ha+0/# a+ +t#&&*-t &#6*#!t( The processor instruct an %45 de$ice interface to acti$ate the interrupt request line as soon as it is ready for a data transfer. it gi$es control to %2R and resumes the wor9 "ac9 where as without %nterrupt the processor has to wait until the print document is transferred to the printer. according to the address.! reads data through "uffer from %4. the processor has to waste its time "y performing all the tas9. Gence (MA ha$e priority o$er the /.%th &#6*#!t a $#$%&' t&a+!)#&. the de$ice is selected. The data transfer is monitored "y (MA controller which is 9nown as (MA channel. it issues a command to the (MA channel "y sending read4 write operation. +t#&&*-t + t at#0 0ata t&a+!)#& %3#& t&a+!)#& *+0#& -&%. The /. The /."a/ I BO +t#&)a"#( )hen the /. Wh' 0%#! DMA ha3# -& %& t' %3#& th# CPU 2h#+ . which handles the tas9. num"er of words to "e read or written. %t transfer the request to %nterrupt ser$ice routin.! issues an % 45 command.! when "oth request a memory transfer. 22. 1=. What a&# th# )*+"t %+! %) a t'. in the interuupt initiated.&a$ 2 th%*t +t#&&*-t( %n the interrupt initiated data transfer. limiting the maximum input 4 output throughput and "andwidth limitation. address of % 45. then it performs other useful wor9. What ! th# a03a+ta.# %) *! +.

architecture.o allow transfer of a bloc. 2. his approach is called /irect "emory Access. (ii "us !rbitration %t is the process "y which the next de$ice "ecomes the "us master is selected and "us mastership is transferred to it. L !t th# 0 ))#&#+t t'-#! %) +t#&&*-t • • • • • • (efinition %nterrupt hardware 'na"ling and disa"ling interrupts Gandling multiple de$ices /ontrolling de$ice requests exceptions 9. E1-/a + D &#"t M#$%&' A""#!! Department of Information Technology @ SVS College of Engineering Page 24 . #%I  %eatures of 1CI  )se of 1CI bus in a computer system  1CI bus signal  !peration of the 1CI bus (%(I  SCSI I2! bus  SCSI bus operation  SCSI signals 3.  )S. Explain (%(I and #%I.of data directly between an external device and the main memory# without continuous intervention by the processor# a special control unit is provided.  %eatures of )S.  bus arbitration scheme * centrali'ed# distributed (iii #rinter $ #rocessor %ommunication  circuit diagram  explanation (i& '("  !b0ectives of )S.

W& t# !h%&t +%t#! %+ .*!#! (efinition 2ynchronous "us Asynchronous "us ???????????????????????????? Department of Information Technology @ SVS College of Engineering Page 25 .• • • • • • • • (efinition (MA registers Cus Ar"itration /entraliHed Ar"itration (istri"uted Ar"itration 5.