INDEX

S.NO

DATE

NAME OFTHE EXPERIMENT

VERIFICATION OF LOGIC GATES

ADDERS AND SUBTRACTORS

DESIGN OF ENCODERS AND DECODERS

DESIGN OF MULTIPLEXERS AND

DEMULTIPLEXER
DESIGN OF FLIP FLOPS

5
6

DESIGN OF SYNCHRONOUS AND

ASYNCHRONOUS COUNTER

CMOS INVERTER

SIGNATURE

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 1

EXP NO: 01

VERIFICATION OF LOGIC GATES

AIM:
To develop the source code for logic gates by using VHDL/VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.
LOGIC DIAGRAM:
AND GATE:
LOGIC DIAGRAM:

NOT GATE:
LOGIC DIAGRAM:

NOR GATE:
LOGIC DIAGRAM:

TRUTH TABLE:
A

Y=AB

0
0
1
1

0
1
0
1

0
0
0
1

TRUTH TABLE:

Y=A

0
0

0
1

TRUTH TABLE:

OR GATE:
LOGICDIAGRAM

NAND GATE:
LOGICDIAGRAM

XOR GATE:
LOGICDIAGRAM

TRUTH TABLE:

Y=A+B

0
0
1
1

0
1
0
1

0
1
1
1

TRUTH

TABLE

Y=(AB)

0
0
1
1

0
1
0
1

1
1
1
0

TRUTH

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 2

TABLE

Y=(A+B)

0
0
1
1

0
1
0
1

1
0
0
0
A

0
0
1
1

0
1
0
1

XNOR GATE:
LOGIC DIAGRAM:

TRUTH TABLE:
A

0
0
1
1

0
1
0
1

VERILOG SOURCE CODE:

module logicgates1(a, b, c);
input a;
input b;
OUTPUT: [6:0] c;
assign c[0]= a & b;
assign c[1]= a | b;
assign c[2]= ~(a & b);
assign c[3]= ~(a | b);
assign c[4]= a ^ b;
assign c[5]= ~(a ^ b);
assign c[6]= ~ a;
endmodule

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 3

1
0
0
1

0
1
1
0

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=======================================================================
==
*
Final Report
*
=======================================================================
==
Final Results
RTL Top Level Output File Name : logicgates.ngr
Top Level Output File Name
: logicgates
Output Format
: NGC
Optimization Goal
: Speed

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 4

Keep Hierarchy
: NO
Design Statistics
# IOs
:9
Cell Usage :
# BELS
:7
# INV
:1
# LUT2
:6
# IO Buffers
:9
# IBUF
:2
# OBUF
:7
=======================================================================
==
Device utilization summary:
--------------------------Selected Device : 3s400tq144-5
Number of Slices:
3 out of 3584 0%
Number of 4 input LUTs:
6 out of 7168 0%
Number of bonded IOBs:
9 out of 97 9%
=======================================================================
==
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Timing Summary:
--------------Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.985ns
Timing Detail:
-------------All values displayed in nanoseconds (ns)
=======================================================================
==
Timing constraint: Default path analysis
Total number of paths / destination ports: 13 / 7
------------------------------------------------------------------------Delay:
7.985ns (Levels of Logic = 3)
Source:
a (PAD)
Destination:
c<5> (PAD)
Data Path: a to c<5>

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 5

Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
7 0.715 1.201 a_IBUF (a_IBUF)
LUT2:I0->O
1 0.479 0.681 _n00021 (c_0_OBUF)
OBUF:I->O
4.909
c_0_OBUF (c<0>)
---------------------------------------Total
7.985ns (6.103ns logic, 1.882ns route)
(76.4% logic, 23.6% route)
RESULT:
Thus the outputs of Basic Logic Gates are verified by simulating and synthesizing the
VERILOG code.

EXP NO: 02
ADDERS AND SUBTRACTORS
AIM:
To develop the source code for adders and subtractors by using VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.
BASIC ADDERS & SUBTRACTORS:
FULL ADDER:
LOGIC DIAGRAM:

TRUTH TABLE:
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

SUM
0
1
1
0
1
0
0
1

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Page 6

CARRY
0
0
0
1
0
1
1
1

VERILOG SOURCE CODE:

module fulladddataflow(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
assign#2 p=a&b;
assign#2 q=b&c;
assign#2 r=c&a;
assign#4 sum=a^b^c;
assign#4carry =(p1 | p2) | p3;
endmodule

Simulation output:

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 7

Synthesis RTL Schematic:

Synthesis report:
=======================================================================
==
*
Final Report
*
=======================================================================
==
Device utilization summary:
--------------------------Selected Device : 3s400tq144-5
Number of Slices:
Number of 4 input LUTs:
Number of bonded IOBs:

1 out of 3584 0%
2 out of 7168 0%
5 out of 97 5%

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 8

=======================================================================
==
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Timing Summary:
--------------Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.824ns

FULL SUBSTRACTOR:
LOGIC DIAGRAM:

TRUTH TABLE:
A B C DIFFERENCE
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
1
0
0
1

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Page 9

BORROW
0
1
1
1
0
0
0
1

VERILOG SOURCE CODE:

module fulsubdataflow(a, b, cin, diff, borrow);
input a;
input b;
input c;
output diff;
output borrow;
wire abar;
assign abar= ~ a;
assign diff=a^b^c;
assign#2 p=abar&b;
assign#2 q=b&c;
assign#2 r=abar&c;
assign borrow =(p | q) |r;
endmodule

Simulation output:

Synthesis RTL Schematic:

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 10

Synthesis report:
=======================================================================
==
*
Final Report
*
=======================================================================
==
Device utilization summary:
--------------------------Selected Device : 3s400tq144-5
Number of Slices:
Number of 4 input LUTs:
Number of bonded IOBs:

1 out of 3584 0%
2 out of 7168 0%
5 out of 97 5%

=======================================================================
==
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Timing Summary:
---------------

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 11

Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.824ns

RESULT:
Thus the OUTPUTs of Adders,Subtractors Adders are verified by synthesizing and
simulating the VERILOG code.

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 12

EXP NO: 03
ENCODERS AND DECODERS
AIM:
To develop the source code for encoders and decoders by using VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.
ENCODER:
LOGIC DIAGRAM:

TRUTH TABLE:
D0 D1 D2 D3 D4 D5 D6 D7 X Y
1
0
0
0
0
0
0
0

0
1
0
0
0
0
0
0

0
0
1
0
0
0
0
0

0
0
0
1
0
0
0
0

0
0
0
0
1
0
0
0

VERILOG SOURCE CODE:

module encoderbehav(d, a,b,c);
input [7:0] d;
output x;
output y;
output z;
reg a,b,c;
always @ (d [7:0]) begin
a= d[4] | d[5] | d[6] | d[7];
b= d[2] | d[3] | d[6] | d[7];

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Page 13

0
0
0
0
0
1
0
0

0
0
0
0
0
0
1
0

0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

Z
0
1
0
1
0
1
0
1

c= d[1] | d[3] | d[5] | d[7];

end
endmodule

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=======================================================================
==
*
Final Report
*
=======================================================================
==
Device utilization summary:
--------------------------Selected Device : 3s400tq144-5
Number of Slices:
Number of 4 input LUTs:
Number of bonded IOBs:

2 out of 3584 0%
3 out of 7168 0%
11 out of 97 11%

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 14

=======================================================================
==
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Timing Summary:
--------------Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.760ns

DECODERS:
LOGIC DIAGRAM:

TRUTH TABLE:
A

Z(0)

Z(1)

Z(2)

Z(3)

VERILOG SOURCE CODE:

module decoderbehv(a, b, en, z);
input a;
input b;

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Page 15

input en;
output [3:0] z;
reg [3:0] z;
reg abar,bbar;
always @ (a,b,en) begin
z[0] = (abar&bbar&en);
z[1] = (abar&b&en);
z[2] = (a&bbar&en);
z[3] = (a&b&en);
end
endmodule

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=======================================================================
==
*
Final Report
*
=======================================================================
==

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 16

Device utilization summary:

--------------------------Selected Device : 3s400tq144-5
Number of Slices:
Number of 4 input LUTs:
Number of bonded IOBs:

2 out of 3584 0%
4 out of 7168 0%
7 out of 97 7%

=======================================================================
==
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Timing Summary:
--------------Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.858ns
RESULT:
Thus the OUTPUTs of Encoder and Decoder are verified by synthesizing and simulating
the VERILOG code.

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 17

EXP NO: 04
MULTIPLEXER AND DEMULTIPLEXER
AIM:
To develop the source code for multiplexer and demultiplexer by using VERILOG and
obtain the simulation, synthesis, place and route and implement into FPGA.
MULTIPLEXER:
LOGIC DIAGRAM:
TRUTH TABLE:
9

D1

1
2
8

D2

1
2
8

D3

1
2
8

S1

2
3
4
5

SELECT
INPUT
S1
S0
0
0
0
1
1
0
1
1

1
2
8

D0

S0

VERILOG SOURCE CODE:

module mux_behv(d, s0, s1, y);
input [3:0] d;
input s0;
input s1;
output y;
reg y;
reg s0bar,s1bar;
reg p,q,r,s;
always@(d or s0 or s1)
begin
p=(d[0]&sobar&s1bar);
q=(d[1]&sobar&s1);

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Page 18

OUTPUT
Y
D0
D1
D2
D3

r=(d[2]&so&s1bar);
s=(d[3]&so&s1);
endmodule

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=======================================================================
==
*
Final Report
*

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 19

=======================================================================
==
Device utilization summary:
--------------------------Selected Device : 3s400tq144-5
Number of Slices:
1 out of 3584 0%
Number of 4 input LUTs:
2 out of 7168 0%
Number of bonded IOBs:
7 out of 97 7%
=======================================================================
==
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Timing Summary:
--------------Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 8.138ns
DEMULTIPLEXER:
LOGIC DIAGRAM:

`
TRUTH TABLE:

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 20

1
2

S0

S1

D
1
1
1
1

2
3

Din

1
4
5

INPUT
S0
0
0
1
1

S1
0
1
0
1

Y0

2
3
1
4
5

Y1

2
3
1
4
5

Y2

2
3
1
4
5

Y3

Enable

VERILOG SOURCE CODE:

module demux_behv(s0, s1,d, y,e);
input s0;
input s1;
input d,e;
output [3:0] y;
reg [3:0] y;
reg s0bar,s1bar;
always@(d or s0 or s1)
begin
s0bar=~s0;
s1bar=~s1;
y[0]=(d&s0bar&s1bar&e);
y[1]=(d&s0bar&s1&e);
y[2]=(d&s0&s1bar&e);
y[3]=(d&s0&s1&e);
end
endmodule

Simulation output:

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Page 21

Y0
1
0
0
0

OUTPUT
Y1 Y2
0
0
1
0
0
1
0
0

Y3
0
0
0
1

Synthesis RTL Schematic:

Synthesis report:
======================================================================
===
*
Final Report
*
======================================================================
===
Device utilization summary:
--------------------------Selected Device : 3s400tq144-5
Number of Slices:
Number of 4 input LUTs:
Number of bonded IOBs:

2 out of 3584 0%
4 out of 7168 0%
7 out of 97 7%

======================================================================
===
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 22

Clock Information:
-----------------No clock signals found in this design
Timing Summary:
--------------Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.858ns
RESULT:
Thus the OUTPUTs of Multiplexers and Demultiplexers are verified by synthesizing and
simulating the VERILOG code.

EXP NO: 05
DESIGN OF FLIP FLOPS
AIM:
To develop the source code for flip flops by using VERILOG and Obtained the simulation,
synthesis, place and route and implement into FPGA.

SR FLIPFLOP:
LOGIC DIAGRAM:

TRUTH TABLE:

Q(t)

0
0
0
0
0
1
0
1
0
0
1
1
1
0
0lab)
Mallareddy college of engineering and technology-Mtech(vlsi
1
0
1
Page 23
1
1
0
1
1
1

Q(t+1)
0
0
1
X
1
0
1
X

1
2

1
2

CP
1

1
3

VERILOG SOURCE CODE:

Behavioral Modeling:
module srflipflop(s, r, clk, rst, q, qbar);
input s;
input r;
input clk;
input rst;
output q;
output qbar;
reg q,qbar;
always @ (posedge(clk) or posedge(rst)) begin
if(rst==1'b1) begin
q= 1'b0;qbar= 1'b1;
end
else if(s==1'b0 &&
r==1'b0)
begin
q=q; qbar=qbar;
end
else if(s==1'b0 &&
r==1'b1)
begin
q= 1'b0; qbar= 1'b1;
end
else if(s==1'b1 &&
r==1'b0)
begin
q= 1'b1; qbar= 1'b0;
end
else
begin
q=1'bx;qbar=1'bx;
end
end
endmodule

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 24

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=======================================================================
==
*
Final Report
*
=======================================================================
==
Final Results
RTL Top Level Output File Name : srff.ngr
Top Level Output File Name
: srff
Output Format
: NGC
Optimization Goal
: Speed

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 25

Keep Hierarchy
Design Statistics
# IOs
Macro Statistics :
# Registers
# 1-bit register

: NO
:6
:2
:2

Cell Usage :
# BELS
:3
# LUT2
:3
# FlipFlops/Latches
:2
# FDCE
:1
# FDPE
:1
# Clock Buffers
:1
# BUFGP
:1
# IO Buffers
:5
# IBUF
:3
# OBUF
:2
=======================================================================
==
Device utilization summary:
--------------------------Selected Device : 3s400tq144-5
Number of Slices:
Number of Slice Flip Flops:
Number of 4 input LUTs:
Number of bonded IOBs:
Number of GCLKs:

2 out of 3584 0%
2 out of 7168 0%
3 out of 7168 0%
6 out of 97 6%
1 out of 8 12%

=======================================================================
==
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+

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Page 26

clk
| BUFGP
|2 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: 3.529ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: No path found
Timing Detail:
-------------All values displayed in nanoseconds (ns)
=======================================================================
==
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 8 / 4
------------------------------------------------------------------------Offset:
3.529ns (Levels of Logic = 2)
Source:
r (PAD)
Destination:
qbar (FF)
Destination Clock: clk rising
Data Path: r to qbar
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
3 0.715 1.066 r_IBUF (r_IBUF)
LUT2:I0->O
2 0.479 0.745 _n00051 (_n0005)
FDPE:CE
0.524
qbar
---------------------------------------Total
3.529ns (1.718ns logic, 1.811ns route)
(48.7% logic, 51.3% route)
=======================================================================
==
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 2 / 2
------------------------------------------------------------------------Offset:
6.216ns (Levels of Logic = 1)
Source:
qbar (FF)
Destination:
qbar (PAD)
Source Clock:
clk rising
Data Path: qbar to qbar

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Page 27

Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FDPE:C->Q
1 0.626 0.681 qbar (qbar_OBUF)
OBUF:I->O
4.909
qbar_OBUF (qbar)
---------------------------------------Total
6.216ns (5.535ns logic, 0.681ns route)
(89.0% logic, 11.0% route)
JK FLIPFLOP:
LOGIC DIAGRAM:

1
2
8

1
2
8

TRUTH TABLE:

1
2

CP
1

Q(t)

Q(t+1)

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
1
1
1
0
1
0

VERILOG SOURCE CODE:

module jkff(j, k, clk, rst, q, qbar);
input j;
input k;
input clk;
input rst;
output q;
output qbar;
reg q;
reg qbar;
always @ (posedge(clk) or posedge(rst)) begin
if (rst==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else if (j==1'b0 && k==1'b0)
begin
q=q;

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Page 28

qbar=qbar;
end
else if (j==1'b0 && k==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else if (j==1'b1 && k==1'b0)
begin
q=1'b1;
qbar=1'b0;
end
else
begin
q=~q;
qbar=~qbar;
end
end
endmodule

Simulation output:

Synthesis RTL Schematic:

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 29

Synthesis report:
=======================================================================
==
*
Final Report
*
=======================================================================
==
Device utilization summary:
--------------------------Selected Device : 3s400tq144-5
Number of Slices:
Number of Slice Flip Flops:
Number of 4 input LUTs:
Number of bonded IOBs:
Number of GCLKs:

2 out of 3584 0%
2 out of 7168 0%
3 out of 7168 0%
6 out of 97 6%
1 out of 8 12%

=======================================================================
==
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 30

Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk
| BUFGP
|2 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
Minimum period: 2.085ns (Maximum Frequency: 479.513MHz)
Minimum input arrival time before clock: 3.529ns
Maximum output required time after clock: 6.280ns
Maximum combinational path delay: No path found
D FLIPFLOP:
LOGIC DIAGRAM:

TRUTH TABLE:

CP
1
3

1
2

Q(t)

Q(t+1)

0
0
1
1

0
1
0
1

0
1
0
1

VERILOG SOURCE CODE:

module dff(d, clk, rst, q, qbar);
input d;
input clk;
input rst;
output q;
output qbar;
reg q;
reg qbar;
always @ (posedge(clk) or posedge(rst)) begin
if (rst==1'b1)
begin
q=1'b0;
qbar=1'b1;
end

Mallareddy college of engineering and technology-Mtech(vlsi lab)

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else if (d==1'b0)
begin
q=1'b0;
qbar=1'b1;
end
else
begin
q=1'b1;
qbar=1'b0;
end
end
endmodule

Simulation output:

Synthesis RTL Schematic:

Synthesis report:

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 32

=======================================================================
==
*
Final Report
*
=======================================================================
==
Device utilization summary:
--------------------------Selected Device : 3s400tq144-5
Number of Slices:
Number of Slice Flip Flops:
Number of bonded IOBs:
Number of GCLKs:

1 out of 3584 0%
2 out of 7168 0%
5 out of 97 5%
1 out of 8 12%

=======================================================================
==
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk
| BUFGP
|2 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: 2.796ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: No path found
T FLIPFLOP:
LOGIC DIAGRAM:

TRUTH TABLE:

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 33

1
2
8

1
2
8

1
2

CP
1
2

Q(t)

Q(t+1)

0
0
1
1

0
1
0
1

0
1
1
0

VERILOG SOURCE CODE:

module tff(t, clk, rst, q, qbar);
input t;
input clk;
input rst;
output q;
output qbar;
reg q,qbar;
always @ (posedge(clk) or posedge(rst)) begin
if(rst==1'b1) begin
q= 1'b0;qbar= 1'b1;
end
else if (t==1'b0)
begin
q=q; qbar=qbar;
end
else
begin
q=~q; qbar=~qbar;
end
end
endmodule

Simulation output:

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 34

Synthesis RTL Schematic:

Synthesis report:
=======================================================================
==
*
Final Report
*
=======================================================================
==
Device utilization summary:

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 35

--------------------------Selected Device : 3s400tq144-5

Number of Slices:
Number of Slice Flip Flops:
Number of bonded IOBs:
Number of GCLKs:

1 out of 3584 0%
2 out of 7168 0%
5 out of 97 5%
1 out of 8 12%

=======================================================================
==
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk
| BUFGP
|2 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
Minimum period: 2.707ns (Maximum Frequency: 369.372MHz)
Minimum input arrival time before clock: 1.984ns
Maximum output required time after clock: 6.280ns
Maximum combinational path delay: No path found
RESULT:
Thus the OUTPUTs of Flip Flops are verified by synthesizing and simulating the
VERILOG code.

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 36

EXP NO: 06
SYNCHRONOUS AND ASYNCHRONOUS COUNTER
AIM:
To develop the source code for synchronous and asynchronous counter by using VERILOG
and obtain the simulation, synthesis, place and route and implement into FPGA.
SYNCHRONOUS COUNTER:
LOGIC DIAGRAM:

VERILOG SOURCE CODE:

module syncntr(clk, rst, q);
input clk;
input rst;
output [3:0]q;

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 37

reg [3:0]q;
reg [3:0]x=0;
always @ (posedge(clk) or posedge(rst))
begin
if (rst==1'b1)
begin
q=4'b0;
end
else
begin
x=x+1'b1;
end
q=x;
end
endmodule

Simulation output:

Synthesis RTL Schematic:

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 38

Synthesis report:
=======================================================================
==
*
Final Report
*
=======================================================================
==
Device utilization summary:
--------------------------Selected Device : 3s400tq144-5
Number of Slices:
Number of Slice Flip Flops:
Number of 4 input LUTs:
Number of bonded IOBs:
Number of GCLKs:

2 out of 3584 0%
4 out of 7168 0%
2 out of 7168 0%
6 out of 97 6%
1 out of 8 12%

=======================================================================
==
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk
| BUFGP
|4 |
-----------------------------------+------------------------+-------+

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 39

Timing Summary:
--------------Speed Grade: -5
Minimum period: 3.388ns (Maximum Frequency: 295.186MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 6.318ns
Maximum combinational path delay: No path found
ASYNCHRONOUS COUNTER:
LOGIC DIAGRAM:

VERILOG SOURCE CODE:

module asyncntr(clk, rst, s, q);
input clk;
input rst;
input s;
output [3:0] q;
reg [3:0] q;
reg [3:0] x=0;
always @ (posedge(clk) or posedge(rst))
begin
if (rst==1'b1)
begin
q=4'b0;
end
else if (s==1'b0)
begin
x=x-1'b1;
end
else if (s==1'b1)
begin
x=x+1'b1;
end

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 40

q=x;
end
endmodule

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=======================================================================
==
*
Final Report
*
=======================================================================
==
Device utilization summary:
--------------------------Selected Device : 3s400tq144-5
Number of Slices:
Number of Slice Flip Flops:
Number of bonded IOBs:
Number of GCLKs:

4 out of 3584 0%
7 out of 7168 0%
6 out of 97 6%
1 out of 8 12%

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 41

=======================================================================
==
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk
| BUFGP
|2 |
t1/qbar:Q
| NONE
|2 |
t2/qbar:Q
| NONE
|2 |
t3/qbar:Q
| NONE
|1 |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST
with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to
the clock signals to help prevent skew problems.
Timing Summary:
--------------Speed Grade: -5
Minimum period: 2.733ns (Maximum Frequency: 365.925MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 6.280ns
Maximum combinational path delay: No path found
RESULT:
Thus the OUTPUTs of Synchronous and Asynchronous counter are verified by
synthesizing and simulating the VERILOG code.

Mallareddy college of engineering and technology-Mtech(vlsi lab)

Page 42