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Application Note AN4149

**Design Guidelines for Quasi-Resonant Converters Using KA5Q-series Fairchild Power Switch (FPSTM)
**

Abstract

In general, a Quasi-Resonant Converter (QRC) shows lower EMI and higher power conversion efficiency compared to the conventional hard switched converter with a fixed switching frequency. Therefore, it is well suited for color TV applications that are noise sensitive. This application note presents practical design considerations of Quasi-Resonant Converters for color TV applications employing KA5Qseries FPSTM (Fairchild Power Switch). It includes designing the transformer, output filter and sync network, selecting the components and closing the feedback loop. The step-by-step design procedure described in this application note will help engineers design quasi-resonant converter easily.

DR(n) NS(n) CO(n) Np DR1 NS1 CO1

LP(n)

VO(n)

CP(n) LP1

VO1 (B+)

CP1

AC IN

KA5Q-series

Sync

Drain Cr GND NS2 DR2 LP2

PWM

VO2 (Sound)

VFB CB

Vcc

Ra Ca

Da Na

CO2

CP2

Linear regulator

Rd R3 R1

MCU

DSY

Rbias

Rstr CSY

RSY1

H11A817A

RSY2 KA431

RF

CF R2

R1

Q

Picture ON

Figure 1. Basic Quasi Resonant Converter Using KA5Q-series (Color TV Application)

1. Introduction

The KA5Q-series FPSTM (Fairchild Power Switch) is an integrated Pulse Width Modulation (PWM) controller and a Sense FET specifically designed for quasi-resonant off-line Switch Mode Power Supplies (SMPS) with minimal external components. Compared with a discrete MOSFET and PWM controller solution, it can reduce total cost, component count, size and weight while simultaneously increasing efficiency,

system reliability and productivity. Figure 1 shows the basic schematic of a quasi-resonant converter using KA5Q-series for the color TV application, which also serves as the reference circuit for the design process described in this paper. Vo1 is the output voltage that powers horizontal deflection circuit while Vo2 is the output voltage that supplies power to the Micro Controller Unit (MCU) through a linear regulator. Rev. 1.0.0

©2005 Fairchild Semiconductor Corporation

the maximum input power is given by Po P in = -----E ff (1) 8. the load occupying factor for each output is defined as Po ( n ) K L ( n ) = -----------Po (2) 9. .Line voltage range (Vlinemin and Vlinemax). fL .7~0. . a design procedure is presented using the schematic of Figure 1 as a reference. Determine the reflected output voltage (VRO) 4. [STEP-2] Determine DC link capacitor (CDC) and the DC link voltage range. which is typically about 0. Step-by-step Design Procedure 1. Choose the secondary side rectifier diodes It is typical to select the DC link capacitor as 2-3uF per watt of input power for universal input range (85-265Vrms) and 1uF per watt of input power for European input range (195V265Vrms). Determine the output capacitors V DC 12. It is assumed that Vo1 is the reference output that is regulated by the feedback control in normal operation. Design the synchronization network min = 2 ⋅ ( V line min 2 P in ⋅ ( 1 – D ch ) ) – ----------------------------------C DC ⋅ f L (3) 13. KL(1)=1. Determine the transformer primary side inductance (Lm) 5.Maximum output power (Po).8~0. The detailed design procedures are as follows: [STEP-1] Define the system specifications . For single output SMPS. Determine the proper core and the minimum primary turns (Npmin) 7.2. Determine the startup resistor For multiple output SMPS. Determine the wire diameter for each winding Is the winding window area (Aw) enough ? N Y Is it possible to change the core ? N Y where Po(n) is the maximum output power for the n-th output. . Pin. Define the system specifications (Vlinemin. Determine the number of turns for each output In this section. set Eff = 0.AN4149 APPLICATION NOTE 2. If no reference data is available. Po . Eff ) 2. ©2005 Fairchild Semiconductor Corporation 2 .Estimated efficiency (Eff) : The power conversion efficiency must be estimated to calculate the maximum input power. With the estimated efficiency. Design the voltage drop circuit for burst operation where CDC is the DC link capacitor and Dch is the duty cycle ratio for CDC to be charged as defined in Figure 3. 10.75 for low voltage output applications and Eff = 0.85 for high voltage output applications. Vlinemin and fL are specified in STEP-1.Line frequency (fL). the minimum DC link voltage is obtained as 11. Determine DC link capacitor (CDC) and DC link voltage range 3. Vlinemax. In the case of Color TV applications. Figure 2 illustrates the design flow chart. Choose proper FPS considering input power and Idspeak 6. With the DC link capacitor chosen. The maximum DC link voltage is given as 14. the typical efficiency is 80~83%. Flow Chart of Design Procedure where Vlinemax is specified in STEP-1. Design the feedback control circuit Design finished V DC max = 2V line max (4) Figure 2.

secondary diode current and the MOSFET drain voltage of a Quasi Resonant Converter. DC Link Voltage Waveform Figure 5 shows the typical waveforms of MOSFET drain current. determine VRO by a trade-off between the voltage margin of the MOSFET and the efficiency. It is typical to set fsmin to be around 25kHz. By increasing VRO. Typical Waveforms of Quasi-Resonant Converter + Cr + Vds - To determine the primary side inductance (Lm). Therefore. the DC link voltage (VDC) together with the output voltage reflected to the primary (VRO) are imposed on the MOSFET. the KA5Qseries is designed to turn on the MOSFET when the drain voltage reaches its minimum voltage (VDC -VRO). EMI can be reduced. However. The typical value for TF is 2-2. Typically. However. In order to minimize the switching loss. However. By increasing fsmin. this increases the voltage stress on the MOSFET as shown in Figure 4. the following variables should be determined beforehand : • The minimum switching frequency (fsmin) : The minimum switching frequency occurs at the minimum input voltage and full load condition and should be higher than the minimum switching frequency of FPS (20kHz). During TOFF.APPLICATION NOTE AN4149 [STEP-4] Determine the transformer primary side inductance (Lm) DC link voltage Minimum DC link voltage T1 Dch = T1 / T2 = 0. Therefore. The Typical Waveform of MOSFET Drain Voltage for Quasi Resonant Converter ©2005 Fairchild Semiconductor Corporation .5us. this results in increased switching losses. the current flows through the secondary side rectifier diode and the MOSFET drain voltage is clamped at (VDC+VRO). V ds V DC +V RO V RO V RO V DC V DC -V RO T ON + VDC VRO FPS Drain T OFF TS TF + Lm VO - Figure 5. Ids [STEP-3] Determine the reflected output voltage (VRO) Figure 4 shows the typical waveforms of the drain voltage of quasi-resonant flyback converter. VRO is set as 120~180V so that Vdsnorm is 490~550V (75~85% of MOSFET rated voltage). • The falling time of the MOSFET drain voltage (TF) : As shown in Figure 5. the capacitive switching loss and conduction loss of the MOSFET are reduced. When the secondary side current reduces to zero. the MOSFET drain voltage fall time is half of the resonant period of the MOSFET’s effective output capacitance and primary side inductance. 3 GND VRO VRO Vdsnom VDC max 0V VRO Vdsnom VRO Figure 4.2 T2 Figure 3. the transformer size can be reduced. By increasing TF. The maximum nominal voltage across the MOSFET (Vdsnom) is V ds nom ID = V DC max + V RO (5) where VDCmax is as specified in equation (4). this forces an increase of the resonant capacitor (Cr) resulting in increased switching losses. determine fsmin by a trade-off between switching losses and transformer size. the drain voltage begins to drop by the resonance between the effective output capacitor of the MOSFET and the primary side inductance (Lm). When the MOSFET is turned off.

(6) and (7).25~0. the maximum peak current and RMS current of the MOSFET in normal operation are obtained as I ds peak NP L m I ds 6 .5A 12. Since the core is saturated at low flux density as the temperature goes high. VDCmin and Dmax are specified in equations (1). Table 1 shows the lineups of KA5Q-series with rated output power and pulse-by-pulse current limit. respectively and fsmin is the minimum switching frequency. consider the high temperature characteristics.28A 7. Then. NP L m I LIM 6 = -------------------. The the maximum flux density swing in normal operation is related to the hysteresis loss in the core while the maximum flux density in transient is related to the core saturation.6A 6. Figure 7 shows the typical characteristics of ferrite core from TDK (PC40). Ae is the cross-sectional area of the core in mm2 as shown in Figure 6 and Bmax is the maximum flux density in tesla.6A 3. where VDCmin is specified in equation (3) and VRO is determined in STEP-3.35~0. the transformer should be designed not to be saturated when the MOSFET drain current reaches ILIM . the minimum number of turns for the transformer primary side to avoid the over temperature in the core is given by min where Pin. use ∆B =0.88A Table 1. With the resulting maximum peak drain current of the MOSFET (Idspeak) from equation (8). Since the MOSFET drain current exceeds Idspeak and reaches ILIM in a transient or fault condition.04A Typ 5A 3. Once Lm is determined. consider the maximum flux density swing in normal operation (∆B) as well as the maximum flux density in transient (Bmax). (3). Therefore. choose the proper FPS whose pulse-by-pulse current limit level (ILIM) is higher than Idspeak.30 T. With the chosen core.92A 5.⋅ I ds 3 min (8) I ds rms (9) where Lm is specified in equation (7). the maximum flux density (Bmax) when drain current reaches ILIM should be also considered as min where VDCmin. Dmax and Lm are specified in equations (3). FPS Lineups with Rated Output Power Ae (mm2) Figure 6. the primary side inductance is obtained as Lm ( V DC ⋅ D max ) = --------------------------------------------min 2 ⋅ fs ⋅ P in min 2 (7) Table 2 shows the commonly used cores for C-TV application for different output powers.96A where Lm is specified in equation (7). Ae is the crosssectional area of the transformer core in mm2 as shown in Figure 6 and ∆B is the maximum flux density swing in tesla.× 10 = ------------------------∆ BA e peak (10) V DC D max = ----------------------------------min Lm fs = D max peak ------------. The primary turns should be determined as less than Npmin values obtained from equation (10) and (11). If there is no reference data. the maximum duty cycle is calculated as V RO min D max = ------------------------------------⋅ ( 1 – fs × TF ) min V RO + V DC (6) [STEP-6] Determine the proper core and the minimum primary turns. When designing the transformer.× 10 B max A e (11) Maximum Output Power PRODUCT 230Vac ±15% 85~ 265Vac ILIM Min 4. Idspeak is the peak drain current specified in equation (8).4A 3.4A 5. there should be some margin for ILIM when choosing the proper FPS device. If there is no reference data.AN4149 APPLICATION NOTE After determining fsmin and TF. and (6).4 T. KA5Q0740RT 90 W (85~170Vac) KA5Q0565RT 75 W 60 W 85 W 120 W 170 W 210 W KA5Q0765RT 100 W KA5Q1265RT 150 W KA5Q1265RF 210 W KA5Q1565RF 250 W Aw (mm2) 10.5A 5A 6A 8A Max 5. respectively and fsmin is the minimum switching frequency. ILM is the pulse-bypulse current limit.12A 11. Since FPS has ± 12% tolerance of ILIM.08A 4. use Bmax =0.72A 8. [STEP-5] Choose the proper FPS considering input power and peak drain current. Window Area and Cross Sectional Area 4 ©2005 Fairchild Semiconductor Corporation .

The sync threshold voltage is also reduced from 2. It is also assumed that the linear regulator is connected to Vo2 to supply a stable voltage for MCU. Once KA5Q-series enters into standby mode. It is assumed that Vo1 is the reference output which is regulated by the feedback control in normal operation. Vcc voltage is hysteresis controlled between 11V and 12V as shown in Figure 9. Commonly Used Cores for C-TV Applications Figure 8. calculate the turns ratio (n) between the primary winding and reference output (Vo1) winding as a reference V R0 n = ------------------------V o1 + V F1 (12) . Typical B-H Characteristics of Ferrite Core (TDK/PC40) Output Power 70-100W 100-150W 150-200W Core EER35 EER40 EER42 EER49 + VO1 - Table 2.6V to 1.3V in burst mode. NS(n) + VF(n) DR(n) + VO(n) - 200 100 0 0 800 M agnetic field H (A/m) 1600 VRO + Ra Vcc + . First. Then.6 (15) (13) ©2005 Fairchild Semiconductor Corporation 5 .Vcc winding design : KA5Q-series drops all the outputs including the Vcc voltage in standby mode in order to minimize the power consumption. The number of turns for the other output (n-th output) is determined as Vo ( n ) + VF ( n ) N s ( n ) = --------------------------------⋅ N s1 V o1 + V F1 ( 14 ) 500 60 ℃ 100 ℃ 400 Flux density B (mT) 300 where Vo(n) is the output voltage and VF(n) is the diode (DR(n)) forward voltage drop of the n-th output. determine the proper integer for Ns1 so that the resulting Np is larger than Npmin as N p = n ⋅ N s1 > N p min ( 11 + 12 ) ⁄ 2 ------------------------------. design the Vcc voltage to be around 24V in normal operation for proper quasi-resonant switching in standby mode as can be observed by where VRO is determined in STEP-3 and Vo1 is the reference output voltage and VF1 is the forward voltage drop of diode (DR1).3 ------24 2.≅ 1. respectively.APPLICATION NOTE AN4149 M agnetization Curves (typical) M aterial :PC40 25 ℃ where n is obtained in equation (12) and Np and Ns1 are the number of turns for the primary side and the reference output. Therefore. Simplified Diagram of the Transformer [STEP-7] Determine the number of turns for each output Figure 8 shows the simplified diagram of the transformer.VFa + N a Da NS1 Np NS2 + VF2 DR2 VO2 + + VF1 DR1 Linear Regulator Figure 7.

If not. ©2005 Fairchild Semiconductor Corporation . PSR scheme regulates the output voltage indirectly by controlling the Vcc voltage without an optocoupler. 10 Startup Resistor and Vcc Auxiliary Circuit In general. the maximum approximate power dissipation in Rstr is obtained as max⎞ 2 2 max⎞ ⎛ ⎛V +V ⋅V 2 2⋅V ⎜ ⎝ line ⎟ ⎠ start 1 start line -⎟ . The startup resistor should be chosen so that Isupavg is larger than the maximum startup current (200uA). Initially. If PSR is used. switched mode power supply employs an error amplifier and an opto-coupler to regulate the output voltage.6V 1.6V 3. The maximum startup time is determined as T str max where VFa is the forward voltage drop of Da as defined in Figure 8. V start = C a ⋅ -------------------------------------------------avg max ( I sup – I start ) ( 18 ) Where Ca is the Vcc capacitor and Istartmax is the maximum startup current (200uA) of FPS. KA5Q-series has an internal error amplifier with a fixed reference voltage of 32. the current supplied through the startup resistor (Rstr) can charge the capacitors Ca1 and Ca2 while supplying startup current to FPS.AN4149 APPLICATION NOTE Vcc C DC 12V 11V Normal mode Vsync Standby mode AC line R str Vcc Ra Da I sup KA5Q-series 4. Because some protections are implemented as latch mode. However. set Vcc to 32.⋅ ----------= ------------------------------------. The startup resistor should have a proper dissipation rating based on the value of Pstr. Once the startup resistor (Rstr) is determined.⋅ N s1 N a = ------------------------V o1 + V F1 ( turns ) ( 16 ) .– ---------------⎜ π 2 ⎟ R str ⎝ ⎠ I sup ( 17 ) where Vlinemin is the minimum input voltage. the current required by FPS is supplied from the transformer’s auxiliary winding. Primary Side Regulation (PSR) can be used for a low cost design if output regulation requirements are not very tight. Vstart is the start voltage (15V) of FPS and Rstr is the startup resistor. AC startup is typically used to provide a fast reset. 6 ( 19 ) where Vlinemax is the maximum input voltage. Therefore.5V. Vcc can not be charged up to the start voltage and FPS will fail to start up. Then. FPS consumes only startup current (max 200uA) before it begins switching.⋅ ⎜ --------------------------------------------------------------. When Vcc reaches a start voltage of 15V (VSTART). After determining Vcc voltage in normal operation. and the current consumed by FPS increases. Burst operation in standby mode Figure.– ---------------------------------------------------------------P = ----------str R str ⎜ π 2 ⎟ ⎝ ⎠ [STEP-8] Determine the startup resistor Figure 10 shows the typical startup circuit for KA5Q-series. which is specified in STEP-1.6V 2.Startup resistor (Rstr) : The average of the minimum current supplied through the startup resistor is given by avg min ⎛ 2⋅V ⎞ V line start⎟ 1 ⎜ .3V Ca Figure 9. FPS begins switching. the number of turns for the Vcc auxiliary winding (Na) is obtained as V cc + V Fa .5V for PSR applications.

In that case. For high current output. Vo(n) is the output voltage of the n-th output and VF(n) is the diode (DR(n)) forward voltage drop. VRO is specified in STEP-3 and KL(n) is the load occupying factor for n-th output defined in equation (2). In this table.2 for multiple output applications. Typically the fill factor is 0. The current density is typically 5A/mm2 when the wire is long (>1m). When the wire is short with a small number of turns.3 ⋅ V D ( n ) I F > 1. where Dmax and Idsrms are specified in equations (6) and (9). If the required window (Awr) is larger than the actual window area (Aw).⋅ ------------------------------------( Vo ( n ) + VF ( n ) ) D max (24) (25) I sec ( n ) rms = I ds rms ( 20 ) where VRRM is the maximum reverse voltage and IF is the average forward current of the diode. A quick selection guide for the Fairchild Semiconductor rectifier diodes is given in Table 3. Sometimes it is impossible to change the core due to cost or size constraints. The required winding window area (Awr) is given by A wr = A c ⁄ K F (21) Ultra Fast Recovery Diode Products EGP10B UF4002 EGP20B EGP30B FES16BT EGP10C EGP20C EGP30C FES16CT EGP10D UF4003 EGP20D EGP30D FES16DT EGP10F EGP20F EGP30F EGP10G UF4004 VRRM 100 V 100 V 100 V 100 V 100 V 150 V 150 V 150 V 150 V 200 V 200 V 200 V 200 V 200 V 300 V 300 V 300 V 400 V 400 V 400 V 400 V 600 V 600 V 600 V 600 V 800 V 1000 V IF 1A 1A 2A 3A 16 A 1A 2A 3A 16 A 1A 1A 2A 3A 16 A 1A 2A 3A 1A 1A 2A 3A 1A 1A 2A 3A 1A 1A trr 50 ns 50 ns 50 ns 50 ns 35 ns 50 ns 50 ns 50 ns 35 ns 50 ns 50 ns 50 ns 50 ns 35 ns 50 ns 50 ns 50 ns 50 ns 50 ns 50 ns 50 ns 75 ns 75 ns 75 ns 75 ns 75 ns 75 ns Package DO-41 DO-41 DO-15 DO-210AD TO-220AC DO-41 DO-15 DO-210AD TO-220AC DO-41 DO-41 DO-15 DO-210AD TO-220AC DO-41 DO-15 DO-210AD DO-41 DO-41 DO-15 DO-210AD DO-41 DO-41 DO-15 DO-210AD TO-41 TO-41 where Ac is the actual conductor area and KF is the fill factor. VRO is specified in STEP-3.2~0. Check if the winding window area of the core. go back to the STEP-6 and change the core to a bigger one.APPLICATION NOTE AN4149 [STEP-9] Determine the wire diameter for each winding based on the RMS current of each output. The typical ©2005 Fairchild Semiconductor Corporation max. Do not use wire with a diameter larger than 1 mm to avoid severe eddy current losses as well as to make winding easier. [STEP-10] Choose the proper rectifier diodes in the secondary side based on the voltage and current ratings.15~0.5 ⋅ I D ( n ) rms The RMS current of the n-th secondary winding is obtained as V RO ⋅ K L ( n ) 1 – D max ---------------------. voltage and current margins for the rectifier diode are as follows V RRM > 1. which reduces the primary side inductance (Lm) and the minimum number of turns for the primary (Npmin) as can be seen in equation (7) and (10). Fairchild Diode Quick Selection Table where KL(n). VF(n) is the diode (DR(n)) forward voltage drop. EGP20G EGP30G UF4005 EGP10J EGP20J EGP30J UF4006 UF4007 The maximum reverse voltage and the rms current of the rectifier diode (DR(n)) of the n-th output are obtained as V DC ⋅ ( Vo ( n ) + VF ( n ) ) V D ( n ) = V o ( n ) + --------------------------------------------------------------V RO ID ( n ) rms max ( 22 ) ( 23 ) = I ds rms V RO K L ( n ) 1 – D max ---------------------. (4). reduce VRO in STEP-3 or increase fsmin. a current density of 6-10 A/mm2 is also acceptable. (6) and (9). Aw (refer to Figure 6) is enough to accommodate the wires. it is recommended using parallel windings with multiple strands of thinner wire to minimize skin effect.⋅ ------------------------------------( Vo ( n ) + VF ( n ) ) D max rms Table 3. trr is the maximum reverse recovery time.25 for single output applications and 0. VDC Dmax and Ids are specified in equations (2). 7 . respectively. Vo(n) is the output voltage of the n-th output.

respectively and VF(n) is the diode (DR(n)) forward voltage drop. To minimize the MOSFET switching loss.AN4149 APPLICATION NOTE [STEP-11] Determine the output capacitors considering the voltage and current ripple. Dmax and Idspeak are specified in equations (2).⋅ ---------------------------------⎞ T Q = R SY2 ⋅ C SY ⋅ ln ⎛ -------⎝ 2. respectively and Ceo is the effective MOSFET output capacitance (Coss+Cr). The output of the sync detect comparator (CO) becomes high when the sync voltage (Vsync) exceeds 4. Typically. choose the sync capacitor (CSY) so that TF is same as TQ as shown in Figure 12. In this technique. Sometimes it is impossible to meet the ripple specification with a single output capacitor due to the high ESR of the electrolytic capacitor. The basic waveforms of a quasi-resonant converter are shown in Figure 12. KL(n). additional L-C filter stages (post filter) can be used to reduce the ripple on the output.6V. The ripple current of the n-th output capacitor (Co(n)) is obtained as rms Np KA5Q-series Sync comparator N s1 V o1 Lm Drain I cap ( n ) = ( ID ( n ) rms 2 + 2 ) – Io ( n ) (26) 4. Choose the voltage divider RSY1 and RSY2 so that the peak value of sync voltage (Vsyncpk) is lower than the OVP threshold voltage (12V) in order to avoid triggering OVP in normal operation. The MOSFET is turned on at the falling edge of the sync detect comparator output (CO). 11 Synchronization Circuit The peak value of the sync signal is determined by the voltage divider network RSY1 and RSY2 as V sync pk R SY2 -⋅V = --------------------------------R SY1 + R SY2 cc ( 28 ) [STEP-12] Design the synchronization network. In those cases. Vsyncpk is set to 8~10V. VRO is specified in STEP-3. The external capacitor lowers the rising slope of drain voltage. TF and TQ are given. KA5Q-series employs a quasi resonant switching technique to minimize the switching noise as well as switching loss. V sync R SY1 C SY R SY2 Figure.6/2. The voltage ripple on the n-th output is given by I D I peak Cr Ids GND + V ds - Na R cc Da D SY o ( n ) max ds RO C ( n ) L ( n ) ∆ V o ( n ) = -------------------------+ ---------------------------------------------------------.6V Sync Vcc CO where Io(n) is the load current of the n-th output and ID(n)rms is specified in equation (23). the MOSFET should be turned on when the drain voltage reaches its minimum value as shown in Figure 12. as T F = π ⋅ L m ⋅ C eo R SY2 V cc . a capacitor (Cr) is added between the MOSFET drain and source as shown in Figure 11. which reduces the EMI caused by the MOSFET turn-off. Ns and Na are the number of turns for the output winding and Vcc winding. Rc(n) is the effective series resistance (ESR) of the n-th output capacitor.(27) Co (n ) fs min V R K ( Vo ( n ) + VF ( n ) ) Ca where Co(n) is the capacitance. respectively. To synchronize the Vsync with the MOSFET drain voltage. Io(n) and Vo(n) are the load current and output voltage of the n-th output.6V and low when the Vsync reduces below 2. The ripple current should be smaller than the maximum ripple current specification of the capacitor. The optimum MOSFET turn-on time is indirectly detected by monitoring the Vcc winding voltage as shown in Figure 11 and 12. ©2003 Fairchild Semiconductor Corporation 8 . (6) and (8) respectively.6 R SY1 + R SY2⎠ (29) (30) where Lm is the primary side inductance of the transformer.

Once FPS enters into burst mode. Vcc decreases. it resumes switching with a predetermined peak drain current until Vcc reaches 12V. If R3 is small enough to make the reference pin voltage of KA431 higher than 2. Typical Feedback Circuit to Drop Output Voltage in Standby Mode [STEP-14] Design the feedback control circuit.5 ⋅ ⎛ --------------------⎞ ⎝ R2 ⎠ (31) VO2 VO1 (B+) RD Rbias R1 CF C R Linear Regulator M icom R3 RF D1 Q1 Picture ON KA431 A R2 In standby mode. In this way. Once FPS stops switching. Therefore. the feedback loop can be easily implemented with a one-pole and one-zero compensation circuit. The current control factor of FPS. Burst Operation Waveforms To minimize the power consumption in the standby mode. and when Vcc reaches 11V. Vcc is hysteresis controlled between 11V and 12V in the burst mode operation. all the output voltages as well as effective switching frequencies are reduced as shown in Figure 13. Since the KA5Q-series employs current mode control as shown in Figure 15.6V 2.APPLICATION NOTE AN4149 Vds Assuming that both Vo1 and Vo2 drop to half of their normal values. K is defined as 9 . which couples R3 and D1 to the reference pin of KA431. the switching operation is terminated again until Vcc reduces to 11V. When Vcc reaches 12V. KA5Q-series employs burst operation. Figure 13. Under normal operation. the picture on signal is disabled and the transistor Q1 is turned off. only Vo1 is regulated by the feedback circuit in normal operation and is determined as V o1 R1 + R2 = 2.5 ⋅ ( R 1 + R 2 ) – ( R 2 ⋅ V 01 ⁄ 2 ) (32) VDC Vsync TF Vovp (12V) Vsyncpk VFB 1V 4. 12 Synchronization Waveforms Normal Mode Standby Mode [STEP-13] Design voltage drop circuit for the burst operation.5 ) ⋅ R 1 ⋅ R 2 R 3 = ----------------------------------------------------------------------------2.5V. which decouples R3 and D1 from the feedback network. Figure 14 shows the typical output voltage drop circuit for C-TV applications.6V Ids Ibpk CO TQ Vcc MOSFET Gate 12V ON ON 11V Figure. the maximum value of R3 for proper burst operation is given by VRO VRO ( V 02 ⁄ 2 – 0. the picture on signal is applied and the transistor Q1 is turned on. the current through the opto LED pulls down the feedback voltage (VFB) of FPS and forces FPS to stop switching. ©2005 Fairchild Semiconductor Corporation Figure 14.7 – 2.

Therefore. the low frequency control-to-output transfer function is proportional to the parallel combination of all load resistance.8kΩ.⋅ ---------------------------------------------------------= ---------------------------------------------------1 + s ⁄ wp 2 ( 2V RO + v DC ) fp ( 34 ) 20 dB where VDC is the DC input voltage. w pc = -------------R1 RD CF RF CF RB CB ( 35 ) Figure 15. adjusted by the square of the turns ratio. Po is specified in STEP-1 and K is specified in equation (33). Vo1 is the reference output voltage. VRO is specified in STEP-3. The feedback compensation network transfer function of Figure 15 is obtained as RB CB CF RF R1 KA431 R2 Ipk MOSFET current ˆ w i 1 + s ⁄ w zc v FB ---.= . w rz = ---------------------------------------. In order to express the small signal AC transfer functions.s ⋅ 1 + s ⁄ w pc v o1 R B ⋅ CTR 1 1 where w i = -----------------------. the small signal variations of feedback voltage (vFB) and ˆFB and v ˆo1. Additionally. which is defined as Vo12/Po. The gain is highest at the high input voltage condition and the RHP zero is lowest at the low input voltage condition. The pole and zeros of equation (34) are defined as RL ( 1 – D ) 1 (1 + D) w z = ------------------. ILIM is the current limit of the FPS and VFBsat is the internal feedback saturation voltage. CTR is the current transfer ratio of opto coupler and R1... which is typically 2. the control-to-output transfer function using current mode control is given by ˆ v o1 G vc = -------ˆ v FB and RB is the internal feedback bias resistor of FPS. w zc = -------------. controlled output voltage (vo1) are introduced as v vo1 FPS vFB iD CTR :1 vbias RD ibias Rbias When the converter has more than one output. Figure 17 shows the variation of a quasi-resonant flyback converter’s control-to-output transfer function for different loads. RL is the effective total load resistance of the controlled output. D is the duty cycle of the FPS.and w p = -----------------2 R c1 C o1 R L C o1 DL m ( N s1 ⁄ N p ) 2 fp 0dB High input voltage fz frz fz frz L ow input voltage -20 dB -40 dB 1H z 10H z 100Hz 1kH z 10k Hz 100kHz Figure 16. Because the RHP zero reduces the phase by 90 degrees.5V. the crossover frequency should be placed below the RHP zero.= ----------------V FB V FBsat (33) where Ipk is the peak drain current and VFB is the feedback voltage for a given operating condition. QR Flyback Converter Control-to Output Transfer Function Variation for Different Input Voltages where Lm is specified in equation (7). Control Block Diagram For quasi-resonant flyback converters. 40 dB K ⋅ R L V DC ( N p ⁄ N s1 ) ( 1 + s ⁄ w z ) ( 1 – s ⁄ w rz ) . RF. ©2005 Fairchild Semiconductor Corporation 10 . the effective load resistance is used in equation (34) instead of the actual load resistance of Vo1. RD. Co1 is the output capacitor of Vo1 and RC1 is the ESR of Co1. This figure shows that the gain between fp and fz does not change for different loads and the RHP zero is lowest at the full load condition. which is typically 2. This figure shows the system poles and zeros together with the DC gain change for different input voltages. CF and CB are shown in Figure 15. Notice that there is a right half plane (RHP) zero (wrz) in the control-to-output transfer function of equation (34).AN4149 APPLICATION NOTE I pk I LIM K = --------.-------------------------------ˆ .. The Figure 16 shows the variation of a quasi-resonant flyback converter’s control-to-output transfer function for different input voltages. Np and Ns1 are specified in STEP-7.

Because CB also determines the high frequency pole (wpc) of the compensator transfer function as shown in equation (35).5 ⋅ R 1 R 2 = ----------------------V o1 – 2. the additional delay capacitor (Cz) is de-coupled from the feedback circuit in normal operation. The procedure to design the feedback loop is as follows (a) Set the crossover frequency (fc) below 1/3 of RHP zero to minimize the effect of the RHP zero. Typical value for CB is 10-50nF. When the feedback voltage exceeds the zener breakdown voltage (Vz). where VSD is the shutdown feedback voltage and Idelay is the shutdown delay current. One simple and practical solution to this problem is designing the feedback loop for low input voltage and full load condition with enough phase and gain margin. too large a CB can limit the control bandwidth by placing wpc at too low a frequency. (b) Determine the DC gain of the compensator (wi/wzc) to cancel the control-to-output gain at fc. The relationship between R1 and R2 is given as 2. respectively. Set the crossover frequency below half of the minimum switching frequency (fsmin). Cz and CB determine the shutdown time.7V -40 dB 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz Figure 18. Typical values for VSD and Idelay are 7.5V to the reference pin of the KA431.5 frz fp 0dB Heavy load -20 dB (36) where Vo1 is the reference output voltage. QR Flyback Converter Control-to Output Transfer Function Variation for Different Loads (37) When the input voltage and the load current vary over a wide range. there are some restrictions as described below: 40 dB fp 20 dB L ight load (a) Design the voltage divider network of R1 and R2 to provide 2. (d) Place a compensator pole (fpc) around 3fc.5V and 5uA. Compensator Design T delay Figure 19. (c) Place a compensator zero (fzc) around fc/3. The RHP zero is lowest at low input voltage and full load condition. The gain increases only about 6dB as the operating condition is changed from the lowest input voltage to the highest input voltage condition under universal input condition. The gain together with zeros and poles varies according to the operating conditions. By setting the zener breakdown voltage (Vz) slightly higher than 2.7V.5 ) ⋅ C B ⁄ I delay fz -40 dB 1H z 10H z 100Hz 1kH z frz 10k Hz 100kHz Figure 17. determining the worst case for the feedback loop design is difficult. FPS IFB Idelay vFB CB Cz Vz Loop gain T 40 dB 20 dB fzc fp fpc fc frz fz Compensator V SD 0 dB Control to output -20 dB VZ 2. Application circuit to extend the shutdown time without limiting the control bandwidth is shown in Figure 19.APPLICATION NOTE AN4149 When determining the feedback circuit component. Delayed Shutdown ©2005 Fairchild Semiconductor Corporation 11 . In general. (b) The capacitor connected to feedback pin (CB) is related to the shutdown delay time in an overload condition by T delay = ( V SD – 2. a delay of 20 ~ 50 ms is typical for most applications.

> 1mA R bias ( 38 ) (39) where Vbias is the KA431 bias voltage as shown in Figure 16 and VOP is opto-diode forward voltage drop. 12 ©2005 Fairchild Semiconductor Corporation . Therefore. which is typically 1mA.> I FB RD V OP ------------. In general. the minimum values of cathode voltage and current for the KA431 are 2.5V and 1mA.5 -------------------------------------------. which is typically 1V. Rbias and RD should be designed to satisfy the following conditions: V bias – V OP – 2. IFB is the feedback current of FPS.AN4149 APPLICATION NOTE (c) The resistors Rbias and RD used together with the optocoupler H11A817A and the shunt regulator KA431 should be designed to provide proper operating current for the KA431 and to guarantee the full swing of the feedback voltage for the FPS device chosen. respectively.

1A 18 C101 330nF 275VAC PC301 817A R201 1kΩ 0.25W ©2005 Fairchild Semiconductor Corporation 13 .5A) 16V (1.2nF D201 Q201 KA431 R205 4.5A 12 3 Vcc IC101 SYNC 5 KA5Q0765RT GND 2 FB 4 ZD101 4.5A 3 C102 220uF 400V R103 68kΩ 0.5A) Schematic T1 EER3540 RT101 5D-9 1 10 D201 EGP20D L204 C210 BEAD 1000uF 35V 20V.4A) 20V (0.0A) 12V (0.25W 0.25W LF101 L201 C202 BEAD 1000uF 35V 16V.25W C105 3.1kΩ 0.25W 39kΩ 0.1kΩ 0. 0.25W R203 1kΩ R204 0.5W 1 Drain 13 C207 470pF 1kV D203 EGP20J D105 1N4937 L203 C208 BEAD 1000uF 35V 12V.25W Q202 KSC945 SW 201 R207 5.5W L101 BEAD 4 C107 1nF 1kV 11 C212 470pF 1kV D205 EGP20D BD101 R104 68kΩ 0.25W R208 5.25W VR202 30kΩ C108 2.5W C103 100nF 50V 6 D106 R106 D103 R107 1N4148 680Ω 1N4937 5.7V 0.1Ω 0.0A R206 220kΩ 0.7kΩ 0.4A C215 47uF 160V C104 47uF 50V C109 47nF 50V R105 470Ω 0. 0.APPLICATION NOTE AN4149 Design Example I (KA5Q0765RT) Application Color TV Device KA5Q0765RT Input Voltage 85-265Vac (60Hz) Output Power 82W Output Voltage (Rated Current) 125V (0.25W VR201 30kΩ C203 22nF 50V F101 FUSE 250V 3. 0.9nF 50V 7 14 15 16 C206 470pF 1kV D202 EGP20D 17 C205 470pF 1kV L202 C214 BEAD 100uF 160V 125V.

6 × 1 0.17 12 .5 × 1 0.13 3-4 15 .4φ φ φ φ φ Turns 35 28 8 6 35 28 10 11 Winding Method Center Winding Center Winding Center Winding Center Winding Center Winding Center Winding Center Winding Center Winding ×2 0.14 11 .6 × 1 0.3 × 1 Electrical Characteristics Pin Inductance Leakage Inductance 1-4 1-4 Specification 565uH ± 5% 10uH Max Remarks 1kHz. 1V 2 nd all short Core & Bobbin Core : EER 3540 Bobbin : EER3540 Ae : 109 mm2 14 ©2005 Fairchild Semiconductor Corporation .5 × 1 0.15 18 .AN4149 APPLICATION NOTE Transformer Specifications EER 3540 N p1 1 2 3 18 Na 17 16 N 16 V N20V N125V/2 N p2 4 5 6 7 8 9 15 N 1 2 5V/2 14 13 12 11 10 N 12 5 V /2 N 12 V Np2 N12V N16V N125V/2 Np1 Na N 20 V Transformer Schematic Diagram Winding Specifications No Np1 N125V/2 N16V N12V Np2 N125V/2 N20V Na Pin (s→f) 1-3 16 .5φ φ φ ×1 0.6 × 1 0.10 7-6 Wire 0.

1kΩ 0.5W L101 BEAD 4 C107 1. 0.5A 3 C102 470uF 400V R103 68kΩ 0.2nF D201 Q201 KA431 R205 4.25W R203 1kΩ R204 0.7kΩ 0.7V 0. 0.25W R208 5.25W C105 2.8A) 20V (0.25W VR202 30kΩ C108 2.25W Q202 KSC945 SW201 R207 5.APPLICATION NOTE AN4149 Design Example II (KA5Q1265RF) Application Color TV Device KA5Q1265RF Input Voltage 85-265Vac (60Hz) Output Power 154W Output Voltage (Rated Current) 125V (0.25W ©2005 Fairchild Semiconductor Corporation 15 .0A) Schematic T1 EER4242 RT101 10D-9 1 10 D201 EGP20D L204 C210 BEAD 1000uF 35V 20V.25W 39kΩ 0.8A C215 100uF 200V C104 47uF 50V C109 47nF 50V R105 470Ω 0.7nF 50V 7 14 15 16 C206 470pF 1kV D202 EGP30D 17 C205 470pF 1kV L202 C214 BEAD 220uF 200V 125V.5nF 1kV 11 C212 470pF 1kV D205 EGP20D BD101 R104 68kΩ 0.25W LF101 L201 C202 BEAD 2200uF 35V 16V.25W VR201 30kΩ C203 22nF 50V F101 FUSE 250V 5.5A) 16V (2.5W 1 Drain 13 C207 470pF 1kV D203 EGP30J D105 1N4937 L203 C208 BEAD 2200uF 35V 12V.5W C103 100nF 50V 6 D106 R106 D103 R107 1N4148 680Ω 1N4937 5.1Ω 0.0A) 12V (1. 2A 18 C101 330nF 275VAC PC301 817A R201 1kΩ 0. 1A 12 3 Vcc IC101 SYNC 5 KA5Q1265RF GND 2 FB 4 ZD101 4.1kΩ 0.0A R206 220kΩ 0.25W 0.

17 12 .13 3-4 15 .3 × 1 Electrical Characteristics Pin Inductance Leakage Inductance 1-4 1-4 Specification 385uH ± 5% 10uH Max Remarks 1kHz.5 × 2 0.5 × 1 0.5φ φ φ ×2 0.15 18 .5 × 2 0.14 11 . 1V 2 nd all short Core & Bobbin Core : EER 4242 Bobbin : EER4242 Ae : 234 mm2 16 ©2005 Fairchild Semiconductor Corporation .5φ φ φ φ φ Turns 22 18 5 4 22 18 6 7 Winding Method Center Winding Center Winding Center Winding Center Winding Center Winding Center Winding Center Winding Center Winding ×2 0.4 × 2 0.5 × 2 0.10 7-6 Wire 0.AN4149 APPLICATION NOTE Transformer Specifications EER4242 N p1 1 2 3 18 Na 17 N 16 15 N 125V/2 14 13 12 11 10 N 125V /2 N 12 V 16V N 20V N 125V/2 N p2 N 12V N 16V N 125V/2 N p1 N p2 4 5 6 7 8 9 Na N 20 V Transformer Schematic Diagram Winding Specifications No Np1 N125V/2 N16V N12V Np2 N125V/2 N20V Na Pin (s→f) 1-3 16 .

25W R208 5.25W R203 1kΩ R204 0. 3A L202 C214 BEAD 330uF 200V 125V.2nF D201 Q201 KA431 R205 4.1kΩ 0.1kΩ 0.5W 1 Drain D105 1N4937 12 3 Vcc IC101 SYNC 5 KA5Q1565RF GND 2 FB 4 ZD101 4.5W C103 100nF 50V C104 47uF 50V C109 47nF 50V R105 470Ω 0.25W Q202 KSC945 SW 201 R207 5.25W ©2005 Fairchild Semiconductor Corporation 17 .25W LF101 18 C101 330nF 275VAC PC301 817A R201 1kΩ 0.25W C105 2.1Ω 0.25W 39kΩ 0.0A) Schematic D201 EGP20D 10 C212 470pF 1kV D205 EGP30D 4 C107 2nF 1kV 13 C207 470pF 1kV D203 FFPF05U60S 6 D106 R106 D103 R107 1N4148 680Ω 1N4937 5.0A R206 220kΩ 0. 1A T1 EER5345 RT101 10D-9 1 3 C102 470uF 400V R103 68kΩ 0.7nF 50V 7 14 15 16 C206 470pF 1kV D202 FFPF05U20S 17 C205 470pF 1kV L201 C202 BEAD 2200uF 35V 16V.25W VR202 30kΩ C108 2.0A) 20V (1. 1A C215 220uF 200V L203 C208 BEAD 2200uF 35V 12V.0A) 16V (3. 2A L204 C210 BEAD 1000uF 35V 20V.0A) 12V (2.APPLICATION NOTE AN4149 Design Example III (KA5Q1565RF) Application Color TV Device KA5Q1565RF Input Voltage 85-265Vac (60Hz) Output Power 217W Output Voltage (Rated Current) 125V (1.25W 0.25W VR201 30kΩ C203 22nF 50V F101 FUSE 250V 5.7V 0.7kΩ 0.5W L101 BEAD 11 BD101 R104 68kΩ 0.

6 × 2 0.6φ φ φ φ φ Turns 21 17 5 4 21 17 6 7 Winding Method Center Winding Center Winding Center Winding Center Winding Center Winding Center Winding Center Winding Center Winding ×3 0.AN4149 APPLICATION NOTE Transformer Specifications EER5345 Np1 1 2 3 18 Na N20V N125V/2 Np2 N125V/2 17 16 15 14 13 12 N16V N p2 4 5 6 7 8 9 N12V N125V /2 N16V N12 V N125V/2 Np1 Na 11 10 N20 V Transformer Schematic Diagram Winding Specifications No Np1 N125V/2 N16V N12V Np2 N125V/2 N20V Na Pin (s→f) 1-3 16 .6 × 2 0.6 × 2 0. 1V 2 nd all short Core & Bobbin Core : EER 5345 Bobbin : EER5345 Ae : 318 mm2 18 ©2005 Fairchild Semiconductor Corporation .6φ φ φ ×2 0.14 11 .6 × 2 0.10 7-6 Wire 0.3 × 1 Electrical Characteristics Pin Inductance Leakage Inductance 1-4 1-4 Specification 325uH ± 5% 10uH Max Remarks 1kHz.5 × 1 0.17 12 .15 18 .13 3-4 15 .

As used herein: 1. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system.0m 002 © 2005 Fairchild Semiconductor Corporation . or (b) support or sustain life.fairchildsemi. NOR THE RIGHTS OF OTHERS. (a) are intended for surgical implant into the body.com 9/20/05 0. can be reasonably expected to result in significant injury to the user. Ph. www. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN.com DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY. or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPROATION.choi@fairchildsemi.AN4149 APPLICATION NOTE Hangseok Choi. FUNCTION OR DESIGN. or to affect its safety or effectiveness. 2. Life support devices or systems are devices or systems which. NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS.D Power Conversion Team / Fairchild Semiconductor Phone : +82-32-680-1383 Facsimile : +82-32-680-1317 E-mail : hangseok.

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