18-240: Structure and Design of Digital Systems

Using Quartus II to Configure the DE2-115 FPGA Board ! Version 1.3

Modern digital designs are specified in a hardware description language such as SystemVerilog. In order to ensure the description is correct, simulation software is used to see how the design reacts to di!erent test inputs. After assuring oneself that the design is correct, the engineer will synthesize the SystemVerilog and configure an FPGA (alternatively, the synthesized design can be used to create layout for an ASIC). For the purposes of 18-240, this design ! test ! synthesize ! configure cycle is performed using software tools provided by the FPGA manufacturer, Altera. The Quartus II software is an integrated design environment where you can edit your SystemVerilog, synthesize it, and configure the FPGA. Simulation is done with a di!erent software tool, VCS. This tutorial will walk you through the process of creating a Quartus II project, editing a SystemVerilog description and programming the DE2-115 Board. Quartus II version 12.1 is used in this tutorial, though the exact version probably doesn’t matter much for what we are doing.

Getting started
1. Log into one of the Linux machines in Hamerschlag Hall 1305. Before executing Quartus, you need to have its file location included in your path as well as having an environment variable set to help find the Quartus license. Assuming you are using bash, you can simply > source /afs/ece/class/ece240/lib/setup_quartus Feel free to include this line in your .bashrc file.1 Now, execute Quartus with: > quartus &


If you are using a shell other than bash, you’ll need to translate yourself. This one is pretty easy. Or, you can execute bash as a sub-shell and run this from inside.

New Project Wizard. just press the "Next" button. 5. Instead. Step 2: Add Files. The default is your home directory. A Quartus II "splash screen" will appear. databases. Top-Level Entity. Press the "Create a New Project" button. 3. Beware that this name must match the name of your SystemVerilog module exactly -. navigate to a work directory that is specific for this lab or tutorial. you will be developing a "library" of SystemVerilog components.case matters. you could add it here. It is your "top" module. You can actually have several projects in a directory. which is not a very good place to put class work.2. You will go through 5 steps in order to define your new project. A project is the collection of all files. 4. and information about your design. Name. New Project Wizard. Step 1: Directory. For now. Later in the semester. This is the step where you can add that library file to the project. You will use separate projects for each of your labs. Press the "Next" button. Name the top-level design entity "top" for this project. Name your project "Tutorial. as well as this tutorial. This window lets you choose a directory for your project. The name you specify on the second line is the project name. In case you happened to have some SystemVerilog file (or other design file) that you wanted to include in this project. as shown in Figure 1." The Top-Level Entity is the name of the module that is the top-level of your design. . A "New Project Wizard" window will appear.

It is a pretty lame project. Congratulations. In our case. as there isn't much in it at the moment. Feel free to use another editor if you wish. Let's fix that by creating a SystemVerilog file. Please. New Project Wizard. Step 4: EDA Tool Settings.6. Ours is the "EP4CE115F29C7. as the FPGA has been chosen by the fact that we are using the DE2-115 boards." Yeah. We just need to choose the exact FPGA that exists on the board. then press the "Next" button. New Project Wizard. Quartus II has an editor that you can use to create your files. Is it really a step if you can't do anything? Just press the "Finish" button. Alternatively. Step 5: Summary. though it does do some SystemVerilog syntax highlighting. you can (after selecting Cyclone IV E Family) type the device name into the "Name Filter" field. Step 3: Family and Device Settings. this is a pretty easy decision. 9. In this step. 7. we need to tell the tool which particular FPGA we are working with. It isn't a particularly good editor. New Project Wizard. . please. don't touch anything on this window except for the "Next" button. you now have a project. I'm sure that was the one you were going to guess. Choose the Family and Available devices to match Figure 2. 8.

d). To create a file using the built in editor: File ! New ! SystemVerilog HDL File ! OK. d) endmodule : top . Note that the module name ("top") must match the "Top-level Entity Name" that we supplied when we created the project (in step 4. a b f c d module top (output logic f. For now. This is a tabbed editing area." 11. awesome functionality in our circuit -. your new (empty) file is called "SystemVerilog1. a. f2) g2(f1. An editing pane will open in the middle-right section of the Quartus II window. input logic a. where various files and reports will be displayed. c.something like the circuit shown below? Type the following (or cut-n-paste) into the editor window. An empty file isn't very interesting. f1. Let's put some major.sv.2).10. nand g1(f. b) g3(f2. b. c.

12.. you can get a list in the "Project Navigator" pane.sv (as the Save dialog will suggest) and ensure that the "Add file to current project" checkmark is selected. you’ll get the entire path.sv is listed as being part of your project (at this point. either by design hierarchy./ junk that makes this almost unusable. Click the "Files" tab at the bottom of the Project Navigator and make sure that top. starting with a bunch of . Now that you have something to lose. At any time that you'd like to see what files there are in your project. as it nicely displays just the filename portion of the files. Under Linux. I’m showing here the screenshot from the windows version of Quartus. it should be the only such file)./. you'd better save it. files or design units. Change editor preferences here 13..e visible whitespace) and dotted vertical lines every two characters (i. indentation guide)./. Depending on the preferences set at the moment. It will show the components of your project. If anyone can figure out how to get Quartus to just display filenames and not complete paths.e. The "Project Navigator" is on the left column of the Quartus II application. you’ll make me very happy! . Save it with a filename of top. Press <ctrl> S to save your SystemVerilog code. You will notice that the editor colors keywords with blue text and numbers each line. You can change these preferences by pressing the buttons in the editor window toolbar.. you also will probably get dots in each space character (i.

20. Quartus II takes care of a great deal of individual analysis tasks. and d). one each for f. c. Another compilation report window has popped up to obscure your source code. total pins used (should be 5. then press the "OK" button to make the dialog box go away. that "Full Compilation was NOT successful" with 3 errors. Celebrate a moment. You should discover. b. That seems like a good idea. thanks to an error dialog. This one is a bit more interesting. It reports the number of logic elements used (should be 1). You can track the progress in the "Tasks" pane on the left side. 17. Can you find the errors? If not. 18.. Simply close the Compilation Report by clicking the small "X" box on the window's tab. you will notice that your source code window has been covered up with a "Compilation Report" window. go find more errors to fix and try again. so press the "Yes" button. here is a hint: . 16. a.14. Looks like I gave you faulty SystemVerilog code. By the way. Start the compilation again. Quartus II is running a full suite of industrial strength analysis tools on it. Did you fix the source code? In all three places? Good. etc. number of logic registers (should be 0 until Lab 2b)." You probably also had a bunch of warnings (10?). . Now it is time to compile the design. below the Project Navigator.. much like how a makefile can guide the build process for a complicated piece of software. If you didn't get successful compilation. there isn't much useful information in the report (since the compilation process failed pretty early on). Start the compilation with the aptly named Processing ! Start compilation (see what I did there?). You will be prompted to save your code before the process starts. 15. 19. Right now. Compilation should take a bit longer this time around. You should get a dialog box announcing that "Full Compilation was successful. Even though it seems we have a pretty small design (which is true). You can also use <ctrl> L or push the purple triangle button in the toolbar.

That warning is in the Critical Warning list: "No exact pin location assignment(s) for 5 pins of 5 total pins. When I ran this tutorial. You'll have to dig into the Compilation Report by selecting sections from the Table of Contents on the left side of the window. We will connect the signals according to the following table (note that you have to type in PIN_XXX): Signal f a b c d I/O output input input input input Device Green LED #0 Switch #0 Switch #1 Switch #2 Switch #3 Abbreviation LEDG0 SW0 SW1 SW2 SW3 Pin # PIN_E21 PIN_AB28 PIN_AC28 PIN_AC27 PIN_AD27 . with a little thought. Let's assign some pins to the input and output signals then. You can check Quartus II's choices in the Compilation Report (did you already get rid of it? Bring it back with Processing ! Compilation Report or <ctrl> R). Right now. a. c. b. There is one warning that." Quartus II doesn't know we are using the DE2-115 board. The buttons with red circle. should bother you. the input and output signals were decided upon by Quartus II without knowing where the switches and LEDs are. the input pin selected for b was Pin #D4. Critical Warnings or Warnings.21. 23. This later warning is given because we never defined logic signals for f1 and f2. purple triangle and yellow triangle let you choose to display Error messages. You can look at the Messages pane at the bottom of the window to discover what the details of the 10 warnings were. All it knows is that we are using a particular FPGA. it doesn't know what pins should be connected to the input and output signals (f. We just used them to connect our nand gates. 22. Thus. and d). Check out Fitter ! Resource Section ! Input Pins (and Output Pins). That'll be hard to get to in order to change the input value. Most are ignorable ("No clocks defined in design" which is completely true for this circuit) or of moderate interest ("created implicit net for f1"). We should probably specify that the inputs are connected to some switches and the outputs to an LED. Perhaps it would be better style to have defined them (and thus have a known type for them). which is actually connected to "ISP1362 DMA Acknowledge 1" a signal to the USB controller. as the project stands.

choose "As input tri-stated".. Let's take a slight detour to ensure the pins we didn't assign aren't lit up.. Yet another window will open. You will see that the input and output signal names are already filled in for you. This tool looks a lot messier than you need to worry about." Select the "Unused Pins" Category on the left.24. re-run the compilation. and select the "Device and Pin Options. named "Device and Pin Options. Your table should look like this when you are done: Close the Pin Planner with File ! Close or the "X" in the upper right of the window.. Go to Assignments ! Device. Now. 25.. Press OK again. You only need worry about the table at the bottom. which is why we allowed Quartus II to pick poor pins for us in the first place. Press OK. You should get a successful compilation dialog box with fewer warnings (9 warnings?). In the pane on the right. Go ahead and fill in the "Location" column of the table with the values from the table above. Open the "Pin Planner" tool with either Assignments ! Pin Planner or the keyboard shortcut <Ctrl+Shift> N." button on the middle right side. Not to worry! . 26. one per row. Unfortunately. the Pin Planner only knows the signal names after a successful compilation.

you can double-click on "Program Device (Open Programmer)" in the Tasks pane. 33.27. The switches provide a logic zero whenever the slider is closest to the bottom edge of the board. I'm including it in this tutorial.1. This last is probably easiest. That big.. as you will have just been paying attention to the compilation success in the same window. 30. your design is volatile. . This process is called "Configuring" the FPGA. In the "Currently selected hardware:" selection field. You should have a USB cable connected to the top of the board on the left side. though Quartus II sometimes calls it "Programming. though it will make more sense after you have learned how to do vectors in SystemVerilog. It should be in the far left socket (which is labeled with "Blaster" in small type on the board. it only stays in the FPGA while power is available." 28. Now it is time to send the synthesized design to the DE2-115 board (finally!). Try all 16 input combinations. If it doesn't at least say “USB-Blaster”. you should check the Run/Prog slide switch in the lower-left corner.5. It should be set to "Run." I love how they must think we wouldn't know that 100% is good and have to tell us we are successful. You may now close the Programmer window. I want to tell you a secret. 32. near a big red button. Hope you enjoyed it! Before you go. Turn the power o! and back on again (big red button).. There is a much easier way to do the Pin Planning work. you simply need to press the "Start" button on the left side. however. You should see lots of blinking lights. it will light up whenever it receives a logic 1. The LED is active high. If the hardware is appropriately selected in the Programmer.. What happens to your circuit? When you program the FPGA in the way we just did. choose "USB-Blaster" and close the window. A power cable should be connected in the upper end of the left side. A green progress bar in the upper-right corner should slowly fill up to "100% (Successful). That is. If the numbers are slightly di!erent.. You have now completed the Quartus II Tutorial. Open the FPGA Programmer with Tools ! Programmer or click this icon in the toolbar. Press it to turn the board on." field near the top says "USB-Blaster [2-1. The LED should light up for seven of them.3]" next to it. however. red button controls power to the board. That is. Be careful. because I'll probably forget to tell you about it later. Recall that SW0-3 are the inputs and that LEDG0 (on the far right) is the output. If you don't see all this electronic wonderfulness. Or. there are two places to plug in the USB cable. The Programmer window will open. You need to check that the "Hardware Setup. pretty much as you would expect. that’s okay." Take a quick look at the DE2-115 board. then click on "Hardware Setup. 29. You may now test the circuit on the DE2-115 board. 31. counting numbers and the message "Welcome to the Altera DE2-115" on the LCD display.".

SW[1]). SW[0]. I have also included a qsf file on Blackboard. It should load with the same Import Assignments process.. As long as your top-level module uses the exact names printed on the DE2-115 board (or listed in the DE2-115 User Manual). g3(f2.I have provided a spreadsheet file (CSV) 2 on Blackboard (in the Lab0 Stu! folder) that includes all pins on the entire FPGA. this file will save you from ever having to look up pin assignments. This works: module top (output logic [0:0] LEDG. endmodule : top 2 In some rare occasions. the csv file doesn't seem to load properly. SW[3]). so it'll take a few hoops to define our signals in ways that map directly to the names in the file. nand g1(LEDG[0].. Merely import it into your design with Assignments ! Import Assignments. f2). . The switches and LEDs are defined in this file as vectors. input logic [3:0] SW). g2(f1. f1. SW[2].