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Instructions to load and run a Verilog design on FPGA tool-kit.

1. Start the Xilinx ISE Project Navigator. 2. Creating new project. Go to file menu and click on new project. Choose the following configuration parameter during project creation. Project name: Whatever you want Project location: Make a directory with you name and put your projects in that directory. Device family: Spartan-3 Device: xc3s200 Package: ft256 Speed grade: -5 Top level module: HDL Synthesize tool: XST Simulator: Modelsim Generated simulation language: Verilog For any other setting just click on next tab. 3. Once the project is created successfully, you will find multiple windows on screen. Window at bottom is for showing the results for any process you apply on your design files (e.g. synthesize, implement). Big window in the right side is for opening various files in your project. Two small windows in left side are most important. (S) Sources in project: This window will list all files in your project. (P) Processes for Source: This window lists the operations you can apply on your project. 4. Creating new files. In the (P) window, click on create new source. Give file name and its location. There will be an option list on the left side of pop-up window. Select Verilog module option. An editor will open for you on right side in the tool window where you are expected to enter your Verilog code there. If you have already created a file, that file can be added to your project using add existing source. 5. Creating pin connections. Select your main Verilog module from the (S) window. Click on assign package pins under user constraints heading in the (P) window. A new window will open; in that window look for Design object list - I/O pins. This window will show you a list of all input-output signals in your module. You need to fill pin numbers in Loc column. You can find pin numbers on the FPGA board itself or in the documentation file. 6. Loading the Verilog design in the FPGA board. Select your main Verilog module. Click on the configure device (iMPACT) under Generate Programming File heading in

the (P) window. It will synthesize and implement your design as sub-steps. You can also synthesize and implement your design in individual steps. After this a small window will pop-up. Choose the following configuration parameters. Boundary scan mode Automatically connect to cable and identify boundary scan chain

Select main_module_name.bit file for assign new configuration file window Click on bypass for second assign new configuration file window You will find two chip diagrams. Select the one with main_module_name.bit as its name. Right click on that chip diagram and choose program option.

7. If your program is successfully loaded in the FPGA board, you will get programming
succeeded message.