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Memory Design

Random Access Memory
2m+k memory cells wide

Row decoder

n-1:k

k-1:0

Column Decoder Sense Amplifier

n bit address
m bit data word
ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut

Memory Timing: Approaches
Address bus Row Address Column Address Address Bus Address Address transition initiates memory operation

RAS CAS RAS -CAS timing

DRAM Timing Multiplexed Adressing

SRAM Timing Self-timed

ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15

© John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut

Memory Timing

DRAM read cycle
– Activate RAS, and place row address on bus – Row decoders select appropriate row – Activate CAS, and place column address on bus – Sense amps are activated and data is placed on the data bus
© John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut

ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15

Memory Timing

from “Ars Technica RAM Guide”, by Jon Stokes, ©Ars Technica LLC

ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15

© John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut

Chandy Dept.Read-Only Memory Cells BL WL VDD WL WL BL BL 1 BL WL WL BL WL BL 0 GND Diode ROM MOS ROM 1 MOS ROM 2 © John A. of Electrical and Computer Engineering University of Connecticut ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 .

MOS OR ROM BL [0] BL [1] WL [0] BL [2] BL [3] V DD WL [1] WL [2] V DD WL [3] V bias Pull-down loads ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut .

of Electrical and Computer Engineering University of Connecticut . Chandy Dept.MOS NOR ROM V DD Pull-up devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 BL [1] BL [2] BL [3] © John A.

5! x 7!) WL0 GND WL1 Programmming using the Active Layer Only WL2 GND WL3 Polysilicon Metal1 Diffusion Metal1 on Diffusion ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.MOS NOR ROM Layout BL0 BL1 BL2 BL3 Cell (9. Chandy Dept. of Electrical and Computer Engineering University of Connecticut .

of Electrical and Computer Engineering University of Connecticut .MOS NOR ROM Layout Cell (11! x 7!) Programmming using the Contact Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. Chandy Dept.

Chandy Dept. of Electrical and Computer Engineering University of Connecticut .MOS NAND ROM V DD Pull-up devices BL [0] WL [0] BL [1] BL [2] BL [3] WL [1] WL [2] WL [3] All word lines high by default with exception of selected row ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.

MOS NAND ROM Cell Layout (8! x 7!) Programmming using the Metal-1 Layer Only No contact to VDD or GND necessary. of Electrical and Computer Engineering University of Connecticut . Chandy Dept. drastically reduced cell size Loss in performance compared to NOR ROM Polysilicon Diffusion Metal1 on Diffusion ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.

of Electrical and Computer Engineering University of Connecticut . Chandy Dept.Equivalent Transient Model for MOS NOR ROM V Model for NOR ROM DD BL WL cword r word Cbit • Word line parasitics – Wire capacitance and gate capacitance – Wire resistance (polysilicon) • Bit line parasitics – Resistance not dominant (metal) – Drain and Gate-Drain capacitance ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.

Equivalent Transient Model for MOS NAND ROM Model for NAND ROM r bit r word cbit V DD BL CL WL cword • Word line parasitics – Similar to NOR ROM • Bit line parasitics – Resistance of cascaded transistors dominates – Drain/Source and complete gate capacitance ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut .

Chandy Dept. of Electrical and Computer Engineering University of Connecticut .Decreasing Word Line Delay Driver WL Polysilicon word line Metal word line (a) Driving the word line from both sides Metal bypass WL K cells Polysilicon word line (b) Using a metal bypass (c) Use silicides ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.

of Electrical and Computer Engineering University of Connecticut . Chandy Dept.Precharged MOS NOR ROM f pre V DD Precharge devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] PMOS precharge device can be made as large as necessary. ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. but clock driver becomes harder to design.

Chandy Dept.Non-Volatile Memories The Floating-gate transistor (FAMOS) Floating gate Source tox tox n+ Substrate p n+_ Gate Drain G S D Device cross-section Schematic symbol ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. of Electrical and Computer Engineering University of Connecticut .

of Electrical and Computer Engineering University of Connecticut .Floating-Gate Transistor Programming 20 V 0V 5V 20 V D S 0V D S 5V D 10 V S 5V -5 V -2. ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.5 V Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V T . Chandy Dept.

Chandy Dept. of Electrical and Computer Engineering University of Connecticut .FLOTOX EEPROM Floating gate Source 20–30 nm Gate Drain -10 V 10 V n1 Substrate p 10 nm n1 V GD I FLOTOX transistor Fowler-Nordheim I-V characteristic ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.

EEPROM Cell BL WL VDD Absolute threshold control is hard Unprogrammed transistor might be depletion ! 2 transistor cell ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. of Electrical and Computer Engineering University of Connecticut . Chandy Dept.

of Electrical and Computer Engineering University of Connecticut .Flash EEPROM Control gate Floating gate erasure n+ source Thin tunneling oxide programming p-substrate n+ drain Many other options … ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. Chandy Dept.

Cross-sections of NVM cells ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 Flash Courtesy Intel © John A. of Electrical and Computer Engineering University of Connecticut EPROM . Chandy Dept.

Basic Operations in a NOR Flash Memory_ Erase cell G 0V D 12V BL 0 array BL 1 12 V S WL 0 0V WL 1 open ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 open © John A. of Electrical and Computer Engineering University of Connecticut . Chandy Dept.

Basic Operations in a NOR Flash Memory_ Write 12 V G 6V 12 V S D 0V WL 1 WL 0 BL 0 BL 1 6V 0V ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. of Electrical and Computer Engineering University of Connecticut . Chandy Dept.

of Electrical and Computer Engineering University of Connecticut . Chandy Dept.Basic Operations in a NOR Flash Memory_ Read 5V G BL 0 1V 5V S D 0V WL 1 1V 0V WL 0 BL 1 ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.

Chandy Dept. of Electrical and Computer Engineering University of Connecticut .Memory Design • Register File – RAM with multiple read or write ports – You can read or write multiple data values at the same time – Useful in data processing applications ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.

of Electrical and Computer Engineering University of Connecticut . Chandy Dept.Memory Design • Register File Cell RB1 RB0 RB1 RB0 Word select 0 Word select 1 Write enable Write data ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.

Chandy Dept.Memory Design • Content Addressable Memory (CAM) – Instead of finding memory by address. find it by content – Search or match every single word in memory array ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. of Electrical and Computer Engineering University of Connecticut .

of Electrical and Computer Engineering University of Connecticut . Chandy Dept.Static CAM Memory Cell Bit Word CAM ••• CAM Bit Bit Bit Bit M4 M8 M6 •• •• Bit M9 M7 M5 Word Word CAM ••• CAM Match S M3 int S M2 M1 Wired-NOR Match Line ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.

CAM in Cache Memory CAM ARRAY H t iL o g c i SRAM ARRAY A d d r e s s D e c o d e r Input Drivers Sense Amps / Input Drivers Address Tag Hit R/W Data ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut .

of Electrical and Computer Engineering University of Connecticut . Chandy Dept.Memory Design • Other memory structures – FIFOs – LIFOs – SIPOs ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.

Periphery " Decoders " Sense Amplifiers " Input/Output Buffers " Control / Timing Circuitry ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut .

Memory Design • Row decoder A1 ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 A0 © John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut .

decode upper bits first and use lower bits to select from there • Increased fanout – Use minimum sized input gates ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. of Electrical and Computer Engineering University of Connecticut . Chandy Dept. two problems • Speed of gates becomes a problem – Use hierarchy of NANDS/NORS – Use predecoding .Memory Design • Row decoder – With multiple inputs (>4).

Hierarchical Decoders Multi-stage implementation improves performance ••• WL 1 WL 0 A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3 ••• NAND decoder using 2-input pre-decoders A1 A0 A0 A1 A3 A2 A2 A3 ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. of Electrical and Computer Engineering University of Connecticut . Chandy Dept.

Chandy Dept. of Electrical and Computer Engineering University of Connecticut .Dynamic Decoders Precharge devices GND GND V DD WL3 WL 3 WL 2 WL 1 V DD V DD WL 2 V DD WL 0 WL 1 WL 0 VDD " A0 A0 A1 A1 A0 A0 A1 A1 " 2-input NOR decoder 2-input NAND decoder ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.

Memory Design • Column decoder Memory Cells Data Out A1 A0 © John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 .

of Electrical and Computer Engineering University of Connecticut . Chandy Dept.Memory Design • Column decoder Memory Cells Data Out A1 A0 ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.

Chandy Dept. of Electrical and Computer Engineering University of Connecticut ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 .Memory Design • Column decoder – AND-decoder based • On the order of N•2N transistors Slow because of the series of passtransistors – Binary tree based • – Usually use a combination of the two © John A.

of Electrical and Computer Engineering University of Connecticut . column pull-down and column decoder can be very long – Use a sense amplifier to speed it up • • • Sense small differences in voltage and amplify it to rail voltage Can be differential or single-ended Usually use transistors with high threshold voltages ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A.Memory Design • Sense Amplifier – Time to get through row decoder. Chandy Dept.

a. Chandy Dept. output © John A.Sense Amplifiers $ #V C t = ---------------p Iav large make # V as small as possible small Idea: Use Sense Amplifer small transition input ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 s. of Electrical and Computer Engineering University of Connecticut .

Chandy Dept.Differential Sense Amplifier V DD M3 M4 y bit M1 M2 bit Out SE M5 Directly applicable to SRAMs ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. of Electrical and Computer Engineering University of Connecticut .

Chandy Dept.Next class • • Memory Reliability and Yield Control logic ECE 249 VLSI Design and Simulation Spring 2005 Lecture 15 © John A. of Electrical and Computer Engineering University of Connecticut .