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DESPLAZAMIENTO
EN BASE OCTAL
TRABAJO DE SISTEMAS ELECTRNICOS
INDUSTRIALES
INTEGRANTES:
ndice
Introduccin y descripcin del trabajo
Introduccin
Descripcin de la estrategia y algoritmos desarrollados
INTRODUCCIN
Y
DESCRIPCIN
DEL TRABAJO
Introduccin
Este memoria es el trabajo de la asignatura Sistemas Electrnicos Digitales, cuyo enunciado es el
siguiente:
Disee un registro de desplazamiento octal, esto es, que inicialmente tenga a su salida 0000 0000 y
que cuando se introduzca un '1' con un pulsador pase a 0000 0001 0000 0010 y as
sucesivamente hasta llegar a 0000 0100, de donde pasar a 0001 0000. Cada vez que se pulse, se
introduce un '1' en el bit menos significativo y recorre las posiciones hasta volver a cero, pero no
introducir el '1' si el nmero resultante no pertenece a la base. Como entradas tendr una seal
de '1', y como salidas dos visualizadores en los que se mostrar el decimal de cada nibble.
A esto hay que aadir una mejora que hemos incluido: adems de los dos visualizadores, hemos
puesto como salida tambin los ocho Leds que dispone la placa Espartan 3E, de esta manera
podemos representar los bits en los Leds, de manera que cada Led encendido represente cada bit del
registro. De esta manera podemos ver y tener en cuenta el desplazamiento que ocurre en el registro.
REG_TOP
Btn
detec_pulso
antirrebote
sin_reb
Btn
c_i
BT
f_i(3:0)
inA
mux2to1
clk_T
b_i
reset
binTo7seg
g_i
pulso
f_i(7:4)
bin
outZ
clk
segment
seg
inB
P_T
clk
pulso_2
a_i
reset
S(0)
e_i
2
I
dec1To2
uno1
S(1)
P_T
uno2
DUENDE
registro
reset
8
8
f_i
clk
reset
balance
pulso_3
P_T
clk
reset
d_i
clk_T
CLK
DIGCTRL
balan2elem
LEDS
DUENDE
P_T
carga
a
desp
P_T
CLK
clk
registro
reg8desp
pulso_t1
reset
clk
reset
reset
registro
CDIGO
Y
EXPLICACIN
DE CADA MDULO
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BT,clk: in std_logic;
pulso: out std_logic:='0');
end detec_pulso;
--------------------------------------------------------------------- arquitectura comportamental serie
architecture comportamental of detec_pulso is
signal BT_R1,BT_R2: std_logic; --son las salidas de los registros
begin
reg_D1: process(clk,BT)
begin
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process(clk,reset)
begin
if reset = '1' then
cuenta<=0;
p_t<='0';
elsif clk'event and clk='1' then
if cuenta >= max - 1 then
p_t<='1';
cuenta<=0;
else
p_t<='0';
cuenta<=cuenta + 1;
end if;
end if;
end process;
end comportamental;
-------------------------------------------------------------------
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Time
clk=1
p_t=0
registro[7:0]=00000000 0000+ 00000001
reset=0
1 us
2 us
3 us
00000010
4 us
5 us
00000011
6 us
00000110
7 us
8 us
9 us
00000000
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carga:
end reg8desp;
----------------------------------------------------------------arquitectura
architecture behav of reg8desp is
begin
P_registro: Process (reset, clk)
begin
if reset = '1' then
registro <= (others => '0');
elsif clk'event and clk='1' then
if desp = '1' then
registro (2 downto 1) <= registro (1 downto 0);
registro (4) <= registro (2); -- aqui se salta el registro(3)
registro (6 downto 5) <= registro (5 downto 4);
--el registro 7 no recibe ningun valor
registro(0)<='0';
end if;
if carga='1'then
registro(0) <= '1';
end if;
end if;
end process;
end behav;
---------------------------------------------------------------
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<= '1';
for 50 ns;
<= '0';
for 50 ns;
P_CARGA: process
begin
carga<='0';
wait for 42 ns;
carga<='1';
wait for 20 ns;
carga<='0';
wait for 100 ns;
carga<='1';
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end behavior;
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mux2to1 is
generic(nbits: natural range 1 to 32 :=4);
port(
end mux2to1;
------------------------------------------------------------arquitectura comportamental RTL
architecture behavioral of mux2to1 is
begin
outZ <= inA when selecS = '0' else
inB;
end behavioral;
------------------------------------------------------------arquitectura comportamental abstracta
architecture abstracta of mux2to1 is
begin
process(inA,inB,selecS)
begin
if selecS = '0' then outZ<=inA;
else outZ<=inB;
end if;
end process;
end abstracta;
-----------------------------------------------------------
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-----------------BINTO7SEG
-------------------------------- Decoder binario a hexa 7 segmentos -------------actualizado
201401131203 (2014/01/13 12:03)
----------------------------------------------------------__________
-| binario |
-bin_/4__|
a
|___/7__ seg
-| 7 segm |
-|__________|
--- Es un decoder que convierte de codigo binario a
-- hexadecimal para visualizarlo en un display de
-- 7 segmentos a nivel bajo
---entrada
salida
_______________
-- num. bin
a b c d e f g
|
___a__
|
-0
0000
0 0 0 0 0 0 1
|
|
|
|
-1
0001
1 0 0 1 1 1 1
| f|
|b
|
-2
0010
0 0 1 0 0 1 0
|
|
g |
|
-3
0011
0 0 0 0 1 1 0
|
-----|
-4
0100
1 0 0 1 1 0 0
|
|
|
|
-5
0101
0 1 0 0 1 0 0
| e|
|c
|
-6
0110
0 1 0 0 0 0 0
|
|___d__|
|
-7
0111
0 0 0 1 1 1 1
|_______________|
-8
1000
0 0 0 0 0 0 0
-9
1001
0 0 0 1 1 0 0
-A
1010
0 0 0 1 0 0 0
-B
1011
1 1 0 0 0 0 0
-C
1100
0 1 1 0 0 0 1
-D
1101
1 0 0 0 0 1 0
-E
1110
0 1 1 0 0 0 0
-F
1111
0 1 1 1 0 0 0
------------------------------------------------------------Librerias
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------------------------------- entidad
entity binTo7seg is
port (
end binTo7seg;
----------------------------------------------------------arquitectura comportamental RTL
architecture behavioral of binTo7seg is
begin
seg <= "0000001" when bin = "0000" else --0
"1001111" when bin = "0001" else
"0010010" when bin = "0010" else
"0000110" when bin = "0011" else
"1001100" when bin = "0100" else
"0100100" when bin = "0101" else
"0100000" when bin = "0110" else
"0001111" when bin = "0111" else
"0000000" when bin = "1000" else
"0001100" when bin = "1001" else
"0001000" when bin = "1010" else
"1100000" when bin = "1011" else
"0110001" when bin = "1100" else
"1000010" when bin = "1101" else
"0110000" when bin = "1110" else
"0111000"; --F
end behavioral;
-------------------------------------------------------
--1
--2
--3
--4
--5
--6
--7
--8
--9
--A
--B
--C
--D
--E
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---------------Decoder 2 a 4
-------------------------------actualizado
201401150829 (2014/01/15 08:29)
-- no comprobado su funcionamiento (compila bien)
-----------------------------------------------------------------_________
-|
|
-|
|
-I ____|
DEC
|___/4__ S
-|
|
-E ___o| 2 a 4 |
-|
|
-|_________|
--- Decodificador 1 a 2 con una entrada de habilitacion a nivel
-- bajo.
----------------------------------------------------------------------------------------DETALLES------------------------------------- por defecto la salida esta en logica negada, para cambiarlo
-- hay que modificarlo en generic:
-logica := '0'
logica negada
-logica := '1'
logica positiva
---Tabla de verdad:
-_________________
-| E | I | S1 S0 |
-| --|-----|-------|
-| 0 | X | 0 0 |
-| 1 | 0 | 0 1 |
-| 1 | 1 | 1 0 |
-|___|_____|_______|
-------------------------------------------------------------librerias
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----------------------------------------------------------entidad
entity dec1to2 is
generic(logica: bit := '0');
port (
I: in std_logic;
E: in std_logic;
S: out std_logic_vector (1 downto 0));
end dec1to2;
-----------------------------------------------------------arquitectura comportamental RTL
architecture behavioral of dec1to2 is
signal S_prev: std_logic_vector (1 downto 0); -- es la seal previa
-- en logica positiva que podr ser modificada mas adelante si
-- la entrada "logica" esta a nivel bajo.
signal E_neg: std_logic;
begin
E_neg <= not E;
S_prev<="00" when E_neg = '0' else
"01" when I = '0' else
"10" ;
S <= not (S_prev) when logica='0' else
S_prev;
-- Aqui se asigna la seal en logica positiva o neg.
end behavioral;
----------------------------------------------------------
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END COMPONENT;
COMPONENT pulso_tiempo
generic (max: integer range 0 to 2**26-1 := 150);
port(
clk,reset: in std_logic;
p_t: out std_logic);
END COMPONENT;
for
for
for
for
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for
for
for
for
for
SIGNAL
SIGNAL
SIGNAL
signal
a_i,b_i,c_i,d_i,e_i: std_logic;
g_i: STD_LOGIC_VECTOR(3 DOWNTO 0);
f_i: STD_LOGIC_VECTOR(7 DOWNTO 0);
uno: std_logic:='1';
BEGIN
uno1<=uno;
uno2<=uno;
LEDS<= f_i;
I_DUENDE: DUENDE PORT MAP(
p_t => a_i ,
RESET => RESET ,
CLK => CLK ,
registro => f_i );
I_antirrebote: antirrebote PORT MAP(
Btn => BTN,
clk_T => b_i ,
reset => RESET,
sin_reb => c_i);
I_balan2elem: balan2elem PORT MAP(
clk_T => d_i,
balance => e_i);
I_binTo7seg: binTo7seg PORT MAP(
bin => g_i ,
seg => SEGMENT);
I_dec1to2: dec1to2 PORT MAP(
I => e_i ,
E => '0',
S (0)=> DIGCTRL(0),
S (1)=> DIGCTRL(1));
I_detec_pulso: detec_pulso PORT MAP(
BT => c_i ,
clk => CLK,
pulso => a_i);
I_mux2to1: mux2to1 PORT MAP(
inA => f_i( 3 downto 0),
inB => f_i( 7 downto 4),
selecS => e_i,
outZ => g_i);
I_pulso_2: pulso_tiempo
generic map (max => 500000)
PORT MAP(
clk => CLK,
reset => RESET ,
p_t => b_i);
I_pulso_3: pulso_tiempo
generic map (max => 500000)
PORT MAP(
clk => CLK ,
reset => RESET ,
p_t => d_i);
end Behavioral;
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P_Clk: Process
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process;
-- Stimulus process
P_CARGA: process
begin
BTN<='0';
wait for 580 ns;
---------pulsacion--------BTN<='1';
wait for 1 ns;
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BTN<='0';
wait for 12 ns;
BTN<='1';
wait for 3 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 4 ns;
BTN<='0';
wait for 13 ns;
BTN<='1';
wait for 6 ns;
BTN<='0';
wait for 8 ns;
BTN<='1';
wait for 5 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 8 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 7 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 4 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 1 ns;
BTN<='1';
wait for 390 ns;
BTN<='0';
-----------------wait for 3500 ns;
---------pulsacion--------BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 12 ns;
BTN<='1';
wait for 3 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 4 ns;
BTN<='0';
wait for 13 ns;
BTN<='1';
wait for 6 ns;
BTN<='0';
wait for 8 ns;
BTN<='1';
wait for 5 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 8 ns;
BTN<='0';
wait for 9 ns;
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BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 7 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 4 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 1 ns;
BTN<='1';
wait for 390 ns;
BTN<='0';
-----------------wait for 1250 ns;
---------pulsacion--------BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 12 ns;
BTN<='1';
wait for 3 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 4 ns;
BTN<='0';
wait for 13 ns;
BTN<='1';
wait for 6 ns;
BTN<='0';
wait for 8 ns;
BTN<='1';
wait for 5 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 8 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 7 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 4 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 1 ns;
BTN<='1';
wait for 390 ns;
BTN<='0';
-----------------wait for 1000 ns;
---------pulsacion--------BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 12 ns;
BTN<='1';
wait for 3 ns;
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BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 4 ns;
BTN<='0';
wait for 13 ns;
BTN<='1';
wait for 6 ns;
BTN<='0';
wait for 8 ns;
BTN<='1';
wait for 5 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 8 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 7 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 4 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 1 ns;
BTN<='1';
wait for 390 ns;
BTN<='0';
-----------------wait for 4000 ns;
---------pulsacion--------BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 12 ns;
BTN<='1';
wait for 3 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 4 ns;
BTN<='0';
wait for 13 ns;
BTN<='1';
wait for 6 ns;
BTN<='0';
wait for 8 ns;
BTN<='1';
wait for 5 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 8 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 7 ns;
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BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 4 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 1 ns;
BTN<='1';
wait for 390 ns;
BTN<='0';
-----------------wait for 8000 ns;
---------pulsacion--------BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 12 ns;
BTN<='1';
wait for 3 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 4 ns;
BTN<='0';
wait for 13 ns;
BTN<='1';
wait for 6 ns;
BTN<='0';
wait for 8 ns;
BTN<='1';
wait for 5 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 8 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 7 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 4 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 1 ns;
BTN<='1';
wait for 390 ns;
BTN<='0';
-----------------wait for 10000 ns;
-----reset
reset<= '1';
wait for 200 ns;
reset<= '0';
assert false report
"puesto el reset" severity note;
wait;-- espera para siempre
end process;
END;
Time
btn
sin_reb
pulso
clk
leds[7:0]
000000+ 00000001
segment[6:0] 0000001
digctrl[1:0]
reset
uno1
uno2
10 us
00000010
00000011
0000+ 00000111
00010110
0011+ 00110101
01110010
Time
btn
sin_reb
pulso
clk
leds[7:0]
0111+ 01100100
segment[6:0]
digctrl[1:0]
reset
uno1
uno2
20 us
30 us
01010001
00100010
0010010
01000100
1001100
00010000
00000000
0000001
+
Time
btn
4300 ns
4400 ns
4500 ns
4600 ns
4700 ns
4800 ns
4900 ns
5 us
5100 ns
5200 ns
5300 ns
sin_reb
pulso
clk
leds[7:0]
00000010
00000011
segment[6:0] 0000+ 0010+ 0000+ 0010+ 0000+ 0010+ 0000+ 0010+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000110
digctrl[1:0] 01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
reset
uno1
uno2
Time
btn
4600 ns
sin_reb
pulso
clk
leds[7:0]
00000010
segment[6:0] 00+ 0010010
digctrl[1:0] 01 10
reset
uno1
uno2
4700 ns
0000001
01
00000011
0000110
10
0000001
01
4800 ns
0000110
10
0000001
01
4900 ns
0000110
10
0000001
01
0000110
10
5 us
0000001
01
0000110
10
5100 ns
0000001
01
0000110
10
0000001
01
Una vez asignados todos los pines le damos a guardar y nos crear un fichero .ucf cuyo contenido
se puede editar.
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