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Fault Modeling

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Outlines

Use the information of interconnected components (e.g., gates) to derived test regardless of the functions Define faults

fault coverage (quality evaluation) ATPG to generate tests for faults DfT for enhancing fault detection.

Model the effects of physical defects on the logic function and timing Identifies target faults

Model faults (defects) most likely to occur Depends on the process, design platform, design style, design level, etc.

Create tests only for the modeled faults

Physical Defects

Silicon Defects Photolithographic Defects Mask Contamination Process Variation Defective Oxides

Electrical Effects

Shorts (Bridging Faults) Opens Transistor Stuck-On/Open Resistive Shorts/Opens Change in Threshold Voltages

Logical Stuck-at 0/1 Slower Transition (Delay Faults) AND-bridging, OR-bridging

5

Logical Effects

Defect

Physical imperfection

The unintended difference between the implemented hardware and its intended design

Error

Fault

One of the gate input terminal was mistakenly connected to ground Defect: short to ground Error: f = 0 when a = b = 1 Fault: b stuck at 0

6

a b

Stuck-at faults Interconnect short and opens Transistor stuck-on/open faults Memory faults Delay faults

Assumptions:

Only One line is faulty Faulty line permanently set to 0 or 1 Fault can be at an input or output of a gate

One of the gate input terminal was mistakenly connected to ground Fault: b stuck at 0 signal b will always be 0

8

a b

Empirically many defects accidentally detected by test derived based on single stuck-at fault

Several stuck-at faults occur at the same time For a circuit with k lines

there are 2k single stuck-at faults there are 3k-1 multiple stuck-at faults A line could be stuck-at-0, stuck-at-1, or fault-free One out of 3k resulting circuits is fault-free

4-bit ALU (Hughes & McCluskey, ITC-84) All double and most triple-faults covered. Large circuits (Jacob & Biswas, ITC-87) Almost 100% multiple faults covered for circuits with 3 or more outputs.

VDD

pull to VDD

VDD

f

B A GND

bridging

g

C D

11

Interconnet Opens

Open defects are due to a defect which splits up a node into two or more distinct nodes.

Large open (break): No current can go between the two ends of the open when a voltage is applied across it. Narrow open: The opening is usually < 100 nm. In this case a small leakage current (by tunnel effect) go across the open.

VDD VDD

f B D C

A

GND GND

12

VDD

IDDQ current

0

stuck-on GND

Output level?

Transistor Stuck-On

Depends on the relative impedances of the pull-up and pull-down networks Both P and N transistors are conducting, causing increased quiescent current, called IDDQ fault

13

Transistor stuck-open

May cause the output to be floating The faulty cell has sequential behavior

VDD

stuck-open

Initialization vector

(0/0) ->(1/0)

Faulty value

1 -> 0 GND

14

It is similar to single stuck-at fault model, except that every cell output is considered observable by IDDQ testing.

The fault site at a gate input requires sensitization and propagation to an output of the same gate (but not to an output of the device) in order to be given credit for IDDQ fault detection.

1/0

f=0

The exhaustive pseudo-stuck-at patterns for IDDQ testing cover all leakage faults in fully complementary combinational CMOS circuits.

ab 01 10 cd 01 11 Detected Pseudo Stuck-At Faults a-sa1 d-sa0 b-sa1 d-sa0 Detected leakage Faults (total 6C2 = 15 leakage faults) <b, 0> <c, 1> <d, 0> <a, 1> <a, b> <a, d> <b, c> <c, d> <0, 1> <a, 0> <c, 0> <d, 0> <b, 1> <a, b> <b, c> <b, d> <0, 1>

11

00

<a, 0> <c, 0> <c, 1> <d, 1> <a, c> <a, d> <b, c> <b, d> <0, 1>

2-input NAND2

S.T., Zachariah, A comparative study of pseudo stuck -at and leakage fault model, IEEE Intl Conf. on VLSI Design 1999

Memory Faults

Parametric Faults

Functional Faults

Stuck Faults in Address Register, Data Register, and Address Decoder Cell Stuck Faults Adjacent Cell Coupling Faults 0 0 0 the presence of a faulty signal depends on 0 d b the signal values of the neighboring cells Pattern-Sensitive Faults 0 a 0 Pattern sensitivity between cells a=b=0 => d=0

Chip with timing defects may pass the low speed stuck-fault testing, but fail at the system speed Transition Fault, Gate Delay Fault, Line Delay Fault, Path Delay Fault, Segment Delay Fault

Types

18

Current practice

N-detect faults

Interconnect open faults and bridging faults Stuck-open (CMOS)

19

t detects f z(t) zf(t) Note that there can be multiple outputs for z(t) A fault f is said to be detectable If there exists a test t that detects f; otherwise, f is undetectable. Example

X1

x

s-a-1

X2

Z1

Z2

X3

The test (x1,x2,x3) = (100) detects f because z1(100)=0 while z1f (100)=1

Redundancy of Faults

Undetectable faults do not change the function of the circuit The wire can be connected to a constant value without changing circuits function.

22

s. a. 1

l x m n

l m n

m n

If l s.a.0 is undetectable, the entire gate can be removed & replaced by a constant 0 wire

s. a. 0

l m n

l

m n

23

Speed: carry look-ahead adders Fault tolerant circuits: triple module redundant (TMR)

24

Redundant faults: e s-a-1, d s-a-0 and d s-a-1 The NAND gate with d is redundant

a

e e sa1

c

d f

b a c b

simplify the redundant signals and gates

Fault Masking

The existence of an undetectable fault may invalidates the test for another fault.

e a e sa1 c

d f

26

Fault b can be detected by test vector 1101. (X10X) 1 a 0 0 1 d 1 1 c 0 1 0/1 1/0 1 g b b g sa0 1/0

0/1

In the presence of the undetectabe fault a, the test vector 1101 becomes invalidate for fault b.

1 1 a c 0 d 1 1

1

1

0 1/0 0/1

g b g sa0 1/0

27

But fault b can also be detected by test vector 010X with fault a.

0 1 a d X 1 0

c

b

1

1/0 0/1

0/1

1 g b g sa0 1/0

28

Fault Equivalence Fault Dominance Checkpoint Theorem

Fault Equivalence

Distinguishing test

A

Za t Zb t 1

Equivalent Faults

faults, a & b are said to be equivalent in a circuit , iff the function under a is equal to the function under b for any input combination (sequence) of the circuit. No test can distinguish between a and b In other words, test-set(a) = test-set(b)

Two

AB

A C

C 0 0

00 01

10

11

0

1

1

0 0 0

31

AND gate:

all s-a-0 faults are equivalent all s-a-1 faults are equivalent all the input s-a-0 faults and the output s-a-1 faults are equivalent all input s-a-1 faults and the output s-a-0 faults are equivalent

OR gate:

x s-a-0

x s-a-0

NAND gate:

same effect

NOR gate:

Inverter:

input s-a-1 and output s-a-0 are equivalent input s-a-0 and output s-a-1 are equivalent

s-a-1

s-a-1 s-a-1 s-a-0

s-a-0 s-a-0

s-a-1 s-a-0

s-a-1 s-a-1

s-a-1 s-a-0

s-a-0 s-a-0

s-a-1 s-a-0

These equivalent faults can be found by sweeping the circuit from the primary outputs to the primary inputs Transitive Rule: When a == b and b == g, then a == g

s-a-0

x

s-a-1

x

s-a-1

x

Three faults shown are equivalent !

Construct a Graph

A node is a fault When there is a link between two node, the two faults are equivalent

a s-a-0

a s-a-0

b s-a-0

x x

c s-a-1

x b s-a-0 c s-a-1

Construct a bigger fault equivalent graph by sweeping the netlist from POs to PIs

a b d e

c

a s-a-0 c s-a-1

b s-a-0

d s-a-1

e s-a-1

c

a

b s-a-0 f s-a-1

There is no rule to guarantee equivalence between faults of branches. It is a special case here b s.a.0 == f s.a.1

37

Fault Dominance

Dominance Relation

A fault b is said to dominate another fault a in an irredundant circuit, iff every test (sequence) for a is also a test (sequence) for b . I.e., test-set(b) > test-set(a) No need to consider fault b for fault detection once a is detected

Test(a)

Test(b)

a is dominated by b

Fault Dominance

AND gate:

Output s-a-1 dominates any input s-a-1 Output s-a-0 dominates any input s-a-1

Easier-to-test x s-a-1

NAND gate:

x s-a-1

OR gate:

Output s-a-1 dominates any input s-a-0

harder-to-test

NOR gate:

AB

A C

C 0 0

00 01

10

11

0

1

1

0 0 0

C s-a-1

40

Equivalence + Dominance

For each n-input gate, we only need to consider n+1 faults during test generation

s-a-0

s-a-0 s-a-0

s-a-1

s-a-1

s-a-1

s-a-1

s-a-1

s-a-0

s-a-1

s-a-0

s-a-0

A node is a fault When fault a dominates fault b, then an arrow is pointing from a to b

a s-a-1

a s-a-1

b s-a-1

x x

c s-a-0

x

b s-a-1

c s-a-0

42

Construct a bigger fault equivalent graph by sweeping the netlist from POs to PIs

a

d e

a s-a-1

c s-a-0

b s-a-1

d s-a-0

e s-a-0

Start Sweeping the netlist from PO to PI To find the equivalent fault groups Equivalence analysis

Dominance analysis

Done

44

Checkpoint Theorem

Checkpoints Theorem

Checkpoints = primary inputs + fanout branches In a combinational circuit, any test which detects all single stuck faults on all checkpoints detects all single faults in the circuit.

Sweeping the circuit from PO to PI to examine every gate and replace output faults by input faults until a PI or branch is met.

Based on an reversed levelized order: EDABC If a branch is met, start the above process from the stem again.

A

D

PO branch faults are ignored, since they are represented by gate output faults, e.g., Ds output

E

46

10 checkpoint faults

a s-a-0 == d s-a-0, c s-a-0 == e s-a-0 b s-a-0 > d s-a-0, b s-a-1 > d s-a-1

6 out of 10 faults are enough.

a

d

f

g

b

e c

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