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# EECS 142

## Lecture 14: MOSFET LNA Design

Prof. Ali M. Niknejad
University of California, Berkeley
Copyright c 2005 by Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 1/29 p. 1/29
MOS Amplier Noise Figure
C
gs
g
m
v
gs
r
o
+
v
gs

R
g
i
d
v
2
R
g
R
s
V
s
R
L
Lets recalculate the MOS amp noise gure (quickly).
Note that the current gain of the MOS amp is given by
i
o
= g
m
v
1
= g
m
v
s
R
s
+R
g
+
1
jC
gs
_
1
jC
gs
_
= v
s
g
m
1 +jC
gs
(R
s
+R
g
)
v
s
g
m
jC
gs
(R
s
+R
g
)
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 2/29 p. 2/29
Noise Figure by Current Gain
This can be rewritten as i
o
= G
m
v
s
, where
G
m
= j

1
R
s
+R
g
This facilitates the noise calculations since the total
noise is given by
i
2
o,T
= G
2
m
(v
2
g
+v
2
s
) +i
2
d
And the noise gure is easily computed
F = 1 +
v
2
g
v
2
s
+
i
2
d
G
2
m
v
2
s
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 3/29 p. 3/29
Expression for F (again)
Substitution of the the various noise sources leads to
F = 1 +
R
g
R
s
+
_

_
g
m
R
s
_

T
_
2
(R
s
+R
g
)
2
Assume that R
s
R
g
to get
F = 1 +
R
g
R
s
+
_

_
_

T
_
2
g
m
R
s
Its important to note that this expression contains both
the channel noise and the gate induced noise. If we
assume that R
g
= R
poly
+
1
5g
m
, and the noise is
independent from the drain thermal noise, we get a
very good approximation to the actual noise without
using correlated noise sources.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 4/29 p. 4/29
Minimum Noise for MOS Amp
Lets nd the optimal value of R
s
F
R
s
=
R
g
R
2
s
+
_

_
_

T
_
2
g
m
= 0
or
R
g
R
2
s
=
_

_
_

T
_
2
g
m
R
s,opt
= R
s
=
_
R
g
_

_
_

T
_
2
g
m
=
_

_
2

R
g
_

_
g
m
We now have (after simplication)
F
min
= 1 + 2
_

T
_
_
g
m
R
g
_

_
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 5/29 p. 5/29
MOS Amp Example
Lets nd R
s,opt
for a typical amplier. Say f
T
= 75 GHz,
f = 5 GHz, and
_

_
= 2. Also suppose that by proper
layout R
poly
is very small. The intrinsic gate resistance
is given by
R
g
= R
poly
+
1
5g
m
=
1
5g
m
To make the noise contribution from this term 0.1
requires that
R
g
R
s
= 0.1
1
5g
m
R
s
= 0.1
5g
m
R
s
= 10
g
m
=
10
5 50
=
1
25
S = 40 mS
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 6/29 p. 6/29
MOS Amp Continued
Note that for V
gs
V
T
= 200 mV, the required current is
fairly hefty
g
m
=
2I
ds
V
gs
V
T
= 40 mS
I
ds
= 40 mS 200 mV
1
2
= 4 mA
The optimum source resistance is given by
R
s,opt
=
f
T
f

R
g
_

_
g
m
= 15
_
5 25
2
119
F
min
= 1 + 2
f
f
T
_
g
m
R
g
_

_
= 1 +
2
15
_
5 2/25 = 1.08
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 7/29 p. 7/29
MOS Amp Continued
This is a very low noise gure of .35 dB !!
In practice, though, itll be difcult to get this low of a
noise gure and get useful gain with the simple
common source. Lets see why.
Note that C
gs
g
m
/
T
= 85 fF. The input impedance of
the FET is given by
Z
i
= R
g
+
1
jC
gs
= R
g
j

T
g
m
5 j375
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 8/29 p. 8/29
Matching Option 1
Matching
Network
R
s
= 50
R
g
= 5
j375
119 j157
Dont match the input impedance. Simply use a
matching network to multiply the 50 source up to 119.
This means that the source (antenna) will see a
termination that is m = 119/50 = 2.38 times smaller, or
This is a good for noise but a bad power match.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 9/29 p. 9/29
Matching Option 2
Matching
Network
R
s
= 50
R
g
= 5
j375
119
+j375
5
2
Use an inductor to tune out the capacitive part of the
input. This will add noise due to nite inductor Q. Note
that the matching network will match this low 5
resistance down to 5/2.38 2.
Now the power match is even worse.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 10/29 p
Matching Option 3
Matching
Network
R
s
= 50
R
g
= 5
j375
119
2
Q
2
R
g
Use a shunt inductor to resonate the input impedance.
The inductor should be connected to the DC value of
V
gs
and can double as a bias element.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 11/29 p
Option 3 (cont)
But since the gate capacitance is high Q
Q =
1
C
gs
R
g

1
C
gs
1
5g
m
= 5
f
T
f
= 5 15 = 75
The input resistance is going to be Q
2
R
g
28 k, or too
big.
The matching circuit will bring this down to about
12 k, a very poor match.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 12/29 p
Source/Emitter Degeneration
The voltage at the input of the
amplier is given by
v
x
= i
x
Z
gs
+ (i
x
+g
m
Z
gs
i
x
)Z
s
Z
in
= Z
s
+Z
gs
+ g
m
Z
gs
Z
s
. .
due to feedback
Lets assume that Z
s
is reactive
(zero noise)
g
m
Z
gs
Z
s
= g
m
1
jC
gs
jX =
g
m
X
C
gs
which produces a purely passive in-
put resistance if X > 0
Z
L
Z
in
Z
S
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 13/29 p
Inductive Degeneration
The reactive feedback from an
inductor produces a broadband
programmable real input impedance
that can simplify matching (or even
eliminate it altogether).
(Z
in
) =
g
m
L
C
gs

T
L
We thus select L by L =
R
s

T
If this value of L is impractical, we
can articially reduce
T
by inserting
a capacitor in shunt with C
gs
.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 14/29 p
Series Resonant Input
The input impedance of the FET
with inductive degeneration is
given by
Z
in
= jL
s
+
1
jC
gs
+
T
L
s
= jL
s
+
1
jC
gs
+R
s
+
v
s

L
g
L
s
R
s
Z
in
The input impedance behaves like a series RLC circuit.
We need to tune the resonant frequency of the series
circuit to align with the operating frequency. This can be
done by adding gate inductance L
g
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 15/29 p
Q Boosting
Recall that in a resonant circuit, the voltage across the
reactive elements is Q times larger than the voltage
across the resistor.
At resonance, the voltage across the resistors is simply
v
s
, so we have
v
gs
= Qv
s
i
d
= g
m
v
gs
= Qg
m
v
s
= G
m
v
s
Q =
1

0
C
gs
2R
s
G
m
= Qg
m
=
g
m

0
C
gs
2R
s
=
_

0
_
1
2R
s
+
v
s

L
g
L
s
R
s
+
Q
v
s

## A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 16/29 p

Equivalent Circuit at Resonance
From the source, the amplier input (ignoring C
gd
) is
equivalent to the following circuit
+
v
s

L
g
L
s
R
s

T
L
s
C
gs
At resonance, the complete circuit is as follows
+
v
s

R
s
R
s Q g
m
v
s
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 17/29 p
Noise Figure for Inductive Degen
C
gs
g
m
v
gs
r
o
+
v
gs

R
g
i
d
v
2
R
g
R
s
V
s
L
s
L
g i
o
Its fairly easy to calculate the noise for the case with
inductive degeneration. Simply observe that the input
generators (v
2
s
and v
2
g
) see a gain of G
2
m
to the output.
The drain noise i
2
d
, though, requires a careful analysis.
Since i
2
d
ows partly into the source of the device, it
activates the g
m
of the transistor which produces a
correlated noise in shunt with i
2
d
.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 18/29 p
Drain Noise (degen)
C
gs
g
m
v
gs
+
v
gs

i
d
i
o
L
g
R
s
L
s
The above equivalent circuit shows that the noise
component owing into the source is given by the
current divider
v

= (g
m
v

+i
d
)
jL
s
jL
s
+
1
jC
gs
+jL
g
+R
s

1
jC
gs
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 19/29 p
Drain Noise (degen)
The denominator simplies to R
s
at resonance, so we
have
v

= (g
m
v

+i
d
)
jL
s
R
s
1
jC
gs
= (g
m
v

+i
d
)
L
s
C
gs
R
s
v

_
1 +
g
m
L
s
C
gs
R
s
_
= i
d
L
s
C
gs
R
s
But
T
L
s
= R
s
, so we have
2v

= i
d
L
s
C
gs
R
s
or
g
m
v

=
i
d
2
g
m
L
s
C
gs
R
s
=
i
d
2
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 20/29 p
Total Output Noise (degen)
So we see that only 1/4 of the drain noise ows into the
output! The total output noise is therefore
i
2
o,T
= G
2
m
(v
2
s
+v
2
g
) +
1
4
i
2
d
F = 1 +
v
2
g
v
2
s
+
i
2
d
4v
2
s
G
2
m
Substitute as before and we have
F = 1 +
R
g
R
s
+
_

_
g
m
(2R
s
)
2
4R
s
_

t
_
2
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 21/29 p
Noise Figure with Degen
Note that the noise gure is the same as the common
source amplier
F = 1 +
R
g
R
s
+
_

_
g
m
R
s
_

t
_
2
The inductive degeneration did not raise the noise ! So
the minimum noise gure F
min
is the same.
The advantage is that the input impedance is now real
and programmable (
T
L
s
). By proper sizing, its
possible to obtain a noise and power match.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 22/29 p
LNA Chip/Package/Board Interface
PCB trace
package
bond wire
on-chip
spiral
Since the LNA needs to interface to the external world,
its input network must transition from the Si chip to the
package and board environment, which involves
macroscopic structures such as bondwires and
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 23/29 p
Bond Wire Inductance
One reason inductive degeneration is popular is
because we can use package parasitics to our benet.
Some or all of L
s
can be absorbed into the loop
inductance (or the partial inductance of the bondwire)
These parasitics must be absorbed into the LNA design.
This requires a good model for the package and
bondwires. It should be noted that the inductance of the
input loop depends on the arrangement of the
bondwires, and hence die size and pad locations.
Many designs also require ESD protection, which
manifests as increased capacitance on the pads.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 24/29 p
Package Parasitics
Recall that a changing ux generates an emf around a
circuit loop. Let
L =

I
v
emf
=
d
dt
= L
dI
dt
Note that in reality is composed of ux from all the
loops in the package, causing undesired mutual
coupling to other parts of the circuit
v
emf
=
d(
1
+
2
+
2
+ )
dt
= L
dI
1
dt
+M
12
dI
2
dt
+
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 25/29 p
Cascode LNA
V
cas
L
g
C
1
R
s
L
L
L
s
V
out
M1
M2
Z
in
V
in
V
dd
Its very common to use a
cascode device instead of a
common source device.
This simplies matching since
the cascode device is nearly
unilateral.
Lets show that the cascode
device adds virtually no noise
at low/medium frequencies.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 26/29 p
Cascode Noise Contribution
C
gs
g
m
v
gs
r
o
+
v
gs

i
d
i
o
The noise contribution
from the cascode is
small due to the degen-
eration. For simplicity
assume the transistor
degeneration is r
o
. Then
most of the drain noise
current will ow into C
gs
at high frequency
v

= (g
m
v

+i
d
)
1
jC
gs
v

(jC
gs
g
m
) = i
d
g
m
v

=
g
m
g
m
jC
gs
i
d
=
1
1 j

T
i
d
i
d
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 27/29 p
Cascode (cont)
A similar calculation shows that at low frequency, the
noise into r
o
produces an output current noise of
(i
d
+g
m
v

)r
o
= v

i
d
r
o
= v

g
m
r
o
v

= (1 +g
m
r
o
)v

=
r
o
1 +g
m
r
o
i
d
g
m
v

=
g
m
r
o
1 +g
m
r
o
i
d
i
d
The total current noise is therefore
_
1
g
m
r
o
1 +g
m
r
o
_
i
d
=
_
1
1 +g
m
r
o
_
i
d
0
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 28/29 p
Differential LNA Design
on-chip
inductors
bond-wire
inductance
bond-wire,
on-chip
or off-chip
One undesired
consequence of
the package is
that the parasitic
inductors vary from
part to part and
require careful
modeling and extra
care to correctly
implement the
LNA.
The advantage of a differential LNA is that the parasitics
are only on the gate side, and not on the source of the
transistors. The source inductors are realized with
on-chip inductors with tight process tolerances.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 14 p. 29/29 p