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4.0 Introduction 4.1 Objectives 4.2 Memory fundamentals 4.3 Main memory implementation 4.4 Cache memory 4. !irtual memory 4." #ummary 4.$ %uestions

&e have learnt that' the pro(rams and data reside in main memory of the computer durin( e)ecution. &e also *no+ that' the speed +ith +hich an instruction (ets e)ecuted is mainly dependent on the speed +ith +hich data can be transferred to or from the main memory. In this unit' +e +ill see different types of memories' its or(ani,ation and +or*in(' also the various techni-ues used to increase the effective speed' reduce the cost and si,e of main memory.

.t the end of this unit' you shall be able to define terms such as memory access time' memory cycle time' /ead Only Memory' /andom .ccess Memory understand the or(ani,ation and +or*in( of semiconductor /.M memories

discuss the use of /OM units as a part of main memory ' see the importance of 0/OM' 10/OM' 110/OM e)plain +hat cache memory is' and the interaction +ith main memory and C02 understand the importance of virtual memory system



3he ma)imum si,e of main memory that can be used in any computer is determined by the addressin( scheme. 4or e)ample' a 1"5bit computer can (enerate 1"5bit addresses and is capable of addressin( upto 2 po+er 1" 67 "4 89 memory locations. #imilarly' a machine +hich can (enerate 325bit addresses can use 2 po+er 32 6 7 4: 9 memory locations. ;ere "48' 4: memory locations represent the si,e of the address space of the computer. 3he memory address space is divided into number of memo ! "o #$' +here each +ord represents the smallest addressable unit of information or (roup of bits that is processed as a unit by the computer. . computer can be a "o #-%## e$$%&'e or &!(e-%## e$$%&'e this depends on the fi)ed number of characters in the address location. 3his is sho+n in fi(ure 4.1 F)*+ e 4.1 Or(ani,ation of the Main memory in a 325bit <yte5addressable computer &ord address 0 4 = 0 4 = > <yte address 1 2 " 10 3 $ 11


?ata transfer bet+een the main memory and C02 is throu(h the use of t+o C02 re(isters Memo ! A## e$$ Re*)$(e 6M./9 and Memo ! D%(% Re*)$(e 6M?/9 and it is sho+n in fi(ure 4.2 F)*+ e 4.2 Connection of the main memory to the C02

CPU k-bit address bus MAR n-bit data bus MDR

Main Memory

Upto 2 Addressable Locations Word length = n bits

Control lines (Read , write, MFC etc.)

@et M./ be *5bits lon(' M?/ be n5nits lon(. ?urin( memory cycle' n5bits of data are transferred bet+een main memory and C02. 3his transfer ta*es place over the memory bus A +hich consists of * address lines and n5data lines. 3o coordinate the transfer' the control lines /ead' &rite' Memory 4unction Complete 6M4C9 etc. are used. Memo ! A..e$$ ()me / It is the measure of the speed of memory units' i.e.' the time that elapses bet+een the initiation of an operation and the completion of that operation. 1)ample B time bet+een /ead and M4C Memo ! C!.'e ()me / It is the minimum time delay re-uired bet+een the initiation of t+o independent memory operations. 1)ample B t+o successive /ead operations

R%0#om A..e$$ Memo ! 1RAM2 B Is a main memory unit' +here any location can be accessed in some fi)ed amount of time for /ead or &rite operation. C%.3e memo ! / Is a small and fast memory that is placed bet+een the main memory and the C02. It holds the currently active se(ments of pro(ram and its data. V) (+%' memo ! / It is an important concept related to main memory or(ani,ation. It is assumed that the address (enerated by the C02 directly specify physical locations in main memory. <ut it is not so. 3he data may be stored in physical memory locations that have addresses different from those specified by the pro(ram. 3his infinite address space is *no+n as virtual memory. 3he mappin( of this virtual memory on to physical memory is throu(h a memory control unit called Memo ! M%0%*eme0( U0)(.


3he main memory is implemented throu(h the use of semiconductor inte(rated circuits.

Sem).o0#+.(o R%0#om A..e$$ Memo )e$ 1RAM2 /

#emiconductor memories are available in +ide ran(e of speeds. 3heir memory cycle times ran(e from a fe+ hundred nanoseconds to fe+ tens of nanoseconds. One reason for the popularity of semiconductor /.M in the implementation of main memory is that of its lo+er cost' and this is due to !ery @ar(e #cale Inte(ration 6!@#I9 technolo(y. #emiconductor memories may be divided into t+o types 1. <ipolar type 2. Metal O)ide #emiconductor 6MO#9 type

I0(e 0%' o *%0)5%()o0 o6 memo ! .3)7$ /

. memo ! .e'' is capable of storin( 15bit of information. . number of cells are or(ani,ed in the form of an array as sho+n in fi(ure 4.3 1ach ro+ of cells constitute a memo ! "o #. .ll cells of a ro+ are connected to a common line called "o # ')0e. 3he +ord line is driven by an address decoder on the chip. 3he cells in each column are connected by t+o lines *no+n as &)( ')0e$ to a $e0$e8" )(e .) .+)(. 3he senseC+rite lines in turn are connected to the input5output lines of the chip. F)*+ e 4.4 Or(ani,ation of <it cells in a memory chip )it lines b$ FF &o
A0 A1 A# A$

ord line


b0 FF


FF FF Me!or" cells

Address decoder


FF &1


Sense/ rite circuit Data bus &n'ut-out'ut lines ( b$

Sense/ rite circuit


%% R/


3he above fi(ure is an e)ample for 1" +ords of =5bit each' referred to as 1" ) = or(ani,ation. ?urin( read operation' the #ense C &rite circuit sense or read the information stored in the cells selected by a +ord line and transmit this information to the output data lines. ?urin( the &rite operation' the sense C +rite circuit receive input information and store it in the cells of the selected +ord. /C& C# system. is the control line that specify the re-uired operation. is the Chipselect line used to select a (iven chip in a multi5chip memory

1. B)7o'% Memo ! .e''

It is basically a stora(e cell' +ith t+o transistors 6+hich are inverted9 that form a basic flip flop. &here a flip flop is 15bit stora(e device. 3his is sho+n in fi(ure 4.4 F)*+ e 4.4 . <ipolar memory cell 3. ! b
R1*#0 + R#*#0 +





%2 ord line

<it lines

%1 and %2 are transistors that form a basic flip flop circuit. 3he cell is connected to a +ord line & and t+o bit lines b and bD. 3he bit lines are *ept at about 1."! and the +ord line at about 2. ! 6sli(htly hi(her than bit line9. 2nder these conditions' the diodes ?1 and ?2 are reverse5biased. 3herefore' no current flo+s throu(h the diodes and the cell is isolated from bit lines. Re%# o7e %()o0 / @et us assume that a E1D is stored in the cell +hen %1 is OF 6conductin(9 and %2 is O44 and a E0D is stored +hen %1 is O44 and %2 is OF. 3o read the contents of a (iven cell' the volta(e on the correspondin( +ord line is reduced from 2. ! to 0.3!6appro).9 . 3his causes one of the t+o diodes ?1 or ?2 to become for+ard5 biased' dependin( on +hether %1 or %2 is conductin(. .s a result' current flo+s from bit line b +hen the cell is in the 1 state and from bit line bD +hen the cell is in E0D state. 3he #ense C &rite circuit at the end of each pair of bit lines 'monitors the current on lines b and bD and sets the output bit lines accordin(ly. , )(e o7e %()o0 / &hen volta(e on the correspondin( +ord line 6+here it is to be +ritten9 is 0.3 !' the cells can be forced individually to either the E1D state by applyin( a positive volta(e 6appro). 3v9 to line bD or to E0D state by usin( line b. 3his function is performed by #ense C &rite circuit.

2. Me(%' O:)#e Sem).o0#+.(o memo )e$

Out of the t+o types of semiconductor memories B)7o'% %0# MOS; MOS technolo(y is very much used in Main Memory units. 3he reasons bein( 3hey allo+ hi(her bit densities on inte(rated circuit chips 3hey are easier to manufacture MO# transistors are hi(h5impedance devices' thus leadin( to lo+er po+er dissipation. <ut' there is one main problem +ith MO# devices' they operate at relatively slo+er speeds. 3he fi(ure 4. sho+s the simplest MO# cell confi(uration +hich is a 4lip flop.

3he operation is similar to that of bipolar type. 3he transistors 33 and 34 perform the same functions as that of resistors /1 and /2 of fi(ure 4.4' and transistors 3 and 3" corresponds to diodes ?1 and ?2 and acts as s+itches' under the control of the +ord line. &hen these t+o s+itches ate closed' the contents of the cell are transferred to the bit lines and +hen a (iven cell is selected' its contents can be over+ritten by applyin( appropriate volta(es on the bit lines. F)*+ e 4.< .n n5channel MO# memory cell confi(uration G ! b 33 34 bD

3 3"



&ord line <it lines

<oth bipolar and MO# cells re-uire continuous flo+ of current from the po+er supply throu(h one of the branches of the flip flop. if this current flo+ is maintained ' both cells are capable of storin( information indefinitely. ;ence they are referred to as S(%(). Memo )e$. D!0%m). Memo )e$ / this memory allo+s hi(her bit density and has lo+ po+er consumption compared +ith static memory. 3he information is stored in the

capacitor' in the form of a char(e. 3he stored information +ill be retained until the capacitor dischar(es. ;o+ever' to store the information for lon(er duration' cell contents must be refreshed periodically' by restorin( the capacitor char(e to its full value. 3he dynamic cell or(ani,ation is sho+n in fi(ure 4." belo+. F)*+ e 4.= 3he dynamic cell or(ani,ation &ord line

3 C )it line

3o store the information in a cell' an appropriate volta(e is applied to the bit line and the transistor 3 is turned on so' *no+n amount of char(e is stored in the capacitor C. Once the transistor is turned off' the capacitor be(ins to dischar(e' so information starts to lea*. ;ence the refreshin( circuits are re-uired to monitor and maintain the char(e on the capacitor.

Sem).o0#+.(o Re%# O0'! Memo )e$ 1ROM2 B

Is non5volatile memory' that is the contents of this memory can only be read and cannot be erased or over+ritten. #uch memories are used for storin( control pro(rams such as micro pro(rams' monitor pro(rams. . bipolar /OM cell is sho+n in fi(ure 4.$. 3he +ord line is held at a lo+ volta(e. 3o select a +ord' the volta(e of the correspondin( +ord line is momentarily raised' +hich causes all transistors to be turned OF. Connection of bit line to +ord line is throu(h a fuse. &hen a fuse is connected' the current flo+s from the po+er supply to the bit line' detectin( the bit as 1s and +hen disconnected' it is detected as 0s. similar confi(uration is available in MO# technolo(y.

F)*+ e 4.> <ipolar /OM cell 0o+er supply bit line

Connected for storin( a H1I' disconnected for storin( a H0I &ord line

-ROM 1- o* %mm%&'e Re%# O0'! Memo !2 / ?ata is +ritten into a /OM at the time of manufacture. ;o+ever' the contents can be pro(rammed by a user +ith a special 0/OM pro(rammer. 0/OM provides fle)ible and economical stora(e for fi)ed pro(rams and data. E-ROM1E %$%&'e - o* %mm%&'e Re%# O0'! Memo !2 / 3his allo+s the pro(rammer to erase the contents of the /OM and repro(ram it. 3he contents of 10/OM cells can be erased usin( ultra5violet li(ht usin( a 10/OM pro(rammer. 3his type of /OM provides more fle)ibility than /OM durin( the development phase of di(ital systems since' they are able to retain the stored information for lon(er duration and any chan(e can be easily made. EE-ROM1E'e.( ).%''! E %$%&'e - o* %mme Re%# O0'! Memo !2 / In this type of /OM' the contents of the cell can be erased electrically' by applyin( a hi(h volta(e. 3he 110/OM need not be removed physically for repro(rammin(.



Is a small and fast memory that is placed bet+een the main memory and the C02. It holds the currently active and more fre-uently used se(ments of pro(ram and its data. 3his is sho+n if fi(ure 4.=. In this approach ' the C02 need not al+ays fetch the pro(ram and data from the main memory instead it can (et it from the cache memory. ;ence' the total time of e)ecution is considerably reduced and it is more economical. F)*+ e 4.? C%.3e Memo ! Memory access control and data paths


Cac.e Me!or"

Main Me!or"

O7e %()o0 o6 % .%.3e memo !/ 3he cache memory is divided into number of bloc*s. &hen the C02 re-uests for an addressed +ord' it is transferred from the main memory to the cache. 3he memory5access control circuitry in the cache' chec*s +hether the re-uested +ord currently e)ists in the cache. I6 (3e e@+e$(e# "o # e:)$($ )0 .%.3e ' then the /ead or &rite operation is performed on the appropriate location in the cache. &hen the operation is /ead' the main memory is not involved. ;o+ever' if the operation is &rite' then there are t+o techni-ues follo+ed. In the first techni-ue *no+n as $(o e(3 o+*3' the main memory and cache locations are updated simultaneously. In the second techni-ue' only the cache location is updated and it is mar*ed as updated usin( #) (! or mo#)6)e# &)(. 3he main memory +ill be updated durin( s+appin(. I6 (3e e@+e$(e# "o # #oe$ 0o( e:)$($ )0 .%.3e; and the operation is /ead; then the bloc* of +ords that contain the re-uested +ord is loaded from the main memory into the cache and the re-uested +ord is for+arded to the C02. 3his

techni-ue is *no+n as 'o%#-(3 o+*3. &hen the operation is &rite' and the re-uested +ord is not in cache' then it is +ritten directly into the main memory. 3he correspondence bet+een the main memory and cache memory bloc*s are specified throu(h a m%77)0* 6+0.()o0. .nd mainly there are three mappin( functions B 1. ?irect mappin( techni-ue 2. .ssociative mappin( techni-ue 3. <loc* set associative mappin( techni-ue 3o brin( a ne+ bloc* into the cache +hen the cache is full' the cache controller must decide +hich old bloc* to over+rite . 3his is done +ith the help of e7'%.eme0( %'*o )(3m$.


In any computer system' if pro(rams and data does not fit into the physical main memory' then secondary stora(e devices such as ma(netic dis*s or tapes are used to hold them. 3his memory space problem is handled by the operatin( system. It automatically s+aps the pro(ram and data bet+een the main memory and the secondary stora(e' +henever they are re-uired for e)ecution. 3his techni-ue is *no+n as V) (+%' memo ! techni-ue. 3hus' the pro(rammer has an infinite si,e of main memory. 3he addresses of pro(ram and data bein( (enerated by the C02 are independent of the main memory. 3hese addresses are referred to as 'o*).%' or A) (+%' %## e$$e$. 3hese virtual addresses are translated into physical addresses by +hat is *no+n as V) (+%'-memo ! %## e$$ ( %0$'%()o0 me.3%0)$m. It is sho+n in fi(ure 4.> O7e %()o0$ o6 A) (+%' memo ! / 3he main memory and the secondary stora(e is divided into fi)ed len(th units called pa(es. 1ach pa(e consists of a bloc* of

+ords occupyin( conti(uous memory locations. &hile s+appin(' the entire pa(e is s+apped bet+een the main memory and the secondary device. F)*+ e 4.B !irtual5memory address translation physical address to main memory

!irtual address from C02

,a/e nu!ber word nu!ber

)lock nu!ber word nu!ber

Direct corres'ondence ,a/e table base re/ister

)lock nu!ber i0 'a/e is 'resent in !ain !e!or"

,ointer to secondar" stora/e i0 'a/e not 'resent in !ain !e!or"


block nu!ber or

,a/e table (i!'le!ented in !ain !e!or")

stora/e 'ointer

1ach virtual address consists of a pa(e number 6hi(h5order bits9 and +ord number 6lo+5order bits9. . 7%*e (%&'e in the main memory specifies the location of the pa(es that are currently in the main memory. 3he startin( address of pa(e table is *ept in a 7%*e (%&'e &%$e e*)$(e . <y addin( the pa(e number to the contents of pa(e table base re(ister' the address of the correspondin( entry in the pa(e table is obtained. 3he contents of the pa(e table location (ives the startin( address of the pa(e in the main memory' if the re-uired pa(e is currently in the main memory' other+ise it (ives the startin( address of the secondary stora(e. 3he control bits are used to indicate the presence or absence of pa(es in the main memory. It also indicates +hether the pa(e has been modified or not. . 7%*e 6%+'( occurs' +hen a pro(ram (enerates an access re-uests to a pa(e that is not in the main memory. In order to overcome this' the correspondin( +hole pa(e should be brou(ht from the secondary stora(e device into the main memory before the access re-uest is processed. 3he pa(e replacement al(orithm such as @east /ecently 2sed 6@/29' is used to replace pa(es' in case the main memory is full +ith the ones in the secondary stora(e.

3he main memory is one of the major components in any computer. Its characteristics such as si,e and speed play an important role in determinin( the capabilities of a (iven computer. .dvancements in technolo(y has made a (reat impact in lo+erin( the cost of semiconductor memories. <ipolar memories are very useful in the implementation of cache memories because of its hi(h speed' +here as MO# memories are used in the main memory because of its relative lo+ cost. 3he use of the virtual memory systems are increasin( rapidly because of its advanta(es. 3his chapter has sho+n the technical and or(ani,ational details of the main memory to some e)tent. 4urther' a student is as*ed to refer to any relevant te)t boo*s or materials for hi(h5end understandin(.

1. ?efine the follo+in( terms B memory access time' memory cycle time' cache memory' virtual memory 2. &hat is a semiconductor /.M J ;o+ is it classified J 3. ?escribe briefly the internal or(ani,ation of memory chips. 4. &hat is /OM' 0/OM' 10/OM and 110/OM J . ?ifferentiate bet+een static memories and dynamic memories. ". ;o+ does cache memory interact +ith the main memory and the C02 J $. ?escribe +ith necessary dia(ram the virtual memory system.