Intelligent Railway security System Using GPS & GSM

Introduction The railways Department, which is wholly owned by the public sector of the country. The government is seeking methods to improve the efficiency of this service with the main objective of providing a better service to the train commuters. However, the effort of the government is constrained by the lack of funding and inappropriateness of the current solutions. But the development of I T has revealed many options to uplift the railway service at a lower cost. !ccurate train positioning has been a fundamental re"uirement to improve the efficiency of the service. The current switch based train#tracking system used supports the train controllers to manage the train operation by providing the train$s location. The location data provided by this system lacks in dependability. %urthermore, the maintenance of the system accounts to a large portion of total cost incurred on the railway service. &ajority of these systems'especially outside the olombo (uburban !rea) offers low accuracy in terms of indicating the location of a train to the Train ontrollers. Installing the systems, which can accurately provide such readings are really e*pensive and the total cost of ownership is unbearable for (+,. The train safety has been an issue with the increasing number of incidents being reported that has caused death and injury. &ajority of deaths on the railway involve third parties with the incursion onto the level crossings. !verage train accident would cost millions of (ri +ankan rupees and these can be avoided if there is a mechanism to track the train location and speed and warn the locomotive drivers about possible safety issues. !dditionally, the train commuters also face difficulties due to fre"uent train delays, as the administration is unable to provide accurate schedules based on train$s location and speed. The solution is a comprehensive -.(/-(& based train tracking system, which provides accurate, dependable and timely information to the controller. The inbuilt -.( module identifies the train location with a highest accuracy and transfers the information to the central system via -(&. The availability of this information allows the Train ontroller to take accurate decisions as for the train location. +ocation data can be further processed to provide visual positioning using maps granting a wholesome view on train location. .ositioning data along with train speed helps the administration to identify the possible safety issues and react to them effectively using the communication methods provided by the system. !dditionally, the location information can be used to facilitate accurate scheduling with regard to train arrival and departure on each station. This information can also be made available for the commuters to identify any train delay in advance making this service more reliable.

System Architecture

System features Train will send various notifications to base station like time, distance and location details 0arious (&( will be e*changed within the train and base station (ecurity and routing messages will be shared with train on regular intervals speed information will be e*changed with the base station

Block Diagram Train Unit

Speed Sensor
'"D

AR! (ngine !otor "ontroller

!A# $%$ GS! !odem

!otor Driver

!A# $%$

G S !odem

Rail&ay "hain

Alarm Driver Bu**er

o&er Supply
Receiver:

GS! !o)ile

hone User

Block Diagram Description G S !odule: It relay position data to a . or other device using the 1&2! 3456 protocol. !lthough this protocol is officially defined by the 1ational &arine 2lectronics !ssociation '1&2!),7839 references to this protocol have been compiled from public records, allowing open source tools like gpsd to read the protocol without violating intellectual property laws.it can provide parameters like, longitude, latitude, time etc . +all Sensor It has been used in order to calculate speed of vehicle. It works on Hall 2ffect. It provide s output pulse per revolution of bus wheel it will help us to measure the speed of vehicle '"D Display It will display the current vehicle speed !icrocontroller The output signals from sensor are captured by &icrocontroller and compared with the standard set values it is also responsible for handballing -(& module via ,(#:6: interface. GS! !odule ! -(& module assembles a -(&/-.,( modem with standard communication interfaces like ,(#:6: '(erial .ort), ;(B etc., so that it can be easily interfaced with a computer or a microprocessor / microcontroller based system. The power supply circuit is also built in the module that can be activated by using a suitable adaptor. It is used to send/ receive (&( from users Alarm "ircuit and status '(DS it is a simple bu<<er system which will be turned on after an accident occurred, !lso the headlight of vehicle will start blinking in order to ensure the safety of vehicle. %, AR! ' " $-./ It is the heart of the entire system and used for data analysis and storage. It will capture the all the answers feed by users and will do the comparison with standard answers enter by system operator. !,&= is a generation of !,& processor designs. This generation introduced the

Thumb 4>#bit instruction set providing improved code density compared to previous designs. The most widely used !,&= designs implement the !,&v?T architecture, but some implement !,&v6 or !,&v8T2@. !ll these designs use a 0on 1eumann architecture, thus the few versions comprising a cache do not separate data and instruction caches.

The 1A. 'founded by .hilips) +. :4?5 is an !,&=TD&I#( based high#performance 6:#bit ,I( &icrocontroller with Thumb e*tensions 84:BB on#chip %lash ,C& with In#(ystem .rogramming 'I(.) and In#!pplication .rogramming 'I!.), 6:BB ,!&, 0ectored Interrupt ontroller, Two 43bit !D s with 4? channels, ;(B :.3 %ull (peed Device ontroller, Two ;!,Ts, one with full modem interface. Two I: serial interfaces, Two (.I serial interfaces Two 6:#bit timers, Datchdog Timer, .D& unit, ,eal Time lock with optional battery backup, Brown out detect circuit -eneral purpose I/C pins. .; clock up to >3 &H<, Cn#chip crystal oscillator and Cn#chip .++. %eatures and benefits :.4 Bey features E 4>#bit/6:#bit !,&=TD&I#( microcontroller in a tiny +F%.>? package. E 5 kB to ?3 kB of on#chip static ,!& and 6: kB to 84: kB of on#chip flash memory. 4:5#bit wide interface/accelerator enables high#speed >3 &H< operation. E In#(ystem .rogramming/In#!pplication .rogramming 'I(./I!.) via on#chip boot loader software. (ingle flash sector or full chip erase in ?33 ms and programming of :8> B in 4 ms. E 2mbeddedI 2 ,T and 2mbedded Trace interfaces offer real#time debugging with the on#chip ,eal&onitor software and high#speed tracing of instruction e*ecution. E ;(B :.3 %ull#speed compliant device controller with : kB of endpoint ,!&. In addition, the +. :4?>/?5 provides 5 kB of on#chip ,!& accessible to ;(B by D&!. E Cne or two '+. :4?4/?: vs. +. :4??/?>/?5) 43#bit !D s provide a total of >/4? analog inputs, with conversion times as low as :.?? s per channel. E (ingle 43#bit D! provides variable analog output '+. :4?:/??/?>/?5 only). E Two 6:#bit timers/e*ternal event counters 'with four capture and four compare channels each), .D& unit 'si* outputs) and watchdog. E +ow power ,eal#Time lock ',T ) with independent power and 6: kH< clock input

!n Introduction to the !,& = !rchitecture

The principle feature of the !,& = microcontroller is that it is a register based load#and# store architecture with a number of operating modes. Dhile the !,&= is a 6: bit microcontroller, it is also capable of running a 4>#bit instruction set, known as GTH;&BH. This helps it achieve a greater code density and enhanced power saving. Dhile all of the register#to# register data processing instructions are single#cycle, other instructions such as data transfer instructions, are multi#cycle. To increase the performance of these instructions, the !,& = has a three#stage pipeline. Due to the inherent simplicity of the design and low gate count, !,& = is the industry leader in low#power processing on a watts per &I. basis. %inally, to assist the developer, the !,& core has a built#in @T!- debug port and on#chip Gembedded I 2H that allows programs to be downloaded and fully debugged in#system. In order to keep the !,& = both simple and cost#effective, the code and data regions are accessed via a single data bus. Thus while the !,& = is capable of single#cycle e*ecution of all data processing instructions, data transfer instructions may take several cycles since they will re"uire at least two accesses onto the bus 'one for the instruction one for the data). In order to improve performance, a three stage pipeline is used that allows multiple instructions to be processed simultaneously. The pipeline has three stagesI %2T H, D2 CD2 and 2A2 ;T2. The hardware of each stage is designed to be independent so up to three instructions can be processed simultaneously. The pipeline is most effective in speeding up se"uential code. However a branch instruction will cause the pipeline to be flushed marring its performance. !s we shall see later the !,& = designers had some clever ideas to solve this problem. GS! !odem GS!0G RS module is used to establish communication between a computer and aGS!1 G RS system. Glo)al System for !o)ile communication 2GS!3 is an architecture used for mobile communication in most of the countries. Glo)al acket Radio Service 2G RS3 is an e*tension of -(& that enables higher data transmission rate. GS!0G RS module consists of a GS!0G RS modem assem)led together &ith po&er supply circuit and communication interfaces 'like ,(#:6:, ;(B, etc) for computer. The &CD2& is the soul of such modules.