MSP430 Family

Instruction Set Summary

Topics
5 5.1 5.2 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 Instruction Set Summary Symbols and Abbreviations Addressing Modes Instruction Set Summary Clock cycles, Length of Instruction Format I Instructions Format II Instructions Format III Instructions Miscellanous Instructions or Operators 5-3 5-4 5-5 5-6 5-8 5-8 5-9 5-9 5-9

Tables
Table 5.1 5.2 5.3 5.4 5.5 Title Symbols and Abbreviations used in the Instruction Set Summary Addressing Modes MSP430 Family Instruction Set Summary Format I Instructions Format II Instructions Page 5-4 5-5 5-6 5-8 5-9

Notes
Title 5.1 5.2 5.3 5.4 Page 5-5 5-7 5-8 5-9

Addressing Modes Emulated Instructions Cycle Time of the DADD Instruction Immediate mode in destination field

5-1

Instruction Set Summary MSP430 Family 5-2 .

5-3 .MSP430 Family Instruction Set Summary 5 Instruction Set Summary This chapter summarizes the MSP430 family instruction set.

Instruction Set Summary MSP430 Family 5.W or no suffix at the instruction memonic will result in a word operation Least significant Bit S-reg D-reg R1 or SP R3 or CG2 Rn @ --> TOS N Z . general purpose Immediate Data Absolute address 16-bit label Carry Bit Overflow Bit The suffix .B MSB LSB Table 5. general purpose Register indirect addressing Data transfer direction Top of Stack Negative Bit Zero Bit The suffix . Symbol Definition src As The source operand defined by As and S-reg The bits representing the addressing mode used for the source The used Working Register for the source src Register 2 or Status Register/Constant Generator 1 Working Register.1: Symbols and Abbreviations used in the Instruction Set Summary 5-4 .B at the instruction memonic will result in a byte operation Most significant Bit Symbol dst Ad Definition The destination operand defined by Ad and D-reg The bit representing the addressing mode used for the destination The used Working Register for the destination dst Register 1 or Stack Pointer Register 3 or Constant Generator 2 Working Register with n=4-15.1 Symbols and Abbreviations The following table lists the instruction set symbols and abbreviations used throughout the rest of this chapter.W R0 or PC Register 0 or Program Counter R2 or SR/CG1 R4 to R15 # & label C V .

The bit numbers show the contents of the As resp. Ad mode bits. X is stored in the next word (PC + X) points to the operand. Rn is incremented afterwards The word following the instruction contains the immediate constant N. Indexed Mode X(PC) is used The word following the instruction contains the absolute address.2: Addressing Modes Note: Addressing Modes The addressing modes using the PC as the working register use the normal effects of the addressing modes. 5-5 .MSP430 Family Instruction Set Summary 5. Rn is used as a pointer to the operand Rn is used as a pointer to the operand. As 00 01 Ad 0 1 Addressing Mode Register Mode Indexed Mode Syntax Rn X(Rn) Description Register contents are operand (Rn + X) points to the operand. The special addressing modes are caused by the pointing of the PC to the ROM word following the currently executed instruction. Indirect Autoincrement Mode @PC+ is used 01 1 Symbolic Mode ADDR 01 1 Absolute Mode &ADDR 10 11 - Indirect Register Mode Indirect Autoincrement Immediate Mode @Rn @Rn+ 11 - #N Table 5. X is stored in the next word.2 Addressing Modes All seven addressing modes for the source operand and all four addressing modes for the destination operand can address the complete address space.

dst src.src dst + C → dst (decimal) src + dst + C → dst (decimal) dst . V) = 1 Jump to Label unconditionally Jump to Label if Negative-bit is set 1 Status bit always set Status bit not affected * ADC(.. dst → dst src .B) BIC(.B) * DADC(. dst Branch to . dst → PC Clear destination Clear carry bit Clear negative bit Clear zero bit dst ..B) JC/JHS JEQ/JZ JGE JL JMP JN Legend: 0 x * dst src.B) BIS(. PC+2 → stack.dst dst src.B) * DINT * EINT * INC(.XOR. dst → dst src .2 → dst Disable interrupt Enable interrupt Increment destination..src .3: MPS430 Family Instruction Set Summary 5-6 .not.B) AND(.B) * INCD(.B) * INV(.dst src.and.dst src.B) * DEC(.XOR.and. dst → dst ..1 → dst dst .B) * CLRC * CLRN * CLRZ CMP(.and.dst src.B) ADDC(.dst dst dst dst src..B) DADD(. dst +1 → dst Double-Increment destination.dst src.or.Instruction Set Summary MSP430 Family 5.3 Instruction Set Summary Status Bits dst + C → dst src + dst → dst src + dst + C → dst src .B) ADD(.dst dst dst dst dst dst Label Label Label Label Label Label V x x x 0 0 x x x x x x x x - N x x x x x 0 x x x x x x x x - Z x x x x x 0 x x x x x x x x - C x x x x x 0 x x x x x x x x - Status bit always cleared Status bit cleared or set on results Emulated Instructions Table 5.B) * DECD(. V) = 0 Jump to Label if (N .B) BIT(.B) * BR CALL * CLR(.. dst+2→dst Invert destination Jump to Label if Carry-bit is set Jump to Label if Zero-bit is set Jump to Label if (N .

src → @SP Return from interrupt TOS → SR..B) * NOP * POP(.LSB → C C → MSB .dst Jump to Label if Carry-bit is reset Jump to Label if Zero-bit is reset src → dst No operation Item from stack.B) RETI Label Label src.B) * SBC(. The emulated instructions use core instructions combined with the architecture and implementation of the CPU for higher code efficiency and faster execution..B) PUSH(..2 → SP..dst src..MSP430 Family Instruction Set Summary Status Bits V x N x Z x C x JNC/JLO JNE/JNZ MOV(. Bit15 Test destination src . dst → dst 1 The Status Bit is set The Status Bit is not affected x x 0 x x x x 0 x x x x x x x 1 x x x x x x x x x x 1 x x x x x x x x x x 1 x x x x x The Status Bit is cleared The Status Bit is affected Emulated Instructions Table 5.LSB → C Subtract carry from destination Set carry bit Set negative bit Set zero bit dst + .B) RRA(.not.B) RRC(.B) SWPB SXT * TST(.B) * RLC(. SP + 2 → SP TOS → PC..xor.. SP + 2 → SP Rotate left arithmetically Rotate left through carry MSB → MSB ....B) * SETC * SETN * SETZ SUB(.not..3: MPS430 Family Instruction Set Summary (Concluded) Note: Emulated Instructions All marked instructions ( * ) are emulated instructions... SP+2 → SP SP ..dst dst dst dst src.. 5-7 .B) SUBC(. SP + 2 → SZP Return from subroutine TOS → PC.B) Legend: 0 x * dst dst dst dst dst src..src + 1 → dst dst + .B) XOR(.src + C → dst swap bytes Bit7 → Bit8 ...dst dst src * RET * RLA(.

#N 11.R5 XOR @R5. It depends on the instruction format and the addressing modes.R6 BR @R9+ MOV #20. x(Rm) 1. EDE 1.6(R9) CMP EDE. EDE 1.R8 BR R9 ADD R5. Rn 0. Rm 0.3(R6) XOR R8. &EDE 0. &EDE 3 6 2 5 11. x(Rn) 1.2(R4) ADD #33.4: Format I Instructions Note: Cycle Time of the DADD Instruction The DADD instruction needs 1 extra cycle. Length of Instruction The operating speed of the CPU is independent from individual instructions.4 Clock cycles. PC 1.EDE MOV R5. &EDE 01.Instruction Set Summary MSP430 Family 5.&EDE ADD @R5+.&TONI ADD EDE. TONI 01.8(R6) MOV @R5.&EDE ADD #33. Rn 1. EDE 1. 5-8 .TONI MOV 2(R5). Rm 1.PC 00. @Rn+ 11. #N 2 3 2 2 5 Table 5. @Rn 10. @Rn 0. EDE 01. Rm 01.EDE MOV @R9+. EDE 1. x(Rm) 1.R6 MOV &EDE.EDE XOR @R5. &EDE 1. Rm 0.4. The number of clock cycles refer to the internal oscillator frequency. x(Rm) 01.R9 BR #2AEh MOV @R9+.&EDE MOV 2(R5). &EDE 01.1 Format I Instructions #of cycles 1 2 4 Length of instruction 1 1 2 2 2 2 2 3 3 3 1 2 2 2 1 1 2 2 2 3 2 3 Example MOV R5.&TONI AND @R4. Rm 0.R7 AND EDE. &TONI 10. PC 0. @Rn+ 11. #N 11.&EDE Address Mode As Ad 00.R8 ADD 3(R4). x(Rm) 1. @Rn+ 11. x(Rn) 0. 5.

Rn 01. This would result in unpredictable program operation. @Rn 11. x(Rn) 01.4.instructions need all the same #-of-cycles independent of a successfull Jump or not.4.2 Format II Instructions Address Mode A(s/d) #of cycles RRC PUSH/ RRA CALL SWPB SXT 1 3/4 4 5 4 5 3 4 3 3 4/5 4/5 Length of instruction [words] Example 00. @Rn+ see Note 11. Length of instruction: 1 word. EDE 10. 5-9 .5: Format II Instructions Note: Immediate mode in destination field Instructions should not use immediate mode in the destination field. #N 1 2 2 1 1 2 SWPB R5 CALL 2(R7) PUSH EDE RRC @R9 SWPB @R10+ CALL #81h Table 5. 5.3 Format III Instructions Jxx . Length of Instruction: 1 word. Clock Cycle: 2 Cycle.4 RETI Interrupt Miscellanous Instructions or Operators Clock Cycle: Clock Cycle: 5 Cycle.MSP430 Family Instruction Set Summary 5. 5. 6 Cycle.4.

Instruction Set Summary MSP430 Family 5-10 .

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