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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006

Advanced Bus-Clamping PWM Techniques Based on Space Vector Approach


G. Narayanan, Member, IEEE, Harish K. Krishnamurthy, Di Zhao, and Rajapandian Ayyanar, Member, IEEE
AbstractConventional space vector pulsewidth modulation (CSVPWM) employs conventional switching sequence, which divides the zero vector time equally between the two zero states in every subcycle. Existing bus-clamping PWM (BCPWM) techniques employ clamping sequences, which use only one zero state in a subcycle. This paper deals with a special type of switching sequences, termed here as double-switching clamping sequences, which use only one zero state and apply an active vector twice in a subcycle. The present work brings out a class of bus-clamping PWM techniques, which employ such sequences. It is shown analytically as well as experimentally that the proposed BCPWM techniques result in reduced harmonic distortion in the line currents over CSVPWM as well as existing BCPWM techniques at high modulation indices for a given average switching frequency of SW . At high modulation indices, the dominant harmonic components in the line voltages are around 2 SW with the proposed BCPWM techniques, while the dominant components are around SW and 1.5 SW , respectively, with CSVPWM and existing BCPWM techniques. The proposed techniques also reduce the inverter switching losses at high power factors over CSVPWM and existing BCPWM techniques. Index TermsBus clamping pulsewidth modulation (BCPWM), discontinuous PWM, harmonic distortion, induction motor drives, PWM inverters, space vector PWM, stator ux ripple, switching sequences.

Fig. 1. Voltage vectors produced by a voltage source inverter. I, II, III, IV, V, angle of R-phase fundamental voltage. and VI are sectors. 

I. INTRODUCTION

N APPLICATIONS such as inverter fed ac drives and high power factor rectiers, the pulsewidth modulation (PWM) technique employed determines the dc bus utilization [1][6], and strongly inuences the quality of line current waveforms [1][11] and inverter switching losses [1][3], [11][15]. Sine-triangle PWM is a simple and popular technique. Third harmonic injection PWM (THIPWM) and conventional space vector PWM (CSVPWM) result in higher line side voltage and also less line current distortion than sine-triangle PWM. At higher line side voltages, discontinuous PWM or existing bus-clamping PWM (BCPWM) techniques result in still less distortion for a given average switching frequency of the inverter [1][6], [8], [9], [11]. This paper proposes a family of space vector-based bus-clamping PWM techniques, which

reduce the harmonic distortion further at line voltages close to the highest voltage in the linear modulation region. In sine-triangle PWM, THIPWM, and CSVPWM, every phase is switched once in every half carrier cycle or subcycle. In discontinuous PWM or existing BCPWM techniques, one phase is clamped, while the other two phases switch once each in every half carrier or subcycle. The proposed bus-clamping PWM techniques employ a special type of switching sequence in every subcycle. As a result, while one phase remains clamped, the second phase switches once, and the third phase switches twice in a subcycle. This paper studies the inuence of this special sequence on the spectral properties of the waveforms produced. II. SWITCHING SEQUENCES The eight switching states of a three-phase two-level voltage source inverter are as shown in Fig. 1. For a balanced threephase load, the voltage vectors produced by the inverter are as shown in the gure, where -axis and -axis are the reference axes of the stationary reference frame, while -axis and -axis are those of a synchronously revolving reference frame. The two zero states of the inverter produce a voltage vector of zero magnitude as shown in Fig. 1. The six active states produce an active voltage vector each. The six active vectors divide the space vector plane into six sectors as shown. The vectors are of equal magnitude, and are shown normalized with respect to the in the gure. dc bus voltage In space vector-based PWM techniques, the revolving reference vector (see Fig. 1) is sampled in every subcycle, . Given and angle in sector I as shown in a sample of magnitude Fig. 1, the active vector 1, the active vector 2 and the zero vector

Manuscript received February 2, 2005; revised September 9, 2005. This work was supported by the Ofce of Naval Research (ONR) under Awards N00014-02-1-0751 and N00014-05-1-0622. Recommended by Associate Editor S. Bernet. G. Narayanan is with the Department of Electrical Engineering, Indian Institute of Science, Bangalore 560012, India (e-mail: gnar@ee.iisc.ernet.in). H. K. Krishnamurthy, D. Zhao, and R. Ayyanar are with the Department of Electrical Engineering, Arizona State University Tempe, AZ 85287 USA (e-mail: harish.krishnamurthy@asu.edu; di.zhao@asu.edu; rayyanar@asu.edu). Digital Object Identier 10.1109/TPEL.2006.876854

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TABLE I SWITCHING SEQUENCES IN SIX SECTORS

Fig. 2. (a)(e) Different possible switching sequences in sector I.

Fig. 3. Existing bus-clamping PWM techniques (a) 60 clamp and (b) 30 clamp.

must be applied for durations shown in (1) [1][3]

and

, respectively, as

(1) Though the two active vectors and the zero vector must be applied for durations as in (1), these can be applied in different sequences within a subcycle as shown in Fig. 2. All these sequences involve only one switching per state transition. The multiplicity of possible switching sequences in a subcycle can be attributed to the following two factors. First, the zero vector can be applied either using the zero state 0 or the zero state 7. Conventional sequence 0127 [see Fig. 2(a)] applies the two zero states 0 and 7 for equal durations of time. Clamping sequences 012 and 721 [see Fig. 2(b) and (c)] use only in a subcycle. These one zero state for the entire duration result in clamping of a phase to one of the dc buses [1][3]. Second, a given active vector need not be applied continually for the required duration. For example, the active vector 1 can be applied over two intervals of time within the subcycle adding [1], [7], [10], [14], [15]. Such multiple application of up to an active vector within a subcycle leads to sequences 0121 and 7212 shown in Fig. 2(d) and (e). These sequences, respectively, divide and into equal halves [7], [10], [15]. More such sequences are also possible [15]. Sequence 7212 leads to clamping of -phase to the positive dc bus, while sequence 0121 results in clamping of -phase to the negative dc bus. Both sequences result in -phase switching twice in a subcycle. Hence, sequences 0121 and 7212 are termed double-switching clamping sequences here. The sequences illustrated in Fig. 2 are employed in sector I. The equivalent sequences in the other sectors are as listed in Table I.

A closed-loop PWM technique [14] and a few open-loop PWM techniques [1], [7], [10], [15] for ac drives employ double-switching clamping sequences. In most cases these sequences are used only at high speeds [1], [14] or only in select spatial regions [7], [10], [15] with other sequences employed elsewhere. This paper brings out a family of open-loop BCPWM techniques, which employ only the double-switching clamping sequences. The line current distortion due to the proposed techniques are studied and compared against those due to CSVPWM and existing BCPWM. III. PROPOSED BUS-CLAMPING PWM TECHNIQUES A popular existing bus-clamping method clamps every phase during the middle 60 duration in every half cycle of its fundamental voltage. Another well-known method clamps every phase during the middle 30 duration in every quarter cycle of its fundamental voltage. These two techniques are, respectively, termed as 60 clamp and 30 clamp. The former employs in the rst half, and 012, 210, in the sequences 721, 127, second half of sector I as shown in Fig. 3(a). It is vice versa in case of the latter as shown in Fig. 3(b) [1][13]. The change in zero state is made at the middle of every sector in case of 60 clamp and 30 clamp. More generally, the zero , where state used can be changed at any spatial angle is between 0 and 60 , as shown in Fig. 4(a) and (b). In Fig. 4(a), every phase is clamped continually for 60 duration in every half cycle of the fundamental voltage waveform. These techniques can be termed continual clamping techniques. In Fig. 4(b), the 60 clamping duration is split into one interval of width in the rst quarter cycle and another interval ) in the next quarter in every half cycle. Since the of (60 clamping duration is split into two intervals, these techniques are termed split clamping PWM techniques. Fig. 5(a) and (b) present average pole voltage waveforms that illustrate the two 45 . Interestingly, despite extensive types of clamping for research on existing BCPWM techniques [1][6], [8], [9],

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Fig. 4. Existing bus-clamping PWM techniques (a) continual clamping type and (b) split clamping type.

Fig. 5. Average pole voltage over a fundamental cycle for V 0.722 corresponding to (a) continual clamping and (b) split clamping both with 45 .

Fig. 7. Stator ux ripple vector over a subcycle and its components along q -axis and d-axis corresponding to sequences (a) 0127, (b) 012, (c) 721, (d) 0121, and (e) 7212.

Fig. 6. Proposed bus-clamping PWM techniques (a) continual clamping type and (b) split clamping type.

[11][13], not much appears to have been reported on split 0 30 and 60 . clamping methods except for The proposed PWM techniques employ sequence 0121 instead of 012, and sequence 7212 instead of 721 as illustrated in Fig. 6. As with existing BCPWM, a proposed BCPWM technique may fall under either continual clamping type [Fig. 6(a)] or split clamping type [Fig. 6(b)]. Further, the proposed PWM technique may use a particular value of or might choose a value of according to a set policy. IV. ANALYSIS OF HARMONIC DISTORTION In any arbitrary subcycle, the applied voltage balances the reference voltage only in an average sense, and not in an instantaneous sense. The time integral of the instantaneous error between the applied voltage and the reference voltage is a measure of the line current ripple in the inverter [8][12]. The integral of the instantaneous error voltage vector is termed here as the stator ux ripple vector [10]. The stator ux ripple vector over a subcycle corresponding to sequences 0127, 012, 721, 0121, and 7212 in a synchronously

revolving reference frame are shown in Fig. 7(a)(e), respectively. The components of the ux ripple vector along -axis and -axis are also shown, where the quantities and are as dened in (2). Same values of and have been assumed for all sequences. However, the subcycle duration is for sequences 0127, 0121, and 7212, while it is 2 3 for 012 and 721. This enables comparison of the different sequences at a given average switching frequency

(2a) (2b) (2c) (2d) The RMS stator ux ripple over a subcycle corresponding to a sequence SEQ is designated as , where 0127, 012, can be expressed 721, 0121, or 7212. Referring to Fig. 7, as shown in

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(3a)

(3b)

(3c)

Fig. 8. Analytically evaluated total RMS harmonic distortion factor F against fundamental frequency at a switching frequency of 3 kHz. (a) CSVPWM, (b) existing continual clamping PWM with 30 , (c) existing continual or split clamping PWM with 0 or 60 , (d) existing split clamping PWM with 30 , (e) proposed continual clamping PWM with 30 , (f) proposed continual or split clamping PWM with 0 or 60 , and (g) proposed split clamping PWM with 30 .

A. Analysis of Proposed BCPWM Techniques (3d) The harmonic distortion factor is calculated as shown in (5a), if the proposed PWM technique is of continual clamping type. The calculation is as shown in (5b), if the proposed technique is of split clamping type

(5a)

(3e) The RMS stator ux ripple over a sector, normalized with respect to the fundamental ux , yields the total RMS harmonic distortion factor based on the notion of stator ux ripple [10] as shown in (4a). The expression for is given in (4b), is the fundamental frequency where

(5b) The harmonic distortion factor is proportional to the RMS stator ux ripple over a sector as shown in (4) and (5). The mean square ripple over a sector is the average of mean square ripple over subcycles that constitute a sector. Of the two sequences considered, sequence 0121 is better in the rst half of sector I as it leads to less mean square ripple over a subcycle, while sequence 7212 results in less ripple in the second half for a given as shown in (6). The inequalities in (6) follow from the and in (3). Further, the RMS ripple expressions for due to 0121 for an angle equals the RMS ripple due to 7212 as shown in for an angle (60 - ) for a given (6a) (6b) (7) 30 employs the The continual clamping technique with worse sequence throughout the sector, while the split clamping 30 uses the better sequence throughout. technique with

(4a) (4b) can be expressed as a function For a given technique, or since the fundamental voltage is maintained proof drive. portional to the fundamental frequency in a constant corresponding to different PWM techCalculation of niques is presented in the following subsections. The results are shown plotted in Fig. 8.

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Fig. 9. Variation of normalized switching energy loss E in an inverter leg over a fundamental cycle for existing BCPWM techniques: (a) continual clamping, 30 ;  0 ; (b) split clamping, 0 ; (c) continual clamping, 90 (lag); and (d) split clamping, 90 (lag). 30 ;  30 ;  30 ;  The average switching loss over a cycle (dashed lines) and the absolute value of the fundamental phase current (dotted lines) are also shown.

Hence the former leads to the highest distortion, while the latter results in the lowest distortion among the proposed techniques as shown in Fig. 8. All proposed techniques for any given 0 or 60 use the better sequence in one with either half of the sector and the worse sequence in the other half. These techniques result in equal distortion as seen from Fig. 8. The mean square ripple over a sector due to any such technique is the average of those due to continual clamping technique with 30 and split clamping technique with 30 . More generally, in continual clamping, the better sequence 30 and , i.e., for a duration is used between 30 in every sector with the worse sequence used of during the remaining duration. Hence the harmonic distortion 30 . In case of split clamping, decreases with increase in 30 in every the worse sequence is used for a duration of sector. Hence the harmonic distortion decreases with decrease 30 . in 30 30 and the remaining duration Note that 60 30 30 . The better of the two sequences is applied for a longer duration in case of split clamping, while the worse sequence is applied longer with continual clamping. Hence split clamping leads to lower harmonic distortion than continual clamping for a given dc bus voltage and line voltage. B. Analysis of Existing BCPWM Techniques Sequence 012 leads to less RMS current ripple over a subcycle than 721 in the rst half of the sector, and vice versa in the second half of the sector (8a) (8b) (9) The inequalities in (8) are similar to those in (6). This is the case with (9) and (7) as well. Hence, the conclusions arrived at for the proposed BCPWM techniques apply qualitatively to the existing BCPWM techniques as well. Among the existing BCPWM techniques, continual clamping 30 leads to the highest harmonic distortion technique with and split clamping technique with 30 leads to the lowest harmonic distortion for a given line-side fundamental voltage

(see Fig. 8). The harmonic distortion due to any existing split clamping technique is less than or equal to the distortion pro. duced by any continual clamping technique at any given C. Switching Sequences and Current Ripple Fig. 7 shows that the conventional sequence 0127 leads to the lowest -axis ripple. With other sequences the -axis ripple increases, but the -axis ripple decreases. The peak -axis ripple for 012 and 721 is two thirds that for 0127. Sequences 0121 and 7212 provide scope for further reduction in -axis ripple. With equal division of active vector time, the peak -axis ripple is only half that of 0127. , the -axis ripple dominates over the -axis At low ripple. Hence current ripple is lowest with conventional sequence 0127, and CSVPWM results in the lowest distortion. increases, the -axis ripple becomes increasingly As dominant over the -axis ripple. Hence, sequences 012 and 721 lead to reduced current ripple. The existing BCPWM techclose niques result in less distortion than CSVPWM. At to the highest fundamental voltage, when -axis ripple is all the more dominant, sequences 0121 and 7212 result in least current ripple. The proposed BCPWM techniques result in reduced distortion over CSVPWM and existing BCPWM in this range. A judicious ratio of division of active vector time and more frequent transitions between the two active states help reduce RMS current ripple as line-side fundamental voltage increases. and one of the CSVPWM can be used at lower to reduce distortion at BCPWM techniques at higher . For an existing a given average switching frequency BCPWM technique to be used at higher line voltages, the . The proposed BCPWM sampling frequency must be 3 techniques have the advantage of reducing the distortion at with the same sampling frequency as that of higher . CSVPWM, namely 2 0.722, If the magnitude of the reference vector conventional sequence may be used in the given subcycle. If 0.722, then double-switching clamping sequence can be used. The sampling frequency must be twice the average switching frequency throughout. This leads to reduction in line current distortion in the range 5060 Hz. Since the RMS current

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Fig. 10. Variation of normalized switching energy loss E in an inverter leg over a fundamental cycle for proposed BCPWM techniques: (a) continual clamping, 30 ;  90 (lag). 0 ; (b) split clamping, 0 ; (c) continual clamping, 90 (lag); and (d) split clamping, 30 ;  60 ;  30 ;  The average switching loss over a cycle (dashed lines) and the absolute value of the fundamental phase current (dotted lines) are also shown.

ripple due to conventional and double-switching clamping se0.722, the transition quences are almost equal around from one sequence to the other is fairly smooth with current transient being low. Though the dominance of -axis ripple over -axis ripple is , it also depends on . Even for primarily determined by higher values of , when is closer to 0 or 60 , the -axis ripple tends to be less dominant. On the other hand, when is around 30 , the -axis ripple is more dominant. Hence a more rened choice of switching sequence must be based on both and . Hybrid PWM techniques [15] make such a rened choice at the expense of moderately higher computational complexity, and result in reduced harmonic distortion. V. INVERTER SWITCHING LOSSES This section presents a comparison of inverter switching losses due to CSVPWM, existing BCPWM techniques and proposed BCPWM techniques. The effect of the type of clamping and the positioning of the clamping duration on switching losses is studied for both existing and proposed BCPWM. The study brings out the appropriate type of clamping and the optimal value of for minimization of switching loss with both existing and proposed BCPWM. A. Normalized Switching Loss The switching energy loss in a subcycle in an inverter leg is proportional to the phase current and the number of switchin the given subcycle. The normalized ings of the phase in an inverter leg is switching energy loss per subcycle as dened in (10a), where is the fundamental phase current, is the peak phase fundamental current and is the line-side power factor angle. The ripple current can be ignored for calculation of switching losses. The dc bus voltage and the device switching times can be assumed to be fairly constant (10a) (10b) over a fundamental cycle, shown The average value of in (10b), gives the average switching energy loss per subcycle.

This must be multiplied by the number of subcycles per second, , to obtain a measure of the i.e., the sampling frequency for inverter switching loss. The sampling frequency is CSVPWM and the proposed BCPWM techniques, while it is for the existing BCPWM techniques. over a fundamental cycle for The variation of CSVPWM is shown in dotted lines in Figs. 9 and 10. The for average value over a fundamental cycle or 0.637. The normalized switching CSVPWM equals 2 loss due to a given PWM technique can be obtained as given in (11a). The normalized switching loss due to existing BCPWM and proposed BCPWM techniques are as given in (11b) and (11c), respectively (11a) (11b) (11c) B. Type of Clamping When the line side power factor is unity, existing continual 30 clamps a phase around its current clamping PWM with over peak, and thus, leads to a signicant reduction in CSVPWM as shown in Fig. 9(a). Split clamping PWM with 30 is less effective in this regard as seen from Fig. 9(a) and (b). At zero power factor (lag), the best value of for continual clamping from the point of view of switching losses is 60 [11]. 60 is less effective than split Continual clamping with 30 at zero power factor (lag) as seen from clamping with Fig. 9(c) and (d) [12]. for the proposed continual clamping The variation in 30 at unity power factor is shown in Fig. 10(a). Since with a phase is clamped around its current peak, there is a substantial saving in switching energy loss as seen. As the double-switching of a phase is only around the current zero-crossings, there is not much increase in the energy lost. Overall there is a substantial 30 is not so energy saving. Proposed split clamping with at unity power factor as seen effective in reducing from Fig. 10(b). For zero power factor (lag), a comparison of

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TABLE II OPTIMAL VALUE OF FOR MINIMUM SWITCHING LOSS

switching energy lost due to proposed continual clamping with 60 and proposed split clamping with 30 are presented in Fig. 10(c) and (d). As seen, split clamping leads to less switching loss than continual clamping at zero power factor. Thus, both in existing as well as proposed BCPWM techniques, continual clamping is better in terms of switching losses at power factors close to unity, while split clamping is better at power factors close to zero. A more detailed analysis is presented in the following sections. C. Position of Clamping Duration In addition to type of clamping, the value of inuences the switching losses signicantly for both existing and proposed BCPWM techniques. Expressions for normalized switching loss corresponding to the four classes of BCPWM techniques - existing continual clamping, existing split clamping, proposed continual clamping and proposed split clamping are given in (12a)(12d), respectively

for

(12d)

for

for

(12a)

for

for

for

(12b)

for

for

for

(12c)

for

for

The normalized switching loss corresponding to the existing as well as the proposed BCPWM techniques depends on the power factor angle as seen from (12). The value of can be varied in accordance with power factor angle to achieve reduction in switching losses. The optimal value of , subject to the 60 , for the four classes of BCPWM techcondition 0 niques are tabulated in Table II. Fig. 11(a) and (b) present the variation in normalized with power factor angle (lagging) for switching loss existing BCPWM and proposed BCPWM techniques, respec90 (lag), the switching loss tively. Over the range 0 30 is corresponding to existing continual clamping with 0 , when a phase is clamped around its current lowest at 90 (lag) as seen peak. The switching loss is highest at 90 (lag), a phase is clamped from curve B in Fig. 11(a). At around its zero-crossings, rendering the reduction in switching loss not very signicant. For a similar reason, the switching 30 is loss corresponding to existing split clamping with 45 as seen from curve C in Fig. 11(a). One of highest at the 30 clamping intervals is around the current zero-crossing, though the other 30 clamping interval is around the current peak. Lengthening the clamping interval around the current peak and shortening the clamping interval around the current zero-crossing will lead to reduction in switching loss under such a condition. For both continual and split clamping, use of optimal value of as tabulated in Table II (instead of a xed value of 30 reduces the switching loss signicantly. This is seen by comparing curves B and D and also curves C and E in Fig. 11(a). With proposed BCPWM techniques, a phase double switches 0 [see Fig. 10(a) and around its current zero-crossings at 90 [see Fig. 10(c) and (b)] and around its current peak at 90 (lag), the switching loss is (d)]. Over the range 0 0 and highest at 90 for both continual and lowest at 30 [see curves F and G in Fig. 11(b)]. split clamping with With the proposed BCPWM techniques, the double switching region cannot be shifted, and is xed around the zero-crossings of the fundamental voltage. Only the clamping duration can be adjusted in accordance with as in the case of existing BCPWM. It is worth noting that the solution for optimal is identical for both existing as well as proposed BCPWM techniques (see Table II). Use of optimal value of reduces the switching loss substantially in case of both continual clamping as well as split clamping as seen from Fig. 11(b). The curves in Fig. 11(a) and (b) clearly indicate the superiority of continual clamping at high power factors and that of

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Fig. 11. Normalized switching loss against power factor angle for various PWM techniques: (a) CSVPWM (curve A), existing continual clamping with 30 (curve B), existing split clamping with 30 (curve C), existing continual clamping with optimal (curve D), and existing split clamping PWM with optimal (curve E), (b) CSVPWM (curve A), proposed continual clamping with 30 (curve F), proposed split clamping with 30 (curve G), proposed continual clamping with optimal (curve H), and proposed split clamping PWM with optimal (curve I), and (c) CSVPWM (curve A), generalized discontinuous PWM (curve D), minimum switching loss existing BCPWM (curve J), and minimum switching loss proposed BCPWM (curve K).

TABLE III MINIMUM SWITCHING LOSS PWM

split clamping at low power factors from the point of view of switching losses. The results obtained here for lagging power factors can easily be extended to leading power factors as well. D. Minimum Switching Loss PWM as explained in Continual clamping with optimal Section V.C has been referred to as generalized discontinuous PWM in [11]. The normalized switching loss due to generalized discontinuous PWM is shown plotted in Fig. 11(c) (curve D) for the entire range of power factor angle. At a given , this technique reduces the average switching frequency switching loss effectively at high power factors as seen from Fig. 11(c). The switching loss can be reduced at low power factors by resorting to split clamping as mentioned earlier.

With existing BCPWM, if the switching loss must be minimized, then the type of clamping and the value of must be as shown in Table III. Such a technique is termed here as minimum switching loss existing BCPWM. For minimizing switching loss with proposed BCPWM, the type of clamping and the value of must be as shown in the last row of Table III. This technique is termed minimum switching loss proposed BCPWM here. Curves J and K, respectively, in Fig. 11(c) show the normalized switching loss corresponding to these two techniques. At unity power factor, the reduction in switching loss with ex30 over CSVPWM is 25% isting continual clamping with . Under such condition, the proposed continual at a given 30 leads to a higher reduction of about 36% clamping with in switching loss over CSVPWM as seen from Fig. 11. With a

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Fig. 12. Measured spectra of line-line voltage (PWM of R-phase minus PWM of Y-phase) for V 0.289; F 20 Hz, F 3 kHz corresponding to (a) CSVPWM, (b) existing split clamping PWM with 30 , (c) proposed continual clamping PWM with 30 , and (d) proposed split clamping PWM with 30 .

Fig. 13. Measured spectra of line-line voltage (PWM of R-phase minus PWM of Y -phase) for V 0.866; F 60 Hz, F 3 kHz corresponding to (a) CSVPWM, (b) existing split clamping PWM with 30 , (c) proposed continual clamping PWM with 30 , (d) proposed continual clamping PWM 60 , (e) proposed split clamping PWM with 60 and (f) proposed split clamping PWM with 30 . with

= =

= =

proper choice of type of clamping and , proposed BCPWM can lead to reduced switching losses over CSVPWM as well as existing BCPWM for power factors greater than 0.866. In particular, proposed BCPWM can lead to reduction in switching loss over CSVPWM for power factors (both leading and lagging) greater than 0.5.

VI. EXPERIMENTAL INVESTIGATION Four techniques representative of the family of proposed BCPWM techniques are tested on a 2-hp, 208-V, 60-Hz, induction motor drive fed from a three-phase constant 2-kW Intelligent Power Module based inverter. TMS320C243

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Fig. 14. Measured no-load current (in amperes) at V 0.866; F 60 Hz, F 3 kHz corresponding to (a) CSVPWM, (b) existing split 30 , (c) proposed continual clamping PWM with clamping PWM with 30 , and (d) proposed split clamping PWM with 30 . The measured are (a) 0.1513, (b) 0.1311, (c) 0.1153, and (d) 0.1029. values of I

=
against F (in Hz) for F Fig. 15. Measured no-load I 3 kHz CSVPWM, proposed continual clamping PWM with 30 , and proposed split clamping PWM with 30 .

DSP-based digital controller is used as the controller platform. The four proposed techniques are (a) continual clamping with 30 , (b) continual clamping with 60 , (c) split 60 and (d) split clamping with 30 . clamping with The total harmonic distortion factor of the no-load motor current is taken as the performance index for comparison of the proposed techniques against CSVPWM and existing split clamping 30 , which offers the lowest distortion among PWM with existing BCPWM techniques (see Section IV-B). This distorand are the RMS tion factor is dened in (13), where values of the no-load current and its fundamental component, respectively [1], [2]

line current distortion with any of the proposed techniques is less than that due to CSVPWM and existing BCPWM as demonstrated by the measured no-load current waveforms in Fig. 14. These experimental observations are in conformity with the theoretical predictions shown in Fig. 8. , Fig. 15 presents a comparison of measured no-load corresponding to CSVPWM, proposed continual clamping with 30 and proposed split clamping with 30 , over a range of fundamental frequency, namely from 40 to 60 Hz. The in Fig. 15 agree well with the relative values of measured in Fig. 8, conrelative values of analytically evaluated rming the reduction in line current distortion with the proposed techniques over CSVPWM. VII. CONCLUSION A class of bus-clamping PWM (BCPWM) techniques, which employ only the double-switching clamping sequences, is proposed. The proposed BCPWM techniques are studied, and are compared against conventional space vector PWM (CSVPWM) and existing BCPWM techniques at a given average switching . frequency With the proposed BCPWM techniques, the dominant harmonic components in the line voltage waveforms are found to at high modulation indices, while the domibe around 2 and 1.5 , respectively, nant components are around with CSVPWM and existing BCPWM techniques. The proposed family of BCPWM techniques result in less line current distortion than CSVPWM and the existing BCPWM techniques at high line voltages close to the highest line side voltage during linear modulation. The analysis presented explains the difference in distortion due to the different techniques. The study classies both the existing BCPWM and the proposed BCPWM techniques into two categories, namely continual clamping methods and split clamping methods, depending on the type of clamping adopted. It is shown that split clamping methods are better than continual clamping ones in terms of line current distortion. In terms of switching losses, continual clamping is better at high power factors, while split clamping is superior at low power factors. Further to the type of clamping, the inuence of the position of the clamping interval on the harmonic distortion is brought

(13) Measured line voltage spectra corresponding to CSVPWM, existing BCPWM and proposed BCPWM are compared at two 20 Hz where the proposed techfrequencies, namely at niques lead to higher harmonic distortion and also at 60 Hz where the proposed techniques result in lower harmonic distortion over comparable techniques. The average switching is 3 kHz in all the cases. frequency 0.289 Fig. 12 presents the line voltage spectra at 20 Hz. Clearly, the individual voltage harmonics are and much higher with the proposed techniques, compared to those of CSVPWM and existing BCPWM. Hence, the line current distortion must be higher as predicted in Fig. 8. 0.866 Fig. 13 compares the measured spectra at 60 Hz. With CSVPWM and existing BCPWM, and (3 kHz) the dominant harmonic components are around (4.5 kHz), respectively. With the proposed and 1.5 BCPWM techniques, the harmonic voltages are around 2 3 as with CSVPWM. At lower moduare dominant as lation indices, the components around shown in Fig. 12(c) and (d). At higher modulation indices, the become dominant over those around components around 2 as demonstrated by Fig. 13(c)(f). Since the dominant (6 kHz) components are at higher frequencies of around 2 with the proposed BCPWM techniques, the ltering by the leakage inductance of the motor is better. Consequently, the

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out for both existing and proposed BCPWM techniques. The optimal position of the clamping interval is determined for existing continual clamping, existing split clamping, proposed continual clamping, and proposed split clamping methods. With an appropriate type of clamping and position of clamping interval, the inverter switching losses can be considerably reduced with proposed BCPWM over CSVPWM at power factors greater than 0.5 and over existing BCPWM at power factors greater than 0.866. REFERENCES
[1] J. Holtz, Pulsewidth modulationA survey, IEEE Trans Ind. Electron., vol. 39, no. 5, pp. 410420, Dec. 1992. [2] J. Holtz, Pulsewidth modulation for electronic power conversion, Proc. IEEE, vol. 82, no. 8, pp. 11941214, Aug. 1994. [3] D. G. Holmes and T. A. Lipo, Pulse Width Modulation for Power Converters: Principle and Practice. New York: Wiley, 2003. [4] V. Blasko, Analysis of a hybrid PWM based on modied space-vector and triangle-comparison methods, IEEE Trans. Ind. Appl., vol. 33, no. 3, pp. 756764, May/Jun. 1997. [5] D.-W. Chung, J.-S. Kim, and S.-K. Sul, Unied voltage modulation technique for real-time three-phase power conversion, IEEE Trans. Ind. Appl., vol. 34, no. 2, pp. 374380, Mar./Apr. 1998. [6] K. Zhou and D. Wang, Relationship between space-vector modulation and three-phase carrier-based PWM: A comprehensive analysis, IEEE Trans Ind. Electron., vol. 49, no. 1, pp. 186196, Feb. 2002. [7] G. Narayanan and V. T. Ranganathan, Synchronised PWM strategies based on space vector approach. Part 1: Principles of waveform generation, Proc. Inst. Elect. Eng., vol. 146, no. 3, pp. 267275, May 1999. [8] H. W. van der Broeck, Analysis of the harmonics in voltage fed inverter drives caused by PWM schemes with discontinuous switching operation, in Proc. EPE91, Firenze, Italy, 1991, pp. 261266. [9] S. Fukuda and K. Suzuki, Harmonic evaluation of two-level carrierbased PWM methods, in Proc. EPE97, Trondheim, Norway, 1997, pp. 331336. [10] G. Narayanan and V. T. Ranganathan, Analytical evaluation of harmonic distortion in PWM AC drives using the notion of stator ux ripple, IEEE Trans. Power Electron., vol. 20, no. 2, pp. 466474, Mar. 2005. [11] A. M. Hava, R. J. Kerkman, and T. A. Lipo, Simple analytical and graphical methods for carrier-based PWM-VSI drives, IEEE Trans. Power Electron., vol. 14, no. 1, pp. 4961, Jan. 1999. [12] J. Kolar, F. C. Zach, and H. Ertl, Inuence of the modulation method on conduction and switching losses of a PWM converter system, IEEE Trans Ind. Appl., vol. 27, no. 6, pp. 10631075, Nov./Dec. 1991. [13] A. M. Trzynadlowski and S. Legowski, Minimum-loss vector PWM strategy for three-phase inverters, IEEE Trans. Power Electron., vol. 9, no. 1, pp. 2634, Jan. 1994. [14] J. Holtz and E. Bube, Field-oriented asynchronous pulse-width modulation for high-performance ac machine drives operating at low switching frequency, IEEE Trans. Ind. Appl., vol. 27, no. 3, pp. 574581, May/Jun. 1991. [15] D. Zhao, G. Narayanan, and R. Ayyanar, Switching loss characteristics of sequences involving active state division in space vector based PWM, in Proc. IEEE APEC04, 2004, pp. 479485.

G. Narayanan (S99M01) received the B.E. degree from Anna University, Madras, India, in 1992, the M.Tech. degree from the Indian Institute of Technology, Kharagpur, in 1994, and the Ph.D. degree from the Indian Institute of Science, Bangalore, in 2000. He is currently an Assistant Professor in the Department of Electrical Engineering, Indian Institute of Science, Bangalore. His research interests include ac drives, pulsewidth modulation, multilevel inverters, and protection of power devices. Dr. Narayanan received the Innovative Student Project Award for his Ph.D. work from the Indian National Academy of Engineering in 2000, and the Young Scientist Award from the Indian National Science Academy in 2003.

Harish K. Krishnamurthy received the M.S. degree from Arizona State University, Tempe. He has been a Design and Analysis Engineer at Delphi Automotive Systems, Bangalore, India, since December 2003. His research interests include topologies and control techniques for switch mode power converters and new pulsewidth modulation techniques for drives.

Di Zhao received the M.S. degree from Tsinghua University, Beijing, China, in 2002 and is currently pursuing the Ph.D. degree in the Electrical Engineering Department, Arizona State University, Tempe. His research interests include topologies and control techniques for switch mode power converters and new pulsewidth modulation techniques for drives.

Rajapandian Ayyanar (S97M00) received the M.S. degree from the Indian Institute of Science, Bangalore, and the Ph.D. degree from the University of Minnesota, Minneapolis. He has been an Assistant Professor at Arizona State University, Tempe, since August 2000. He has many years of industrial experience designing switch mode power supplies. His current research interests include topologies and control techniques for switch mode power converters, especially dc-dc converters, fully modular power system architecture, new pulsewidth modulation techniques for drives, distributed generation, and other power electronic applications in power systems. Dr. Ayyanar received the ONR Young Investigator Award in 2005.