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VHDL Tutorial Open Xilinx Project Navigator.

From File select New Project Name the project and do the adjustments just as in the first lab and as in the below figure.

You continue on by pushing Next button until the front window dissappears just as in the first lab. Then right click as in the below figure and select New Source just the same as the first lab.

Therefore select VHDL module from the New Source window. From now on there is a difference as you will design your circuit by VHDL instead of schematics. Then give a name to your project and click to Next until this window disappears. .

end dene_vhdl. For instance you should write the below code in order to implement D=A. B : in std_logic.B + C’ circuit in VHDL language : entity dene_vhdl is port ( A : in std_logic. Here in the left half of the window. we will give the VHDL codes of the circuits from the first lab. D : out std_logic ). std_logic. But here as a beginning for you. C : in std_logic. The best way to learn about VHDL is to look at a tutorial from the web if you want to design your circuit by VHDL. . you will define your circuit by writing the VHDL code instead of drawing its schematic in schematic editor. Now you can see the VHDL code design environment as below. architecture Behavioral of dene_vhdl is signal AB signal CN begin : : std_logic.

The resultant scene becomes as below: Now after saving this file. D <= AB or CN. CN <= not C. you can make the simulation by right clicking to the VHDL file and selecting Testbench Waveform as in the first lab.AB <= A and B. End Behavioral. And the other parts are all same as in the first lab. Look at below figure: .

gates and relation between them are specified. we add some more examples including the second circuit of first lab. For now and for you to learn some more about VHDL.std_logic_1164. end component. end component. library WORK.2nd design --file named lab1_2. use IEEE. For further information there is more than enough source about VHDL on the web.vhd library IEEE.all. package lab1_2 is component my_xor port ( X : in std_logic. Lab 1. ------------------------------------ . Y : in std_logic. Z : out std_logic ). end lab1_2. Z : out std_logic_vector(3 downto 0) ). component my_xor4 port ( X : in std_logic_vector(3 downto 0). meaning how the inputs. Y : in std_logic_vector(3 downto 0). Here the most important thing is to understand the syntax of VHDL.

ynx <= yn and x. end. yn <= not y. architecture structure of my_xor4 is begin XOR_01 XOR_02 XOR_03 XOR_04 : : : : my_xor my_xor my_xor my_xor port port port port map map map map (X(0). Z(1)). Y(2). (X(2).all.all. Y : in std_logic_vector(3 downto 0).------1bit xor gate----library IEEE. end my_xor4. Z(0)). architecture structure of my_xor is signal xn signal yn signal xny signal ynx begin xn <= not x.std_logic_1164. (X(3). library WORK. ------4bit xor gate-----library IEEE. end.std_logic_1164. entity my_xor4 is port ( X : in std_logic_vector(3 downto 0). entity my_xor is port ( X : in std_logic.all. library WORK. std_logic. -----end of file----- . Y(3). Z <= xny or ynx. use work. use IEEE. Y(0). Z : out std_logic_vector(3 downto 0) ). Z(3)).lab1_2. Y(1). std_logic. std_logic.lab1_2. Z : out std_logic ). Y : in std_logic. end my_xor. use work.all. Z(2)). (X(1). use IEEE. : : : : std_logic. xny <= xn and y.

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