2.

PERFORMANCE

2. PERFORMANCE
2.1 H/W Features
Item Li-Ion, 1050 mAh Standard Battery Extended Battery AVG TCVR Current Standby Current Talk time Stand by time Charging time RX Sensitivity TX output power GPRS compatibility SIM card type Display Size: 39.5 * 67 * 5.4t (mm) Weight: 31g No Extended Battery Min: ?mA(Pwr Level 19), Max: ?mA(Pwr Level 5) < ? mA Min : 2hr40min (2hr30min) Max : 5hr20min(5hr) Up to 200 hours 3 hours GSM, EGSM: -108 dBm, DCS: -107 dBm GSM, EGSM: 33(32) dBm (Level 5) DCS: 30(29) dBm (Level 0) Class 10 Plug-In SIM 3V/5V Main : 65535 Color-TFD(176X220) Sub : Mono(84X40) Status Indicator : 7-color LED Key pad : Status Indicator & Keypad • 0 ~ 9, #, *, Navigation Key, Up/Down Side Key • Side Key, Confirm Key, Record Key • Send Key, END/PWR Key,Function Key ANT EAR Phone Jack PC Synchronization Speech coding Data and Fax Vibrator Speaker Voice Recording C-Mic Receiver Travel Adapter Options Fixed Type Ear-Mike connector Yes EFR/FR Yes Yes Yes Yes Yes Yes Yes Hands-free kit, CLA, USB Cable, DTC Feature Comment

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2. PERFORMANCE

2.2 Technical Specification
Item Description GSM TX: 890 + n RX: 935 + n 1 Frequency Band 0.2 MHz 0.2 MHz (n = 1 ~ 124) 0.2 MHz 0.2 MHz (n = 975 ~ 1024) 0.2 MHz 0.2 MHz (n = 512 ~ 885) Specification

EGSM TX: 890 + (n - 1024) RX: 935 + (n - 1024) DCS TX: 1710 + (n-512) Rx: 1805 + (n-512)

2 3

Phase Error Frequency Error

RMS < 5 degrees Peak < 20 degrees < 0.1 ppm GSM, EGSM Level 5 6 7 8 9 10 11 Power 33 dBm 31 dBm 29 dBm 27 dBm 25 dBm 23 dBm 21 dBm 19 dBm Power 30 dBm 28 dBm 26 dBm 24 dBm 22 dBm 20 dBm 18 dBm 16 dBm Toler. 2dB 3dB 3dB 3dB 3dB 3dB 3dB 3dB Toler. 2dB 3dB 3dB 3dB 3dB 3dB 3dB 3dB Level 8 9 10 11 12 13 14 15 Power 14 dBm 12 dBm 10 dBm 8 dBm 6 dBm 4 dBm 2 dBm 0 dBm Toler. 3dB 4dB 4dB 4dB 4dB 4dB 5dB 5dB Level 13 14 15 16 17 18 19 Power 17 dBm 15 dBm 13 dBm 11 dBm 9 dBm 7 dBm 5 dBm Toler. 3dB 3dB 3dB 5dB 5dB 5dB 5dB

4

Power Level

12 DCS Level 0 1 2 3 4 5 6 7

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2. PERFORMANCE

Item

Description GSM, EGSM

Specification

Offset from Carrier (kHz). 100 200 250 400 600 ~ 1,200 1,200 ~ 1,800 1,800 ~ 3,000 3,000 ~ 6,000 5 Output RF Spectrum (due to modulation) 6,000 DCS Offset from Carrier (kHz). 100 200 250 400 600 ~ 1,200 1,200 ~ 1,800 1,800 ~ 3,000 3,000 ~ 6,000 6,000 GSM, EGSM Offset from Carrier (kHz) 400 600 1,200 6 Output RF Spectrum (due to switching transient) 1,800 GSM Offset from Carrier (kHz) 400 600 1,200 1,800 7 Spurious Emissions Conduction, Emission Status Conduction, Emission Status -9-

Max. dBc +0.5 -30 -33 -60 -60 -60 -63 -65 -71

Max. dBc +0.5 -30 -33 -60 -60 -60 -65 -65 -73

Max. (dBm) -19 -21 -21 -24

Max. (dBm) -22 -24 -24 -27

400 4.000 2.7 25.000 Hz to be Max.000 * Mean that Adopt a straight line in between 300 Hz and 1.000 3.2.10 Level Ratio (dB) 17.5 22.5 > 6 dB .(dB) -12 0 2 * 0 2 2 2 Min.000 3.400 4.439% @-102 dBm DCS BER (Class II) < 2.000 12 RLR 2 3 dB 100 200 300 500 Frequency (Hz) 13 Receiving Response 1.5 ppm . PERFORMANCE Item Description GSM. level in the range.439% @-100 dBm 3 dB 8 3 dB Max.(dB) -12 -6 -6 -6 -9 Min.(dB) -12 0 0 0 4 4 4 0 Max.5 30.(dB) -7 -5 -5 -5 -10 100 200 300 Frequency (Hz) 8 Bit Error Ratio 9 10 RX Level Report Accuracy SLR 11 Sending Response 1.000 3.7 31.7 33.000 3. EGSM Specification BER (Class II) < 2.3 33. 14 15 STMR Stability Margin 13 5 dB dB to ARL (dB) -35 -30 16 Sending Distortion -20 -10 0 7 10 17 18 Side tone Distortion <Change> System frequency (13 MHz) tolerance Three stage distortion < 10% ≤ 2.

2.93 V 3.62 ~ 3.79 ~ 3.03 V (Call) 0.7 V Battery full charge voltage = 4. 2.5 A .93 V~ 21 Charge Voltage 22 Antenna Display 23 Battery Indicator 24 25 Low Voltage Warning Forced shut down Voltage 26 Battery Type 27 Travel Charger 3.2 V. Ringer set as ringer.11 - .62 0. 1. Test distance set as 50 cm Fast Charge : < 650 mA Slow Charge: < 60 mA Antenna Bar Number 5 4 3 2 1 0 Battery Bar Number 0 1 2 3 4 3. 50/60 Hz Output: 5. PERFORMANCE Item 19 20 Description <Change>32.03 V 1 Li-Ion Battery Standard Voltage = 3.71 V 3.5 3.2 V Capacity: 1050 mAh Switching-mode charger Input: 100 ~ 240 V.62 V~ 3.79 V 3.28 0.768KHz tolerance Ringer Volume ≤ 30 ppm Specification At least 80 dB under below conditions: 1.71 ~ 3.03 V (Standby) Power -85 dBm ~ -90 dBm ~ -86 dBm -95 dBm ~ -91 dBm -100 dBm ~ -96 dBm -105 dBm ~ -101 dBm ~ -105 dBm Voltage 3.

3.12 - . The RF front-end circuit is shown Figure 3-1. TECHNICAL BRIEF 3. All active circuits for a complete receiver chain with the exception of RF VCO are contained in the transceiver IC (TRF6150). an external dual RF VCO and a transceiver IC (TRF6150). two RF SAW filters. Figure 3-1. which are on both I and Q signal paths. which contains two LNAs and three direct conversion demodulators for E-GSM. RF front-end circuit . The TRF6150 chip set has direct conversion structure.1 Receiver The receiver part consists of a dual band (GSM & DCS) antenna switch. TECHNICAL BRIEF 3. DCS and PCS. so the received RF signal is directly converted to base band I and Q signal by the transceiver IC (IF frequency is 0 Hz). The demodulated I and Q signals pass two base band AGC amplifiers and a channel filter.

The logic and current is given below. the IC includes a hardware DC offset compensation circuit on both I and Q base band paths.1. The RF received signals (GSM 925MHz ~ 960MHz. To reduce the static offset due to components mismatch and LO self-mixing. . In addition.3.7 V 0V 0V VC2 0V 2. Figure 3-2 shows RX path block diagram. The BB I&Q signals pass via two integrated baseband amplifiers with digitally programmable gain and two fully integrated baseband channel filters to the baseband A/D converters which is contained in baseband chipset. a dual band antenna switch. the received RF signal.13 - . The logic and current VC1 GSM TX DCS TX GSM/DCS RX 2. which are contained in the transceiver IC (TRF6150). is filtered by an appropriate RF SAW filter for better stop band rejection.1.2 Demodulator and Baseband Processing IF stage is not necessary in this system because the receiver is based on direct conversion architecture. An antenna matching circuit is between the antenna and the connector. So the RX LO frequency is the same as input radio frequency. two RF SAWs and two LNAs for EGSM. which has two control signals VC1 and VC2 that are connected to 4-Input NOR Gate (U102) to switch either TX or RX path on. The filtered RF signal is amplified by an LNA integrated in the transceiver IC(TRF6150) and pass to a direct conversion demodulator. TECHNICAL BRIEF 3. The antenna switch (FL103) is used to control the Rx and TX paths.1 RF front end RF front end consists of an antenna.7 V 0V 3. 3. Table 3-1.3 DC offset compensation The transceiver IC(TRF6150) is based on direct-conversion architecture. When the RX path is turned on. This process is the same both GSM and DCS. This implies that a parasitic DC offset may appear at the output of the IQ demodulator.1. The amplified signal at LNA stage passes to a direct conversion demodulator and is mixed down to generate I&Q BB signals. a quadrature demodulator gain mismatch calibration system is used to reduce the signal distortion. The transceiver IC uses a divider by 2 for LO generation in EGSM and a multiplier by 2 in DCS to minimize the DC offset generated by self mixing and the LO radiation. DCS 1805MHz ~ 1880MHz) are input via the antenna or coaxial connector. DCS band. which has passed through the dual band antenna switch. Table 3-1.

Total Gain and Noise Figure of RX path Total Gain 22.5 -2. RX path block diagram Table 3-2.5 Table 3-3.7 RF SAW Filter -2. Gain and Noise Figure of RX path Ant. EGSM DCS .4 I.2 dB 7.9 dB Total Noise Figure 7.9 dB 19.3.Q demodulator (LNA+Mixer) 26 23 3 3.14 - . TECHNICAL BRIEF Figure 3-2.4 dB GSM.6 -0. switch GSM Gain(dB) DCS GSM NF(dB) DCS -0.

and a RF synthesizer. The auxiliary integer-N synthesizer (IF synthesizer). which is an integer-N synthesizer. Two synthesizers consist of an IF synthesizer. The phase frequency detector with charge pump provides programmable output current. prescaler and counter. synthesizers use a number of techniques to improve lock time.15 - . Table 3-4. The main fractional-N synthesizer (RF synthesizer). the external VCO output frequency band is from 902 to 940MHz for DCS Rx and from 1850 to 1920MHz for GSM Rx. The RF VCO works only when the transmitting operation is on. which includes an IF VCO with external tank circuits.6MHz for Tx) is generated by a reference divider from the external applied 13 MHz crystal oscillator. Output frequency of the RF VCO is set by the factional number. The frequency of the signal from the external VCO is divided by 2 for GSM Rx and is doubled by 2 for DCS Rx operation before entering into the direct conversion mixer. 3-wire BUS of Synthesizer in the TRF6150 Pin Number 11 12 13 Description Serial clock input to the synthesizer Serial data input to the synthesizer Input latches the serial data transferred to the synthesizer TSPCLK TSPDATA TSPEN . The IF VCO is also followed by a buffer amplifier. The TRF6150 is a transceiver IC suitable for GSM and DCS GPRS up to class 12 applications. is necessary for transmitting operation only. which uses the PLL block of the main fractional-N synthesizer. which includes a RF VCO with external tank circuits. the OPLL block of the TRF6150 directly modulates the dual band external VCO with I and Q signals. A buffer amplifier follows the RF VCO.2 Synthesizer The TRF6150 includes two synthesizer parts. which is a fractional-N synthesizer.3MHz for Rx (or 2. For receiving operation. The fractional counter in the RF synthesizer just differs from the IF synthesizer. The counter and mode settings of the synthesizer in the TRF6150 are programmed via 3-wire interface. A dual band external VCO. For transmitting operation. A fixed reference frequency of 1. The IF VCO has a frequency band from 832 MHz to 858 MHz. TECHNICAL BRIEF 3. which is to give reverse isolation and prevent any frequency pulling of the VCO when the transceiver is powered UP and DOWN. The purpose of the buffer is to give reverse isolation and prevent any frequency pulling of the VCO when the transceiver is powered UP and DOWN.3. is necessary for transmitting and receiving operation. Output frequency of IF VCO is settled by prescaler and counter. The main fractional-N synthesizer has frequency band from 1294 MHz to 1356 MHz. DCS frequency operation. which could drive the capability and the pulse width. The dual band means that it can support GSM. So. is necessary for both transmitting and receiving operation. making them well suited to GPRS.

16 - .3.6/1. Synthesizer internal Block Diagram . TECHNICAL BRIEF Dual band VCO : 902 ~ 940MHz DCS Rx 1850 ~ 1920MHz GSM Rx RF SYNTHESIZER 13MHz or 26MHz 2.3MHz :2 : 5/ 10 PFD 1294 ~ 1356MHz TANK RX : OPEN TX : CLOSED 7 bits A 4 bits B 4 bits FN 16/17 P/P+ 1 2.6MHz Delay PFD IF SYNTHESIZER 6 bits A 3bits B 8/9 P/P+ 1 TANK 832 ~ 858MHz Figure 3-3.

and the frequency band of the IF VCO is from 832MHz to 858Mhz.17 - . which frequency bands are only for the transmitting operation. is the output frequency of the IF VCO (the auxiliary integer-N synthesizer) and fRFout is the output frequency of the RF VCO (the main fractional-N synthesizer). PLL AUXVCON 24 C142 VC-TCXO-208C C175 R140 C174 D102 HVC369B C164 C167 L105 C156 L108 R141 C178 C179 L109 R142 C176 C177 R139 R143 L110 R145 C184 C185 R137 D103 C183 SMV 1233-074 Figure 3-4. The frequency setting equations of the IF and RF frequencies are as follows.3. The frequency band of the RF VCO is from 1294MHz to 1356 MHz. Synthesizer circuit . TECHNICAL BRIEF The IF and RF output frequencies of the TRF6150 are set by programming the internal divider registers. C116 VT 13 FL101 R107 C117 ENFVF382S18 C118 R109 57 MAINSPUP2 R110 58 R2 MAINSPUP14 MAINCP 5 MAIN PLL 60 59 TXRXCP PFD U105 TRF 6150 TSPCLK TSPDATA TSPEN AFC R131 X101 VCC7 22 AUXVCOP 23 R124 R123 R128 C146 CLK 11 DATA 12 EN 13 AUXCP 14 CRF 16 Serial Interface R111 35MAINVCO AUX.

B.3. The TRF6150 active parts consist of the vector modulator and offset phase-locked loop block (OPLL) including down-converter.P.P.B ON/OFF H.Transmitter Block Diagram . dual schottky diode and dual band VCO. phase detector. The VCO feed the output frequencies into PAM and TRF6150 for Tx local frequency.6V 0V 0V 0V 0V 2./H. L.B./L. coupler.18 - . H. TECHNICAL BRIEF 3.3 Transmitter The Transmitter part contains TRF6150 active parts.3MHZ TX MAINcp LF :5/10 RX 1294~1356 MHz :2 CRF TANK MAINvco VC1 GSM VC2 DCS TX RX TX RX VC1 VC2 2.B./H. H. and APC IC for power control. The PAM outputs from the directional coupler pass to the antenna connector via an integrated dual band antenna switch module.6/1.P./L.B. A dual band directional coupler is used to control the RF output from the PAM. The peak output power of the PAM is controlled by means of a closed feedback loop.6V 0V 0V 16/17 P/P+1 4bits FN 4bits B 7bits A VR4in LF SHS-M090B AUXcp Delay Serial Control Logic & Resisters CLK DATA EN RESETZ 832~858 MHz TANK AUXvcon AUXvcop 8/9 P/P+1 3bits B 6bits A DCS EGSM APC DAC APCEN DETD DETR IFout = (P*A + B)*13MHz PA CONTROLLER RFout_tx = (P*A + B + FN/13)*2. PAM.6MHz Vapc FILT /2 BAT15-05W OMIXrf 416-429MHz IN LBTX R3 LF HBTX TXRXcp MAINspup2 R2 PFD 90˚ IP LDC15D190A0007A HBRX QN QP PF08122B ENFVF382S18 HBswitch LBswitch TXRXswitch Vreg3 L. L.B ON/OFF RX/TX SWITCH 0 1 1 0 1 0 1 0 1 1 0 0 ON=0/OFF=1 RX=1/TX=0 CLARA TRF6150 Figure 3-5. RFout_rx = (P*A + B + FN/13)*1.3MHz MAINspup1 2.P.

1 Tx Modulator The Tx I & Q signals from BB analog chipset are fed to the TRF6150 Tx modulator.14 R107 C118 TSPEN TSPDATA TSPCLK R109 ENFVF382S18 C116 C117 GSM TX DCS TX 0 1 0 LBSW HBSW TXRXSW TXRXSW LBSW HBSW 0 0 1 Figure 3-6.3. The Tx LO signal(1294 – 1356 MHz. VCO. where they are modulated onto either a Tx of 880 MHz(for GSM-Tx) or 1710 MHz(for DCS-Tx) by the quadrature mixer inside the U604.3. It is used as reference signal for the OPLL. The frequency input signal is split into two precise orthogonal carriers. The modulator provides more than 40dBc of carrier and unwanted side-band rejection and produces a GMSK modulated signal. which are multiplied by the BB modulation signal IP/IM and QP/QM.5. The BB software is able to cancel out differential DC offsets in the I/Q BB signals caused by imperfections in the D/A converters. AUX PLL N-integer R505 QM R506 C502 18 19 20 C501 21 QN QP IN IP QP IM IP R129 R501 :2 R502 22 RESETZ C143 RESETCL C123 880 . GSM) 1710 .19 - .1785MHz(TX. 426. Tx IF Modulator and OPLL Circuit .915MHz(TX. The Tx-Modulator implements a quadrature modulator.7 12. DCS) 51 OMIXRF MAIN PLL N-fractional PFD 62 R114 R113 VREG3 U105 TRF6150 FL101 TXVCO 1 6 VCC GSM_OUT DCS_OUT GND VT PWR_SW DCS_SW GSM_SW 9 10 8 13 11 C110 L153 TXRXCP 59 R2 MAINSPUP2 58 57 R111 CLK DATA EN 11 12 13 R124 R123 R128 R110 2. TECHNICAL BRIEF 3.4 MHz) is fed from the internal main and aux.

5 V. the control voltage Vapc should be control to less than 0. Power Amplifier and its Control Part Circuits . To avoid the oscillation at no input power. which depends on the GMSK modulation and the desired channel frequency.3.2 OPLL The down converter contained inside of the TRF6150 (U105) mixes the Tx RF frequency with the RF VCO signal from the ENFVF382S18 (FL101) to generate a ‘feedback’ signal at 414. before the input is cut off. The error current is filtered by a second order low-pass filter to generate an output voltage. To avoid permanent degradation.3. all the GND terminals and the metal cap should be soldered to ground plane of PCB. C107 C134 R138 R117 45 46 DETR DETD U105 TRF6150 FILT 47 APC 8 APCEN 9 FL103 SHS-M090B D101 BAT15-05w VAPC 48 C131 R112 R116 R126 R120 C120 C188 R125 PA_ON PA_LEVEL C135 C136 VBAT R119 R103 C199 N101 1 OUT B1 8 3 B2 GND 2. The efficiency of module is the 55% at 35 dBm for E-GSM and the 50% at 32. the through holes should be layouted as many as possible on PCB under the module.6 4 5 IN 7 2 U101 PAM PF08122B + Vdd1 3 GSM 1 Vdd2 6 C154 C130 C125 C153 C119 L191 C150 C186 R135 R133 R134 L150 C191 Vapc C133 4 GSM C132 5 DCS Bias Circuit Vctl 7 DCS 8 C198 Directional Coupler LDC15D190A0007A GND 9.12 H : GSM. 3. L : DCS Figure 3-7. TECHNICAL BRIEF 3.EGSM and DCS operation. The GMSK ‘reference’ signal from the Tx IF modulator passes via a second limiter to the other input port of the phase detector.20 - . CW operation should not be applied. This module should be operated under the GSM burst pulse. The phase detector generates an error current proportional to the phase difference between the ‘feedback’ signal from the down-converter and the ‘reference’ signal from the Tx IF modulator. EGSM and DCS oper ation.10. We have to improve thermal resistance. This voltage controls the transmit VCO such that the VCO output signal.4MHz for GSM.4MHz for GSM.3.11. The ‘feedback’ signal passes to one port of the phase detector.3 Power Amplifier The PF08122B (U101) is Dual band power amplifier for EGSM (880 to 915 MHz) and DCS (1710 to 1785 MHz). The center frequency of the transmit VCO is offset from the RF VCO frequency by 414. centered on the correct RF channel is frequency modulated with the original GMSK data. And to get good stability.5 dBm for DCS for 3.5 V nominal battery use.

TECHNICAL BRIEF 3. The RF sense voltage is peak detected using an schottky diode of BAT15-05W (D101). TC7SZ04AFE buffers the output to NAUCICA_CS and CALYPSO.4 13 MHz Clock The 13 MHz clock (VC-TCXO-208C) consists of a TCXO (Temperature Compensated Crystal Oscillator). This detected voltage is compared to the DAC voltage in the TRF6150 to control the output power. RF power is controlled by driving the power control pins of power amplifier and sensing. The resultant RF output power via a directional coupler (N101). Pin#3@ U104 C147 R130 R913 4 VCC VCONT 1 R131 AFC C139 C142 3 OUT GND 2 R913 13MHz R121 X101 VC-T CXO-208C 4Y GND 3 C140 CRF@TRF6150 A2 5 VCC NC 1 U103 TC7SZ04AFE Figure 3-8. VCTCXO Circuit . which is digital BB chipset (U503). An internal input signal (PA_LEVEL) from CALYPSO.4 PA Circuit and Control The power amplifier control circuit ensures that the RF signal is regulated to the required limits of operation. The inverter IC.21 - .3. which oscillates at a frequency of 13 MHz. is applied to the APC IC in TRF6150 during the PA_ON mode and a directional coupler near the antenna feeds a portion of the RF output signal back to the APC IC and peak detector converts this signal to a low frequency feedback signal that balances the amplifier when this signal is equal to the RAMP input signal level. The 13MHz clock is used within the Synthesizer block of the TRF6150. and Digital (CALYPSO). 3. BB Analog chip-set (NAUCICA_CS).3.

The Regulator R1 is used to provide DC power to the receiver. Transmitter. The Regulator R3 is used for the external Rx/Tx VCO. VCOs VCTCXO TCXO_EN Enable Signal TCXO_EN R132 1 VEN BYPASS 5 2 GND 2.8V C148 C149 RADIO_TEMP R182 PT101 R181 R183 Figure 3-9. External Regulator Circuit . An external regulator is used to provide DC power to the VCTCXO (X101).5 Power Supplies and Control Signals Three Regulators are integrated in the TRF6150 to provide DC power to the RF blocks (Regulator R1.1 V 0. R2. TECHNICAL BRIEF 3.3. R3). the main synthesizer and VCOs.85 V 0.22 - .85V_OUT VBAT_RF 3 VOUT VIN 4 U104 LP3985IBPX_2. The Regulator R2 is used to provide DC power to the DC offset compensation circuit. Synthesizers. R3 (These are all integrated in the TRF6150) LP3985IBPX_2.8 V 2. R2. Regulator Specification Regulator Regulator R1. the transmitter and the PA control loop of the TRF6150.8V (U104) 2. Table 3-5. the auxiliary synthesizer. switchplexer control buffer.1V Voltage Powers Receiver.

internal 8Kb of Boot ROM memory. This chip combines a DSP sub-chip (LEAD2 CPU) with its program and data memories.3. Top level block diagram of the Calypso G2 (HERCROM400G2) 3.1 General Description CALYPSO is a chip implementing the digital base-band processes of a GSM/GPRS mobile phone.6 Digital Baseband (DBB) Processor 32KHz CRYSTAL External ARM7 Memories Boot ROM MEMIF Memory protect Unit 1Mbit SRAM 1Mbit SRAM 1Mbit SRAM 1Mbit SRAM MCU top-cell RTC IT Alarm Ck32khz Debug Unit ARM7 B R I D G E ULPD GSM time RREA bus TPU W r i t e b u f TSP SIM 8K API cDSP s28c128 PWL UART irda UART modrn DSP subchip Figure 3-10. 4M bit SRAM memory. a MicroController core with emulation facilities (ARM7TDMIE). several compiled single-port or 2-ports RAM and CMOS gates.6. TECHNICAL BRIEF 3. a clock squarer cell. Enhanced Full-Rate and Half-Rate speech coding. PMT. JTAG boundary-SCAN). .23 - . BIST. CALYPSO implements all features for the structural test of the logic (full-SCAN. The chip will fully support the Full-Rate.

Flash or ROM • 4 Mbit Static RAM with write-buffer Application peripherals • ARM General purposes I/O with keyboard interface and two PWM modulation signals • UART 16C750 interface (UART_IRDA) with .Software flow control (UART mode).6. 3 wait state nCS1 : Pseeudo . 32bit access. 16bit access. (25*4 = 100ns) 3 wait state is necessary for the 80ns access because of 25ns . • UART 16C750 interface (UART_MODEM) with . 16bit access. 3 wait state nCS2 : Not Used nCS3 : Not Used nCS6 : Int SRAM. CALYPSO is composed from the following blocks: • ARM7TDMI CPU core • DSP subchip • ARM peripherals: General purpose peripherals • ARM Memory Interface for external RAM.autobaud function • SIM Interface. CTS/RTS) .SRAM.24 - .3. 0 wait state * Calypso internal 39MHz machine machine cycle.2 Block Description CALYPSO architecture is based on two processor cores ARM7 and DSP using the generic RHEA bus standard as interface with their associated application peripherals. TECHNICAL BRIEF 3. • TPU (Time Processing Unit) : Processing for GSM time base • TSP (Time Serial Port) : GSM data interface with RF and ABB Memory Interface : External/Internal Memory Interface nCS0 : FLASH1.hardware flow protocol (DCD.IRDA control capabilities (SIR) .

6.4 RF Interface (TPU. RF Interface Specification TSP (Time Serial Port) Resource TSPDO TSPEN0 TSPEN1 TSPACT00 TSPACT05 Interconnection ABB & RF main Chip ABB RF main Chip RESET_RF PA_ON Description Control Data ABB Control Data Enable Signal RF Control Data Enable Signal RF main Chip Reset Signal Power Amp ON signal TPU (Time Processing Unit) Parallel Port .25 - . External Device Spec connected to memory interface Interface SPEC Device FLASH 1 SRAM Name TH50VPF5683DASB TH50VPF5683DASB Maker Toshiba Toshiba Write Access Time 80ns 70ns Read Access Time 80ns 70ns 3. TECHNICAL BRIEF 3.6.3 External Devices connected to memory interface Table 3-6.3. TSP block) Calypso uses this interface to control Nausica_CS (ABB Processor) and Clara (RF Processor) with GSM Time Base Table 3-7.

6.UART2 : Interface and Communication With Helen UART1 Table 3-9.5 SIM interface SIM interface scheme is shown in (Figure 3-11).3.6 UART Interface The model has two UART Drivers as follow : . TECHNICAL BRIEF 3. SIM_RST ports are used to communicate DBB with ABB and the Charge Pump in ABB enables 3V/5V SIM operation. SIM Interface 3. UART Interface Specification UART MODEM (UART1) Note Transmit Data Receive Data Clear To Send Request To Send Data Terminal Ready Data Carrier Detect UART IRDA (UART2) Transmit Data (UART2) Receive Data (UART2) Resource TX_MODEM RX_MODEM CTS_MODEM RTS_MODEM GPIO 11 GPIO 12 TX_IRDA RX_IRDA Name TXD RXD CTS RTS DTR DCD TX RX . SIM Interface SIM (Interface between DBB and ABB) SIM card async/sync reset SIM card power activation SIM card bidirectional data line SIM card reference clock SIM_RST SIM_PWCTRL SIM_IO SIM_CLK SIM_PWCTRL 20K SIM_IO SIM_CLK SIM_RST SIO3 SCLK3 SRST3 SVDD Naucica SIO5 SCLK5 SRST5 20K VDD IO CLK RST CARD Figure 3-11. SIM_IO.6. Table 3-8.26 - .UART1 : Interface and Communication with Helen UART2 . SIM_CLK.

I/O state. describing application. GPIO Map Table I/O # I/O (0) I/O (1) I/O (2) I/O (3) I/O (4) I/O (5) I/O (6) I/O (7) I/O (8) I/O (9) I/O (10) I/O (11) I/O (12) I/O (13) I/O (14) I/O (15) Application _HEL_SYS_RST CAL_TX_MBOX CAL_UART_SEL MOTOR_EN HEL_TX_MBOX SIM_PWCTL BAT_SENSE DTC_SENSE HS_HF_SW NOT USED MM_AUDIO_C_H CAL_UART_DTR CAL_UART_DCD EAR_SPEAKER_SW NBHE NBLE O I O O O O GPIO GPIO GPIO GPIO MEMORY MEMORY HIGH (Nausica VDR is connected to Helen) LOW LOW HIGH (Audio out is connected to Speaker) LOW (Nausica VDR is connected to Calypso) HIGH HIGH LOW (Audio out path is connected to Earjack) I/O O O O O I O I I O Resource GPIO GPIO GPIO GPIO GPIO SIM GPIO GPIO GPIO Inactive State HIGH (Helen Reset released) HIGH HIGH (UART Modem connected to Keypad connector) LOW LOW LOW LOW LOW (Audio out path is connected to EarJack) Active State LOW (Helen is reset) LOW LOW (UART modem isconnected to Helen UART2) HIGH HIGH HIGH HIGH HIGH (Audio out path is connected to HandsFree) 3. GPRS Class 10 with Digital Basband Chip (Calypso G2) Nausica_CS processes GSM modulation/demodulation and power management operations.3.7 GPIO map In total 16 allowable resources. DCS1800.7. TECHNICAL BRIEF 3.3V/5V SIM card Interface .Baseband in-phase (I). and enable level.4 internal & 5 external ADC channels .Supply voltage regulation .7 Analog Baseband (ABB) Processor 3. quadrature (Q) Signal Processing . GPIO(General Purpose Input/Output) Map.27 - .Battery charging control . This model is using 12 resources except 4 resources dedicated to SIM and Memory.RF interface with DBB (time serial port) . Block Description .Audio Signal Processing & Interface . is shown in below table.6. Table 3-10.1 General Description Nausica CS is Analog Baseband (ABB) Chip supports GSM900.Switch ON/OFF .

Audio Interface Block Diagram .2dB 620mVrms Sensitivity -49. This transmitted signal is reformed to fit in GSM Frame format and delivered to RF Chip.7. SLR = 8 +/.6dB ADC 2.7dBspl/Vrms 1.28 - . TECHNICAL BRIEF 3. The downlink path amplifies the signal from DBB chip and outputs it to Receiver (or Speaker).3dBv/Pa 32. MICBIAS is 2.237Vrms EARAMP 1dB VREF 1. The uplink path amplifies the audio signal from MIC and converts this analog signal to digital signal and then transmit it to DBB Chip.385Vrms Sensitivity 106.3dB 365mVrms AUXI : 4.5V level.2 Audio Signal Processing & Interface Audio signal processing is divided Uplink path and downlink path.6dB 28.3dB Figure 3-12.5dB UL Filter 3.3.5dB PGA : Gain 0dB +12dB -12dB Step 1dB +3dBm0 Full Scale 1.5mVrms MICAMP 25.75V Sidetone : +1dB -23dB Mute 692mVrms AUXAMP -5dB DAC & Smoothing Filter 0dB Digital Modulator 0dB PGA : Gain 0dB +6dB -6dB Step 1dB DL Filter 0dB Volume Control : 0dB -24dB +Mute +3dBm0 Full Scale 0V to AVDD BUZZER Pulse Width Modulation 1MHz RLR = 2 +/.

8.1u C809 R815 R849 1K 1K MICP 0.8V 10K R823 C817 27p 3 MIC801 1 2 C812 27p OBG-15S44-C2 AVDD U805 MAX4684EBC STEREOJACK_DET 2 4 To OMAP1510 1K C B E KEY_ROW1 Q810 DTC144EE 5 V+ B4 G1 B2 R822 15 R828 1K R804 C806 10u 6 1 EAR_SPEAKER_SW 220n C821 A2 R871 470 C819 47p C3 A3 IN2 NO2 A4 220n C810 From Calypso AUXI C2 IN1 NO1 C4 B1 B3 SP13 SP14 SP15 D2 2 GNDD3 D4 D5 D1 C802 47p C813 47p SMF05C Nausica GND C1 COM1 NC1 A1 COM2 NC2 G2 HF_MIC (FromHandsfree Mic) Speaker_ Output_To_MIDI Q803 UMD2N C904 0.1u 1 2 3 4 5 6 J801 R881 R882 R883 R884 0 0 0 0 R803 0 R846 0 1 3 4 5 6 C889 10uF R816 Figure 3-13.3 Audio MICBIAS 0. Audio Section Scheme .3. TECHNICAL BRIEF Audio 3.29 - D801 1K .1u C815 C814 27p C854 10u C857 27p MICN R848 SP17 R906 SP18 1K Nausica_CS EARP C523 EARN C521 C522 AVDD U803 MAX4684EBC B4 B2 HS_HF_SW C2 A2 G1 V+ From Calypso IN1 IN2 NO1 NO2 C4 A4 C1 A1 C808 10p HF_SPK_P HF_SPK_N R813 C804 10p C807 10p B1 GND B3 G2 AUXOP AUXON R814 0 R812 0 C3 A3 (Handsfree Speaker) (Handsfree Speaker) COM1 NC1 COM2 NC2 R824 R905 HEL_IO_MEM_2.

3-14 Uplink Path .6dB Sigma delta Mod.3. EARN AUXOP. 2.48dB SINE Filter UPLinkIIR bandpass filter 3.30 - . When the headset is inserted. U805). Analog Switch Contol Mode Uplink HS_HF_SW Low Low High EAR_SPEAKER_SW Low High Don’t care Mode Headset SpeakerPhone HandsFree The microphone (Zebra Type) is touched to the main PCB. EAR_SPEAKER_SW outputs Low states.52dB Fs3=8KHz PGA +12. AUXON AUXOP. Audio Voice Mode Table Mode Receiver Mode Headset Mode Speaker Phone Mode HandsFree Mode Nausica_CS in/out Port IN MICP...2dB Figure. Table 3-11. Two Geneal Purpose IO Signal (HS_HF_SW. AUXON AUXOP. Side Tone to Voice Downlink MICBIAS Bias generator MICIP Microphone amplifiter 25. TECHNICAL BRIEF Audio Voice Mode -Audio Voice Mode is 5 Mode. AUXON Voice Mode controlled by Two analog switch (dual) Headset. SpeakerPhone and HandsFree Mode is controlled by Two analog switch (dual). MICN AUXI OUT EARP..-12dB To voice serial interface MICIN Fs1=1KHz Fs2=40KHz AUXI Auxihary amplifier 4. MICN AUXI MICP. Table 3-12. EAR_SPEAKER_SW) from calypso control two analog switchs (U803.. STEREOJACKDET outputs High state and HS_HF_SW.6dB 28. The uplink signal is passed to MICIP and MICIN pins of Nausica_CS. The MICBIAS voltage is supplied from Nausica_CS (dedicated mode only) through R815 and R849.

There are two path ( Multimedia speaker and Multimedia Headset) for multimedia audio.3. When the headset is inserted and OMAP1510 detects ‘STEREOJACK_DET’ signal (High Active). TECHNICAL BRIEF Downlink The downlink signal is passed from EARP and EARN pins of Nausica_CS. Headset).U805) AND Melody IC (U807). Calypso makes Nausica_CS switches the downlink path from ‘EARP’ and ‘EARN’ to ‘AUXOP’ and ‘AUXON’. Table 3-13. OMAP1510 informs Calypso of inserting jack And then. Nausica_CS(U501) and external voice path (Speakerphone. AUXOP AUXON EARP Earphone ampifier 1dB DAC and LPF 4bit output sigma_delta modulator Fs1=1KHz EUZZER PWM REceive PGA (-6dB -+6dB step 1dB Fs2=40KHz Auxiliary amplifier -5dB Side Tone from uplink EARN DownLink Bandpass Filter IIR Volume Control From voice serial interface Fs3=8KHz BUZZOP Figure. 3-15 Downlink Path Speaker Phone In speakerphone mode.31 - . Calypso makes ‘SPKER_EN’ to High state and AUXOP signal is passed to speaker (located in upper Folder Case) through two analog switches (U803. Analog Switch Contol Mode MMAUDIO_CAL_HEL State High Low Mode Multimedia Audio Mode Voice Mode . OMAP1510 makes ‘MMAUDIO_CAL_HEL’ to High state and multimedia audio signal from OMAP1510 is passed to speaker (located in upper Folder Case) or headset through MUX switches (U555). MM (Multimedia)_Audio In MM_Audio mode.

8kHz Fs=1. BDL process is opposite procedure of BUL.3. FIR Filter SINC Filter Sigma-Delta Modulator Anti-aliasing Filter BDLIP BDLIM + Fs=270. Namely.32 - .7. - FIR Filter BDLQP BDLQM Figure 3-16.3 Baseband Codec (BBC) Baseband codec is composed of baseband uplink path (BUL) and baseband downlink path (BDL). M Offset Reg.5MHz Sigma-Delta Modulator Anti-aliasing Filter M + Offset Reg. and then transmit it to DSP of DBB chip with 270KHz data rate through BSP. This modulated signal is transmitted through RF section via air. TECHNICAL BRIEF 3. Baseband Codec Block Diagram . it performs GMSK demodulation with input analog I&Q signal from RF section. BUL makes GMSK Gaussian Minimum Shift Keying) modulated signal which has In-phase (I) component and quadrature (Q) component with burst data from DBB. from TSP Timing Control 6-bit DAC Offset Reg.08MHz SINC Filter Fs=6. Burst Buffer1 GMSK Modulator Burst Buffer2 Cos Table 10-bit DAC Low-pass Filter BULIP BULIM BULQP BULQM 16X270kHz Sine Table 10-bit DAC Low-pass Filter from BSP 270kHz Baseband Codec to BSP Uplink Block Downlink Block 6-bit DAC Offset Reg.

1uF R550 C524 X501 Figure 3-17. TECHNICAL BRIEF 3.33 - .8V 2.7. The output of these 5 LDOs are as following table.8V 2. Power Supply Scheme Table 3-14. LDO Output Table Output Voltage 1. (Figure 3-17) shows the power supply related blocks of DBB/ABB and their interfaces.4 Voltage Regulation (VREG) There are 5 LDO (Low Drop Output) regulators in ABB chip.8V Usage Digital Core of DBB Digital Core of ABB Memory Interface of DBB Digital I/Os of DBB & ABB Analog Block VR1 VR1B VR2 VR2B VR3 .3.8V 2.0V 2. U505 D510 0.

Idle : 3.2V Full charge indication current (icon stop current) : 100mA Low battery alarm a. TECHNICAL BRIEF 3.6 Charging Charging block in ABB processes charging operation by using VBAT.2 ~ 3.3. Battery Block Indication Charging method : CC-CV Charger detect voltage : 4. This block operates charging process and other related process by reading battery voltage and other analog values. Battery Block Indication and SPEC is as follow.62 ~ 3.71V 3.62V b.0V Charging time : 3h Icon stop current : 100mA Charging current : 540mA CV voltage : 4.5 ADC Channels ABB ADC block is composed of 4 internal ADC (Analog to Digital Converter) channels and 5 external ADC channel. ICHG value through ADC channel.93V 3.7. ADC Channel Spec ADC 9 channels Resource VCHG VBAT ICHG VBACKUP ADCIN1 ADCIN2 ADCIN3 ADCIN4/TSCXP ADCIN5/TSCYP Name VCHG VBAT ICHG VBACKUP RADIO_TEMP BATT_Thermister Not Used Not Used Not Used Backup Battery Temperature Sensing Battery Temperature Detect Charging Management 3. 4.93 ~ 3. Dedicated : 3.62V 3.34 - .79V 3.5V Figure 3-18. Table 3-15.7.50V Low battery alarm interval : Idle : 3 min Dedicated:1 min .71 ~ 3.79 ~ 3.

7.Power-ON : mobile is powered by main battery or backup battery.Power-OFF : mobile isn’t any battery. . TECHNICAL BRIEF Switch-off voltage : 3. .7 Switch ON/OFF Power State : Defined 4 cases as follow . .PWR-ON :pushed after a debouncing time of 30ms. . 3.CHARGER_IC :When a charger voltage is above VBAT+0.35 - . 47 °C~ : not charging operation. when a falling edgeis detected on RPWON pin.Switch-OFF : mobile is powered to maintain only the permanent function (ULPD). To enter into Switch-ON state. .8 Memories • 64Mbit/32Mbit Flash/SRAM MCP 64Mbit Flash + 32Mbit SRAM • 16 bit parallel data bus • ADD01 ~ ADD22 . .4V on VCHG.ON_REMOTE : After debouncing. one of following 4 condition is satisfied.3.IT_WAKE_UP : When a rising edge is detected on RTC_ALARM pin.Switch-ON : mobile powered and waken up from switch-off state. .7.28V Charging temperature adc range ~ -20 °C : not charging operation. -20 °C ~ 47 °C : charging. 3.

a memory interface traffic controller. The MPU is the master of the platform. Top Level Block diagram of Helen OMAP1510 3.8 Multimedia Processor (HELEN) Figure 3-19. The OMAP1510 performs all personal communication system tasks such as PDA. The OMAP1510 processor provides application developers with an open.36 - . The OMAP1510 device includes the MPU subsystem. TECHNICAL BRIEF 3. the MPU and DSP share access to the internal SRAM and external memory interface. dedicated multimedia application peripherals. . and it has access to the entire 16M bytes of memory space and to the 128K bytes of I/O space of the DSP subsystem.1 gigacell as its core building block. general-purpose peripherals. easy-to-use programming environment by supporting popular os and programming languages.8. PIM tasks.1 General Description The OMAP1510 processor features 1st generation TI OMAP architecture with the OMAP3. the DSP subsystem. Additionally. and multiple interfaces.3.

debug. pixel interpolation. such as flash/SRAM/ROM/page-mode ROM/SB flash/DPRAM). and applicationspecific functions: For the MPU: Three 32-bit timers A 16-bit watchdog timer An interrupt handler An LCD controller Configuration registers McBSP2 (multichannel buffered serial port) Inter-integrated circuit (I2C) interface MicroWire interface Keyboard interface Universal serial bus (USB) function and host interface Camera interface Five MPUIO general-purpose input/output signals in default multiplexing mode. with 64M bytes of memory space JTAG port for test.2 Block Description The OMAP1510 device has the following features: _Ability to support reduced instruction set computer (RISC) and DSP operating systems TI925T MPU subsystem with: Instruction cache (16K bytes) and data cache (8K bytes) Memory management unit (MMU) A 17-word write buffer (WB) DSP subsystem (C55x••DSP core and subsystems) with: Internal 32K-word dual-access RAM (DARAM).16-. 128-bit line size. DSP. and peripherals with byte alignment and packing capability Ability to perform simultaneous transfers (single or multiple burst). general-purpose housekeeping. the MPU. with 128M bytes of memory space A 16-bit bus interface to external memory interface fast (EMIFF). five more . allowing glueless hookup to: A 16-bit bus interface to external memory interface slow (EMIFS). 16Kword ROM Software-configurable instruction cache (12K words. 48K-word single access RAM (SARAM). TECHNICAL BRIEF 3. 2-way set-associative + RAM set) Hardware accelerators for video processing. or 32-bit data between the external memory. and emulation Clock management: One digital phase-locked loop (DPLL) and three clock management units for MPU.8. and motion estimation Six-channel DMA controller for high-speed data movement without DSP intervention DSP MMU for address translation and access permission checks System DMA controller with: Six ports and nine independently programmable generic channels An additional dedicated DMA channel tied to the liquid crystal display (LCD) controller Ability to transfer 8-.3. and traffic controller clock generation and management System power management for idle mode and power-down functions Peripherals available for the OS. such as memory SDRAM. if no resources conflict Low-power design (no clocking when idle) Two external memory interfaces.37 - .

or memory stick interface HDQ and 1-Wire serial interface Two light emitting diode (LED) pulse generator modules Frame adjustment counter For the DSP: Three 32-bit timers A 16-bit watchdog timer An interrupt handler McBSP1: Multichannel buffered serial port McBSP3: Multichannel buffered serial port MCSI1: Multichannel serial voice interface MCSI2: Multichannel serial voice interface Shared peripherals: UART1: UART modem with autobaud (16C750 compatible) UART2: UART modem with autobaud (16C750 compatible) UART3: UART modem with IrDA (16C750 compatible) Fourteen general-purpose input/output (GPIO) Mailbox 3.38 - . serial data (SD) card interface. Helen External Memory Interface SPEC Device Flash1 Flash2 SRAM MIDI Name TH50VPF5683DASB TC58FVB641XB-70 TH50VPF5683DASB YMU762 Maker TOSHIBA TOSHIBA TOSHIBA YAMAHA Write Access Time 70ns 70ns ` 70ns Read Access Time 70ns 70ns 70ns . TECHNICAL BRIEF available through alternative pin multiplexing modes 32-kHz timer Pulse-width tone (PWT) module Pulse-width light (PWL) module Real-time clock (RTC) module Multimedia card (MMC).8.3.3 External Device Description Table 3-16.

0V LDO On) HIGH O O O O O GPIO GPIO GPIO GPIO GPIO HIGH (UART3 is connected to Receptacle) LOW (Data) LOW LOW LOW LOW (UART3 is connected to IrDA) HIGH (Command) HIGH HIGH HIGH Table 3-18.0V LDO OFF) LOW HIGH (Open) HIGH HIGH ( 3.3.8. Each port can be configured as input or output.39 - . TECHNICAL BRIEF 3. ARMIO Map Table I/O # I/O (0) I/O (1) I/O (2) I/O (3) I/O (4) I/O (5) I/O (6) I/O (7) Application HEL_TX_MBOX MAIN_LCD_RES SUB_LCD_RES YMU762_RST MAIN_LCD_LED_ON _HF_DET STEREOJACK_DET CAL_TX_MBOX I/O O O O O O I I I Resource State GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Inactive State LOW HIGH HIGH HIGH LOW LOW LOW LOW Active State HIGH LOW LOW LOW HIGH HIGH HIGH HIGH . GPIO Map Table I/O # I/O (0) I/O (1) I/O (2) I/O (3) I/O (4) I/O (5) I/O (6) I/O (7) I/O (8) I/O (9) I/O Resource State USB_DETECT I USB CAMERA_POS_DET I GPIO YMU762_IRQ I GPIO KEYPAD_LED_ON O GPIO MAIN_LCD_CD_SEL O GPIO Not Implemented On Chip HEL_FOLDER_DET I GPIO HEL_IND_LED_O O GPIO Application HSPEAKER_EN O O GPIO GPIO Inactive State LOW LOW (Front) HIGH LOW LOW (Data) Active State HIGH HIGH (Rear) LOW HIGH HIGH (Command) HEL_IND_LED_G I/O (10) Not Implemented On Chip I/O (11) PC_IRDA_SEL I/O (12) SUB_LCD_CD_SEL I/O (13) HF_CALL_OFF_ON I/O (14) EL_ONOFF I/O (15) HEL_IND_LED_B LOW (Close) LOW LOW ( 3.4 GPIO Map Helen has 8 ARMIO and 14 GPIO ports. Table 3-17.

5V 1.5V C900 10u ONNOFF_BUF R857 R855 SPEAKER_EN C856 10u 270K 180K U809 1 5 IN OUT 2 GND 3 4 EN ADJ MIC5219BM5 C858 470p AVDD C855 10u SPK_VDD U810 VIN GND USB_PWR 100K R869 1 2 LP3985IM5X-3.8V HEL_IO_MEM_2.2K 4 RUN 20K HEL_CORE_1. 3-20 shows the power supply related blocks for Helen and Melody IC.5V 1. Helen Power sources Table 3-19. Helen & MIDI LDO Output Level Table Output Voltage HEL_CORE_1.0V 3.8V ACDD or SPK_VDD USB_VDD 1.8V C866 10u VRIO U813 1A 5 2 BVCC 3 GNDY 4 TC7SZ08AFE U804 1 5 2 IN OUT GND 3 EN ADJ 4 C829 10u MIC5219BM5 C830 470p R807 R808 ONNOFF_TO_BUF 200K 150K HEL_IO_MEM_2.8.8V 2.3V Usage Digital Core of Helen DPLL of Helen Main LCD Module IO pin of Helen and Melody IC Audio analog switch.7uH 3 4 P3 P4 P1 P2 2 L801 R842 R810 300K 2. TECHNICAL BRIEF 3.5V LCD_1.3.8V C831 10u U890 1 5 2 VDDVOUT GND 3 CE NC 4 R1111N151B-TR HEL_PLL_1.5V R844 C R821 10K C888 0F R878 B 12K E C853 330p Q802 DTC144EE VBAT NCP500SN18T1 5 1 VIN VOUT 2 GND 3 EN NC 4 U812 100K C852 47uF LCD_1.3 5 VOUT USB_VDD C861 10u 3 VEN BYPASS 4 C863 0.40 - .01u Figure 3-20. Fig. Table 3-19 shows the output level of each power source.5 Helen Power There are 5 LDO (Low Drop Output) regulators and 1 DC-DC converter for Helen and Melody IC. Speaker amp of Melody IC USB module of Helen Enable Control ON_nOFF (from Nausica) ON_nOFF ON_nOFF ON_nOFF SPEAKER_EN (Helen GPIO) USB_PWR (receptacle) . VBAT D6 8 D5 D4 7 D3 6 5 S D2 3 C851 D1 2 G 1 33u R811 4 NTHS5441T1 Q801 0 5 R843 R875 1M U808LTC1701BES5 1 VIN SW 2 GND VFB 3 D802 1 MBRM120LT3 4.8V 3.5V HEL_PLL_1.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SYMBOL NC VDD_L VDD_H GND SCL XRST HSYNC SDA D6 D7 D4 D5 VSYNC D1 D2 DCK D0 D3 GND CKIN NC FUNCTION 2.3.8. vertical sync signal. Devices in LCD Module Device Main LCD Sub LCD Main LCD Backlight Sub LCD Backlight Type 176 x RGB 220 65K Color TFD LCD 84 x 40 mono FTN LCD White LED Deep Blue EL . The camera port supply 8MHz master clock to camera module and receive 4MHz pixel clock. Table 3-20.8. The camera module is controlled by I2C port in Helen.6 Camera & Camera FPC Interface The Camera module is connected to main board with 21-pin FPC connector (21FXL-RSM1-TB).8V 2. Table 3-21. Interface between Camera module and main board (in Camera Module) PIN. horizontal sync signal and 8bits YUV data from camera module.7 Display & LCD FPC Interface LCD module include devices in table 3-21. TECHNICAL BRIEF 3.8V Ground Serial Clock Signal for I2C Reset Signal Horizontal Sync Signal Serial Data for I2C YUV Data YUV Data YUV Data YUV Data Vertical Sync Signal YUV Data YUV Data Pixel Clock Signal YUV Data YUV Data Ground Master Clock Signal I/O P P P O I O O O O O O O O O O P I REMARKS 3. Its interface is dedicated camera interface port in Helen.41 - .

Vibrator PIN. Interface between LCD module and Speaker. Receiver. 1 2 3 4 1 2 SYMBOL ES+ E+ SMB MG FUNCTION SPK TERMINAL Ear Piece Minus Loud Speaker Plus Ear Piece Plus Loud Speaker Minus MOTER PAD TERNINAL MOTOR Power MOTOR Ground I/O O O O O O O REMARKS . Receiver.42 - . Vibrator is connected by soldering the leads to 6 pads in LCD module.3. The main LCD is controlled by McBSP2 Port(in SPI Mode) in Helen and the sub LCD is controlled by uWire Port in Helen. TECHNICAL BRIEF LCD module is connected to key board with 30-pin FPC connector (AXK830145J) and Speaker. Table 3-22.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SYMBOL Motor GND Motor Batt NC NC EAR PIECE+ EAR PIECELOUD SPK+ LOUD SPKNC NC LEDLED+ EN On/Off VDDL VDD(VDDI) VDD(EL) GND(EL) GND(LCD) SDA_S SCK_S RS(A0)_S XCS_S XRES_S VDDL SD0_M XWR_M A0_M XCS_M XRES_M GND(LCD) FUNCTION Ground MOTOR Power Not Connect Not Connect Ear Piece Plus Ear Piece Minus Loud Speaker Plus Loud Speaker Minus Not Connect Not Connect LED cathode LED anode EL ON/OFF signal Power supply for internal logic (1.43 - .8V) Ground for EL & EL Driver Ground for system Sub Display data Sub Serial Data clock Sub Serial Data command select signal Sub Chip select signal Sub Reset signal Power supply for internal logic (1.8V) Power supply for EL Driver (2.8V) Main Serial data Main Write signal Main Data command select signal Main Chip select signal I Main Reset signal I Ground for system I/O P P I I I I P P I P P P P P I I I P I I I I I P REMARKS Serial data transfer line . Interface between LCD module and main board (in LCD Module) PIN.8V) Power supply for system and I/O logic (2. TECHNICAL BRIEF Table 3-23.3.

44 - 220p . TECHNICAL BRIEF 3.7 C651 10u C612 R647 100K 1u 1 2 3 4 5 U602 SC600BIMSTR VOUT CF1+ VIN FID0 FID1 CF2+ CF1GND CF2EN 10 9 8 7 6 C676 R658 470 C606 1u C605 1u PWL_MAIN_LCD_BL Figure 3-21. LED3 : NACW215T (Nichia) . Main LCD Backlight Circuit * R1.8. Charge Pump Circuit for Main LCD Backlight MAIN_LCD_LED+ GND Figure 3-22. R3 : 47ohm * LED1. R2. VBAT_2 R628 R629 100K MAIN_LCD_LED+ R627 4.3.8 Main LCD Backlight Illumination There are 6 white LEDs in main LCD backlight circuit which are driven by ‘PWL_MAIN_LCD_BL’ line from Calypso. LED2. PWL is used for backlight brightness control.

Multi-color LED is controlled by GPIO_7 (HEL_IND_LED_O). green LED and blue LED. GPIO_14(EL_ONOFF) in Helen does ON or OFF the ELD-3410 inverter.1u R621 2. In other case (ON_OFF=High).45 - 47K 2 LNJ717W80RA1 . GPIO_7 (HEL_IND_LED_O). Indicator Illumination Circuit In case of power off mode (ON_OFF=Low).10 Indicator Illumination Indicator LED illumination circuit can make 7 colors using multi-color LED. GPIO_9 (HEL_IND_LED_G) and GPIO_15 (HEL_IND_LED_B) in Helen do ON or OFF its own LEDs. Multi-color LED consists of orange LED. 3. if TA is inserted. which include the inductor in itself.8. TECHNICAL BRIEF 3. GPIO_9 (HEL_IND_LED_G) and GPIO_15 (HEL_IND_LED_B) in Helen .7K HEL_IND_LED_B R625 20K Figure 3-23. VBAT R681 R682 3 10 3 10 1 1 3 LD603 LD602 LNJ717W80RA1 LNJ717W80RA1 LD601 1 2 2 4 4 R626 R622 R601 150 33 HEL_IND_LED_G VBAT R623 20K 6 5 4 6 5 4 R620 ONNOFF Q602 NC7SB3157P6X 100 EMX1 Q603 1 2 3 EMX1 Q604 1 56 2 4 3 HEL_IND_LED_O CHARGER R619 10K 1 B1 S 2 GND VCC 3 B0 A 6 5 4 R624 10K R661 C666 0.3.8. NC7SB3157P6X multiplexer is switched to charger and orange LED is turned-on.9 Sub LCD Backlight Illumination A family of Deep blue EL is used for Sub LCD backlight and Citizen’s ELD-3410 is used for its driver.

Keypad Backlight Circuit . which are driven by ‘GPIO_3’ line from Helen.46 - 39 . GPIO_3 >> R614 12 1 2 3 R612 12 6 5 4 Q601 EMX18 KEY_LEDFigure 3-24.1u R2 R4 R1 R3 39 39 39 KEY_LED- Figure 3-25.11 Keypad Illumination There are 16 Blue LEDs in key board backlight circuit.7K LD12 LD10 LD13 LD15 LD11 LD16 LD7 LD3 LD1 LD2 LD4 LD5 LD6 LD8 LD9 C2 0.8.3. Keypad Backlight Control Circuit on Main Board VBAT LD14 R611 2. TECHNICAL BRIEF 3.

TECHNICAL BRIEF 3. Key matrix mapping Table KEY_ROW[4] KEY_ROW[3] KEY_ROW[2] KEY_ROW[1] KEY_ROW[0] KEY_COL[0] KEY_COL[1] KEY_COL[2] KEY_COL[3] KEY_COL[4] KEY_COL[5] KEY_ROW4 Soft Function 3 Function 2 # 0 * KEY_ROW3 Option Navigate SEND 9 8 7 KEY_ROW2 Navigate OK Navigate 3 5 4 KEY_ROW1 Clear Back Function 1 6 2 1 KEY_ROW0 Navigate• V2.8 10K 10K 10K KB18 KB2 KB25 KB8 10K R8 R7 2K R9 R6 R5 KB16 KEY_COL0 KB23 KB24 KB20 KB1 KB13 _END_ONOFF KEY_COL1 KB21 KB6 KB9 KB14 KEY_COL2 KB4 KB5 KB19 KB7 KEY_COL3 KB17 KB10 KB22 KB3 KEY_COL4 KB26 KB15 KB11 KB12 KEY_COL5 Figure 3-23.3.12 Key pad There are 26 key buttons and 3 side keys in Fig.8. 3-26 shows the Keypad Circuit .47 - . Indicator Illumination Circuit . Table 3-24.

8.13 Folder ON/OFF Detection GPIO_6(HEL_FOLDER_DET) detects the folder ON or OFF. Folder ON/OFF Detection Circuit 3. HEL_IO_MEM_2. V2. TECHNICAL BRIEF 3.8.3.48 - .8 R11 51K HEL_FOLDER_DET C1 10p C3 0.14 Camera Position Detection GPIO_1 detects the camera position (front or back).1u R680 10p C601 Figure 3-28. Camera Position Detection Circuit .8V R602 51K R646 10K U1 A3212ELH 1 VDD 3 GND OUT 2 >>GPIO 1 U601 A3212ELH 1 VDD 3 GND OUT 2 SP42 C602 0.1u Figure 3-27.

15 USB Interface The universal serial bus (USB) function module supports the implementation of a full-speed device fully compliant with the USB 1. the type (bulk/interrupt or ISO). see text) Low ESR cap.1 standard. The module supports one control endpoint (EP0). and up to 15 OUT endpoints. or SN75240 Figure 3-29.R2 R3 R4. It provides an interface between the MPU core (TI925T) and the USB wire and handles USB transactions with minimal TI925T intervention. The specific items of a configuration are for each endpoint. SN65240. USB W2FC Function Connection .VBUS UBS differential (+) line UBS differential (-) line UBS clock (6 MHz) UBS pullup enable UBS VBUS detect input R1. OUT).CLKO UBS. Table 3-25.minimum 120 uF Transient suppessor.8.PUEN UBS.5K Ohm+/-5% Weak pulldown (optional.R5 C1 U1 Value depends on transceiver 1.49 - . such as SN65220. The module also supports three DMA channels for IN endpoints and three DMA channels for OUT endpoints for either bulk/interrupt or ISO transactions. up to 15 IN endpoints. The exact endpoint configuration is software programmable. TECHNICAL BRIEF 3.DM UBS. the direction (IN. the size in bytes.3.DP UBS. USB Signal Interface for Helen UBS Funtion UBS. and the associated number.

47u 8 PC_IRDA_SEL HEL_UART_IRDA_TX HEL_UART_IRDA_RX HEL_UART_PC_TX HEL_UART_PC_RX 6 7 signals To Receptacle Figure 3-31.8V Q809 UMC4N USB_DETECT 100K R802 R896 4 3 1K USB_VDD 5 Figure 3-30. Helen UART3 IrDA Path .17 IrDA This model supports SIR IrDA.8V 1 2 IrDA Transceiver 1 U802SN74CBTLV3257DGVR 16 1 15 4 7 9 12 8 VCC S _OE 1A 2A 3A 4A GND 1B2 2B2 3B2 4B2 3 6 10 13 2 1B1 2B1 3B1 4B1 2 5 11 14 3 4 5 LEDA LEDK TXD SHIELD RXD SD VCC GND CIM-80S7B-T U801 C801 0. Uses both two mode. There is a Quad2:1 Mux to select IrDA. If external connection by UART is needed.16 USB detect USB is detected by Helen GPIO HEL_IO_MEM_2. the quad 2:1 mux set the UART path to receptacle. HEL_IO_MEM_2.50 - . Helen’s UART3 module support IrDA or UART.3.8. During the normal operation. TECHNICAL BRIEF 3. USB Detect Circuit 3.8. UART path is connected to IrDA.

18 Vibrator Activating vibrator. HEL_IO_MEM_2. MOTOR_BATT signal connects with vibrator device and vibrator device is activated.8. Calyso makes ‘MOTOR_EN’ to High state (2.19 Hands Free Detect Hands Free is detected by Helen GPIO.8V) and MOTOR_BATT outputs High. VBAT R829 R827 47K UMT2907A Q805 R826 0 10 MOTOR_BATT C MOTOR_EN R825 2K B Q804 DTC144EE E C832 0.8V R868 4 3 HF_Detect_Signal_From_Receptacle R801 100K 5 Figure 3-33. Vibrator Circuit 3.51 - UMC4N Q808 1 2 10K . Handsfree Detect Circuit .3.8.1u Figure 3-32. TECHNICAL BRIEF 3. And then.

2K R835 8. Table Supply Voltage HEL_IO_MEM_2.2K C845 0. Handsfree Detect Circuit Table 3-25.52 - .8V U807 C848 68n 11 10 R836 8.022u 12 13 C847 390p 14 2 19 R841 C850 47p 0 R840 SPK_VDD 0 18 SPOUT2 EQ3 LED MTR HPOUT_R HPOUT_L EQ1 EQ2 YMU762 1 CLK1 4 _RST 30 A0 31 _RD 29 _CS 5 NC _WR _IRQ D0 D1 D2 D3 D4 D5 D6 D7 PLLC VREF Speaker_Output_From_Analog_Switch HEL_CLK_12M_OUT _YMU762_RST HEL_FADD(1) HEL_NFOE HEL_NFCS_3 R817 R837 82K 28 3 27 26 25 24 23 22 21 20 HEL_DATA[0] HEL_DATA(1) HEL_DATA(2) HEL_DATA(3) HEL_DATA(4) HEL_DATA(5) HEL_DATA(6) HEL_DATA(7) LOUD_SPKM 17 SPOUT1 HEL_DATA(0:15) HEL_NFWE _YMU762_IRQ HEL_DATA(0:15) LOUD_SPKP R834 6 3.1u 0 15 C846 10u C849 0.8.8V 3. Supply Volt.3.20 MELODY IC HEL_IO_MEM_2.0V Usage Digital VDD of Melody IC Analog VDD of Melody IC Enable Control ON_nOFF (from Nausica) ON_nOFF . TECHNICAL BRIEF 3.1u 16 SPVDD IOVDD VDD SPVSS VSS Figure 3-34.3K C843 C844 0.1u 1000p 9 R818 32 7 8 C828 0.8V SPK_VDD 2.

organization and naming of files and directories.2 CALMON Environment 4. .60 full) Driver Install • HP8960 Vxi driver • CALMON Exe Files • OS : Win98. Power Cable) 4. From now on. Win2000 & WinXP • Serial Port Configuration (Baud rate : 115200 / Char length : 8bit / Parity : No / Bits stop : 1bit ) *Flash File System – Make a Flash the hierachy. the Calibration Software will be called CALMON in this document. Calibration S/W User Guide Ver 1. RF Cable.0 4.2 S/W Environment • National Instrument GPIB & Visa (2. FFS is used for storing many kinds of data and configuration parameters that should be non-volatile across power-cycles. 4.and so on) adjusted and programmed during Calibration and production test. AGC Calibration and *Flash File System access (Read/Write) to apply Calibration results to the Phone.1 Introduction This document describes the construction and the use of the Software used for the Calibration of GSM/GPRS Multimedia Mobile. This includes RF calibration parameters(. This Calibration Software includes APC Calibration.4.1 H/W Environment • PC with RS-232 Interface & GPIB card installed • GSM/GPRS Mobile Set • HP8960 Instrument • Power Supply • Etc (GPIB cable.0 4. CALIBRATION S/W USER GUIDE VER 1.2. This Calibration Software is called ‘CALMON’. Serial Cable.53 - . The Calibration menu and their results are displayed by a PC terminal connected to the GSM/GPRS Multimedia Mobile.2.

3 Configuration Diagram of Calibration Environment PS2521G HP8960 GPIB Cable Power Cable RF Cable NoteBook Serial Cable Figure 4-1. connect HP8960 to the Phone’s antenna with RF cable.4. . For making the CALMON can control each instrument and Phone. vice versa CALMON control the Phone’s operation so the instrument receive the power signal through the RF cable and measure the signal to do the Tx Calibration. Calibration Configuration When you calibrate the Mobile.54 - . Make a connection of the Phone and the PC. connect Instrument and the PC (in fig. Thus. CALMON can control the Instrument (HP8960) to run Rx Calibration with the Phone that received the RF signal from the instrument controlled by CALMON. Using GPIB cable. When Tx Calibration (APC) is run. use Power cable from Power supply.2. When Rx Calibration (AGC) is run.g. it’s notebook PC) and using Serial Cable. To supply the Phone with electricity.e. Calibration S/W User Guide Ver 1.0 4. also.4-1. make a configuration of Calibration environment like Figure1.

APC DAC calibration for each defined Channel. the Results are displayed in the CALMON Result Window. when any of Calibration is done. but “Pre-defined” level according to each boards. (using Standard Power Level) # Standard Channel for EGSM (channel 40) / Standard Channel for DCS (channel 700) *Actually this is not “Automatic”.AGC Calibration • Item from Specific requirement Flash File System Access Battery Calibration 4. Mask. it is explained calibration items in the CALMON.4.3 Calibration Explanation 4. At first.1 Overview In this section.) . Flash File System(From now on ‘FFS’) should be formatted before anything else and should have hierarchy of directories in advance to be stored for calibrated data after the Calibration is done.. We need to find out what voltage level can make the wanted level output in antenna.(We need to know the DAC value for each power level in the point of layer1 software.for using Flash File System. there are two steps for APC calibration.APC DAC Calibration for each Power Index (using a Standard Channel) . And in some case.3.Ramp coefficients calibration for each Power Index. Calibration Items of CALMON • General Items .3.0 4. the Explanation includes technical information such as basic Formula of Calibration and settings for Key parameters in each Calibration Procedure. Thus. .2 APC Calibration (*Auto Power Control ) APC Calibration is for adjusting voltage level that can make the wanted level output in antenna and adjusting Ramping shape at assigned level to be able to remain in Spec.APC Calibration .55 - . (using a Standard Channel) . Also. as user’s choice the Result of Calibration will be stored in Flash File System for non-volatile across power cycle. So. Calibration S/W User Guide Ver 1.

3.1.1. Setup the mobile to transmit on the channel specified in Table 4. 6. If output power is lower than specified in Table 4.56 - . then increase the APC level.4. Setup up the power level that needs to be calibrated. If output power is higher than specified in Table 4.1. 2.0 4. Proceed with the steps above until all power levels both bands have been calibrated. 4. Calibration S/W User Guide Ver 1. Calibrate the power level according to Table 4.1. Table 4-1 EGSM900 and GSM1800 Power level settings Power level 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 EGSM900 @ channel 40 [dBm] 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 GSM1800 @ channel 700 [dBm] 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 - . then decrease the APC level.3. 5.1 APC DAC Calibration for each power index The TX power levels needs to be calibrated in order to achieve the required accuracy To calibrate the TX power levels the following steps have to be performed for both bands : 1.2.

. 3. 742. for DCS Index is 5. 696.0 4. 8. Calculate PMAV = (PM1 +PM2 )/2. DCS) 4.2. Default Channel Calibration Value is set to 128.3. 6.3 APC DAC Calibration for Each Channel When APC DAC Calibration is done for each Power Index. Set Test frequency as specified in 0 minus 67Khz. *INI_AFC value can be obtained by performing the VCTCXO Calibration procedure.2. APC DAC for predefined channels should be calibrated for both GSM and DCS to make each Channel have Wanted Transmit Power. 983. Write *INI_AFC value to MS 5.2. So.2 Specified Arfcn Limits and Test Arfcns for Apc Channel calibration Arfcn Limit for Apc Channel Calibration 20. Measure PM2. 604. . 71. Set the AGC in the receiver to the gain specified in Table 4. 80. Setup the mobile to receive on the ARFCN specified in Table 4.Mask at the same time. After Channel Calibration. If output power is higher than specified value then decrease Channel Calibration Value at lower than 128. 992. make Power level received by Mobile equal to calculated power level by itself.3.3. In this case. 124. 1023 558. 40. 673. So. The Important thing of Ramp Up/Down Calibration is maintenance of Sum of indexes’ coefficients. Standard Power Level Indexs for each band are for GSM Index is 10. Each Ramp Template has 31 Coefficients (0 to 30).4. do the calibration for each Channel in Table 4. 9. 112. 100.3. 51. 4.57 - .3. 885 Test Arfcn For Apc Channel Calibration 10. 834. 30. 719. Adjusting G_magic. 4. Measure PM1. The sum has to be 128 exactly. 90. in-band signal and interference power for the A/D converters.3. if that hasn’t already been done.3 AGC Calibration The AGC block generates automatic gain control from the digital baseband signal and then feeds it to the analog IF variable gain amplifier (VGA) to maintain a constant. 7. 2. Special Consideration needs to maintain specific sum value ‘128’ and to make Ramping shape in Spec.1 G_magic Calibration To calibrate GMagic the following steps have to be performed for both bands: 1. There are 16 Indexes for both Up and Down Ramp Template. Up and Down separately.2 Ramp Up/Down Calibration for each Power Index Ramp Up/Down Calibration is to adjust Ramp Template Up/Down Coefficients for Ramping shape at assigned level to remain in Spec. 650. Calibration S/W User Guide Ver 1.G_magic Calibration for Both Band (GSM.3. 581. 1007 535. Set Test frequency as specified in 0 plus 67Khz. 811. 627. 765. If output power is lower than specified value then increase Channel Calibration Value at higher than 128 Table 4.3. At first get the APC DAC Calibrated Value at Standard Power Level Index and based on this calibrated value from Standard Power Level. 788. 62. Set the generator level to TL specified in Table 4. 857 EGSM900 DCS1800 4. Mask for defined Power Levels of both band.

These are lists of directories and files using in CALMON. User/MMI Data — Volume. Table 2.0 1842. TL is the test signal level in dBm PMAV is an average over the two power measurements by the DSP AGC is the IF gain in dB 11.5 -74.1800 /gsm/rf/tx/caltemp. * Note : Instead of step 5 to 8 you could also test only at the ARFCN center frequency modulated by a pseudo–random bit sequence (PRBS).4.900 /gsm/rf/tx/caltemp. Calibration S/W User Guide Ver 1. Initial AFC DAC value.8 4.900 GSM RF calibration and configuration.Download GMagic to MS.0 10.58 - . AFC parameters RF Transmitter PA ramps for GSM/EGSM RF Transmitter PA ramps for DCS RF Transmitter levels table for GSM/EGSM RF Transmitter levels table for DCS RF Transmitter channel calibration for GSM/EGSM RF Transmitter channel calibration for DCS RF Transmitter temperature calibration for GSM/EGSM RF Transmitter temperature calibration for DCS RF Receiver AGC global parameters RF Receiver AGC gain programming words table RF Receiver AGC il2agc tables RF Receiver channel calibration for GSM/EGSM . Mosts are for RF Calibration parameters.900 /gsm/rf/tx/levels. Melodies.1800 /gsm/rf/tx/calchan. Flash File System is consist of the Hierarchy of directories and files.900 /gsm/rf/tx/ramps. This includes RF calibration parameters and System Configuration. Test Data.4 Flash File System Flash File System (FFS) is used for storing many kinds of data and configuration parameters that should be non-volatile across power-cycles. SMS. Calculate GMagic = (PMAV – AGC – TL)x2.3. /gsm/rf/ 4 /gsm/rf/afcdac /gsm/rf/afcparams /gsm/rf/tx/ramps. etc adjusted and programmed during Calibration and production test.5 Test frequency [MHz] 943. Production Adjustment.1800 /gsm/rf/rx/agcglobals /gsm/rf/rx/agcwords /gsm/rf/rx/il2agc /gsm/rf/rx/calchan.1800 /gsm/rf/tx/levels.900 /gsm/rf/tx/calchan.3 Test settings for calibrating GMagic Receive Band EGSM900 GSM1800 Test ARFCN 40 700 AGC setting [dB] 34 ˜ 34 TL [dBm] -74.

Calibration S/W User Guide Ver 1. Set the Power supply Voltage to 3. And Flash File System Access is for Accessing to Read and Write Control through the Flash.2V (cc2cv_Voltage) 3. 4.900 /gsm/rf/rx/agcparams. Table 4. if it is. Save it to FactorySettingData. Read ADC value and Compare whether Adc value is in between Lower Limit and Upper Limit.4.35V (Shutdown_Voltage) Lower Limit 0x250 0x1d0 Upper Limit 0x290 0x210 .5 Battery Calibration The battery sensor uses the baseband ADC to read the battery voltage (Vbat). 2.4. Read ADC value and Compare whether Adc value is in between Lower Limit and Upper Limit. Proceed with the steps above until two Voltage levels have been calibrated. Measuring the ADC slope and offset makes it possible to correct this in the SW.1800 RF Receiver channel calibration for DCS RF Receiver temperature calibration for GSM/EGSM RF Receiver temperature calibration for DCS RF Receiver AGC parameters for GSM/EGSM RF Receiver AGC parameters for DCS So. 4. *This directory contains RF calibration data and tables adjusted during production.2V specified in Table 4. and the ADC internal reference voltage is the largest contributor to measurement inaccuracy.3.1800 /gsm/rf/rx/agcparams.4 Battery Calibration Settings Voltage Level 4. 7. 6. if it is.cc2cv_Voltage value. this is a Flash File System structure.4. 5. Set the Power supply Voltage to 4. It also contains files that are only used during development for overriding compiled-in default data and parameters for the RF.59 - . Save it to FactorySettingData.shutdown_Voltage value. To calibrate the Battery Voltage the following steps have to be performed : 1.900 /gsm/rf/rx/caltemp. 3.35V specified in Table 4.1800 /gsm/rf/rx/caltemp.0 /gsm/rf/rx/calchan.

Band : You can select Band either GSM900 (EGSM) or DCS1800.1 APC DAC Calibration Figure 4-2.4 Program Operation 4.0 4. You can also change these parameters’ value.but. . .TCH : You can read current Target’s Tch Arfcn.4.60 - . APC DAC Calibration Basic Settings Window • Basic Setting Target Control .Tx Power Level : You can change the Tx Power level of Instrument .Update all values : You can read all values of current Window’s parameter from the Target Instrument Control . Arfcn will be changed automatically by the available value of selected Band. Calibration S/W User Guide Ver 1.4. If change the band.Cable Loss : Compensate the Cable Loss through the RF Cable . .Tx Power Level : You can change the Tx Power level of Target. Usually APC Level and Ramp template Index are followed accordingly by the value of Tx Power Level.

If not. Variance from Avg. { When you do the Measurement. In the Fig 4-3.4.4. So. APC Measurement Window Fig4-3 is a APC Measurement Window. Avg.1 APC Measurement Window Figure 4-3. etc statistical results are displayed. And the value measured from the instrument is compared with the Expected power pre-defined by the specification. measure the Target’s Tx Power read from the instrument by the value of current selection of Power Level. Calibration S/W User Guide Ver 1. Difference between Expected Power and Measured power. decide whether this compared value is in allowable Margin from specification or not. Statistics for Measured MS tx Power : it shows measured Tx Power Value. | Measured margin : to check how much margin measured power have from upper and lower limit specified. .0 4.start. you can select whether you consider Cable loss or not. And in addition. If it is.1. it’s the measurement of Tx Power Level 5 • Tx Power Measurement When click the x Meas. Min / Max. it will be filled red and written ‘Fail’. then fill Mask Test item green and write ‘Pass’ (y)..61 - .

You can just check the APC DAC Result shown from the z List Box and if you have more time to check.2 APC DAC Calibration Window Figure 4-4. y Processing time is the time taken during the entire APC DAC Calibration Procedure. It’s working Automatically through the levels pre-defined from the EGSM900 to the DCS1800 band.1. 5 to 19 for EGSM. it’s stored automatically in flash after APC DAC Calibration is completed. compare the { Tx power by this calibrated APC DAC with | Tx Power specified and check the accuracy of APC DAC Calibration. When click x CAL Start.0 4. APC DAC Calibration starts. the Calibrated data has to be stored in Flash File System . Fortunately. Calibration S/W User Guide Ver 1.4.4. . APC DAC Calibration Window • APC DAC Calibration APC Calibration is adjusting APC DAC that can make the wanted level output in antenna. Each band has different range of Power Level for Calibration. After all Procedure has done. Or see the Progress bar is running to the 100% end.62 - . 0 to 15 for DCS. Standard Channel for EGSM is Traffic channel 40 and for DCS is Traffic channel 700.

etc.1 will help you. As you see the Red Box in the Fig 4-5. to adjust Ramp Template Up/Down Coefficients for Ramping shape at assigned level can remain in Spec. there are 16 Indexes for both Up and Down Ramp Template each. And you can change the visual part of the graph as Full or Rising edge. APC Ramp Calibration Window • APC Ramp Calibration APC Ramp Calibration is for both GSM and DCS band.3 APC Ramp Calibration Window Figure 4-5. section 4. the window will show you the z avg. In this Window the upper part of Figure. When click the x Meas. But that’s similar to APC DAC Calibration. They are from the instrument. Tx Power of current Power Level and the plot for y Ramping Shape from current Ramp Index’s Coefficients’ values.4.63 - . but the sum of all coefficients has to be 128. there is basic setting menu for parameters.1.start. You can change each coefficient value. 31 Coefficients (0 to 30). And each Ramp Template Index has its coefficients.so.{ .Mask per each Power Level.0 4.4. Calibration S/W User Guide Ver 1.

4. Calibration S/W User Guide Ver 1.0

4.4.1.4 APC Channel Calibration

Figure 4.6. APC Channel Calibration When APC DAC Calibration is done for each Power Index, APC DAC for predefined channels should be calibrated for both GSM and DCS to make each Channel have Wanted Transmit Power. Standard Power Level Indexs for each band are for GSM Index is 10, for DCS Index is 5. So, At first get the APC DAC Calibrated Value at Standard Power Level Index and based on this calibrated value from Standard Power Level, do the calibration for each Channel predefined in Table 4.2. In this case, Default Channel Calibration Value is set to 128. After Channel Calibration, If output power is higher than specified value then decrease Channel Calibration Value at lower than 128. When click the x Chan Cal start, it will start to run automatically from EGSM900 to DCS1800 Band for each Arfcn predefined. So, y Whole Results will shown in List Box. z is APC DAC of Standard Channel , { is Calibration results for each channel, APC’s Compensated Value for each Channel. - 64 -

4. Calibration S/W User Guide Ver 1.0

4.4.2 AGC Calibration Window

Figure 4-7 AGC Calibration Parameters Control Window • Basic Setting Target Control - AFC Settings : Read x INI_AFC DAC value from the Target.and also you can write another value you want to change. But when you try to do AGC Calibration precisely, you should set the Calibrated INI_AFC value to the Target. - AGC gain : y Set the AGC gain Value to 34dB. It’s calculated based on the IL (Input Level = -74.5) from the Target. - AGC Algorithm : z To get the AGC G-Magic, Disable the AGC algorithm from L1.AGC Parameters : { | G-Magic Value will be updated automatically after the AGC Calibration is complete. And the other AGC Parameters (LNA ~)will have appropriate value from the definition. - Measurement setup : } You can choose the option to see the result you want. You can choose any of three selection (RSSI,DSP-PM and G-Magic) and also you can choose multiple selection. And the results will be displayed as you chose. The results will be updated moment by moment. Miscellaneous Control - Cable Loss : ~ Compensation for loss from RF cable between the instrument and the Tartget.You can set the value per Band. (It is defined at the every Cable) - 65 -

4. Calibration S/W User Guide Ver 1.0

4.4.2.1 AGC Calibration Measurement Window

Figure 4-8. AGC Calibration Measurement Window • AGC Calibration Measurement After the Basic Setting from Fig 4-6, based on the set value of AGC Calibration Parameters from current window, CALMON (CALMON’s AGC Calibration Measurement Menu) does AGC Measurement and displays the result. Measurement result that you already chose (} from fig 46) will be displayed. Figuring out from fig4-7, all of measurement options are chosen. RSSI, DSP-PM, G-Magic results are shown. When you click the x AGC Measurement, Measurement start. And if you click again, it will stop. y DSP-PM from target z PM mean from received PM values. { RSSI, | difference between the very first Power Level from instrument transmits and actually received Power Level that target received. only when you choose the | Îth option, you can also check the Cable Loss consideration ~. } Calculated G-Magic.

- 66 -

And also you can save the calibrated data to file and load calibrated data from file.2 AGC Calibration Window Figure 4-9. Feel free to choose the File name to save or load and directory in the dialog window. you can get the calibrated G-Magic z for each Band. after AGC Calibration.67 - . So.4. | you can choose this storing option. Calibration S/W User Guide Ver 1. you have to find out proper value of G-Magic. calibrated G-Magic has to be non-volatile to be applied permanently for the Target’s Performance. During the AGC Calibration.0 4. When AGC Calibration is done. it will start.2. So. Calibrated G-Magic value has to be stored in Flash RF part. It’s programmed to run automatically from EGSM900 to DCS1800 Band. DSP-PM accumulated value is used in Program internally. here is selective option for the { count of DSP-PM accumulation. So. Just click the y Save Config button or Load Config button. when calculate the G-Magic. make Power level received by Mobile equal to calculated power level by itself. . Current Count is 10. So. When you click the x AGC Calibration.4. AGC Calibration Window • AGC Calibraiton AGC calibration is for Adjusting G_magic.

4.3 Flash File Window• Figure 4-10.0 4. Calibration S/W User Guide Ver 1. you can read ({) or write (z)the contents of flash file data on the ListBox (|). . Once you selet the file you want.4.900 file in figure 4-10. x when you click the Select File utton. y The content of the Red Box is the selected flash file. following window will come.(Figure 4-9) Using this window. you can see the contents of /gsm/rf/tx/levels. Flash File Window It is intended to access Flash more simply like we access and control PC files at personal computer. you can load Flash File Data to file of PC or load the Flash file data from PC file without difficulty. There are more files’ list in fig 4-12.68 - .

make the hierarchy of directory as Fig 4-12.4. Flash has its own blueprint for the advanced operation.69 - . Flash is like blank space at first. The hierarchy of directories and files is not configured in the beginning. First. Calibration S/W User Guide Ver 1.0 Figure 4-11. And second. But downloading the Boot source and Application source. you should do Format the Flash before using Flash File System like you format the Floppy diskette before you use. Select File Save or Backup or Restore There is a caution for you to use Flash File System. .

4.70 - . Flash File Open Error Window . This window will ask you would want to format flash and create directories in flash. You can make complete both just clicking ‘OK’ button. Then following message window will come up.0 Figure 4.13. Figure 4. ‘’Diretory/directory/File” Window from Flash File System Although you do not format flash and make any directory in it. Calibration S/W User Guide Ver 1. you will access flash nevertheless.12.

2V.cc2cv_voltage means the value reading ADC register from Target after setting the target’s Vbat to 4.0 4.stop. and in additiions.4 Battery Calibration Window. Figure 4. When you chose it. And FactorySettingData. first You should choose the Voltage.71 - .4.4.14. then click the Cal. CALMON compare the value with the Limits and notify it as you see the Mask Test ‘Pass’( or ‘Fai l ’). If you want Calibration of AD. between Upper and Lower Limit. . CALMON will do Battery Calibration for both Voltage Level one by one. Calibration S/W User Guide Ver 1. Battery Calibration Window If you want to measurement ADC value. CALMON would set the power supply voltage to the value that you’ve chosen.

72 - .2. i.5. Then. B.Target SW* downloaded to mobile phones of this model.1 Download Equipment 1) Data Kit 2) Desktop or Notebook PC 3) Download tools 4) Mobile phones of this model 5.1. Otherwise downloading process won’t properly Note: Target SW* means any necessary software to be downloaded to the mobile phone.2 Download Procedure 5.The model’s Data Link Kit is connected to COM1. In order to download or upgrade Target SW* of each processor. COM2 or USB serial port in the Desktop or Notebook PC.exe.3 Download Procedure for Calypso Software A. • X-monitor : Download tool for Calypso software. choose “Connect” in the Target Menu.e. And then select the “Target ” Menu shown in Figure 5-1. the following working environments should be prepared: . .1 Download Setup 5.Download tools that are copied to Desktop PC or Notebook PC. 5.2 Download Environment This model has two micro-processor. .2.zip) in PC. Calypso and Helen. Warning You must use the Data Link Kit and Download tools for each processor that are provided from the manufacturer. . • FlashRW : Download tool for Helen software. DOWNLOAD 5.1 General Purpose This document gives a guideline for upgrading software of this model using UART or USB port.. DOWNLOAD 5.2. Execute x-monitor. 5. Unzip download tool for calypso processor (x-monitor.

DOWNLOAD Figure. If the connection is succeeded. the following screen will show the contents as shown in Figure 5-4. . 5-1 C. 5-2 D. A table will be displayed as shown in Figure 5-2. As the following window shown in Figure 5-3. And press “OK” button. connect the phone to Data Link Kit and power on it. Then press the arrow-button and choose a correct serial port. is displayed.5.73 - . Figure.

DOWNLOAD Figure.74 - . 5-4 E. Click on “Flash” on the top menu and select “Get type” item as shown in Figure 5-4. .5. 5-3 Figure. and select “Erase and Program Appli Only+Boot” item as shown in Figure 5-5.

75 - .5. DOWNLOAD Figure. . Figure. If the downloading procedure is succeeded. Finally choose the target SW that you want to download. And then you can see the following window in Figure 5-6. 5-5 F. 5-6 G. and then the following window is shown.

Figure. FlashRW supports an USB port also.exe. Executable used to load the software on Helen is FlashRW. 5-8 . click serial port configuration button and change your serial options in following screen.76 - .3 Download Procedure for Helen Software A. To change the attribute of serial port. It is available in FlashRW. 5-7 5.zip into the directory. Create directory and then unzip all files in FlashRW.2.5. B.zip. FlashRW opens a RS232 port automatically at startup. DOWNLOAD Figure. Start FlashRW application.

Default serial configurations are 115200-8-N-1.77 - . DOWNLOAD [ In the case of using RS232 port ] C. Figure. 5-9 . Following screen will be displayed if there is no error to open RS232 port in PC.5.

5. 5-10 . Figure.78 - . the following screen will be displayed in the log window as shown in figure 5-9. If the connection is succeeded. DOWNLOAD D. Connect G8000 phone to data link kit and power on G8000 after click “connect” button.

DOWNLOAD [ In the case of using RS232 port ] Note: Please make sure that LG-USB driver is installed correctly in PC. Contrary to RS232 mode. 5-11 .79 - . Please make sure that data link kit is unplugged at this step.5. FlashRW in USB mode is waiting for a target detection automatically when FlashRW is startup or click the connect button like as following screen. Figure. C.

If the connection is succeeded. DOWNLOAD D. the following screen will be displayed in the log window as shown in figure 5-9.5. 5-12 .80 - . Figure. Connect G8000 phone to data link kit and press power key until target flash writer code isprogrammed successfully or target work manager identified correctly.

5-13 . informations regarding loaded file are displayed like as follow. please make sure that each files are selected correctly. Figure. click each “File Select” button indicate in Fig 5-9. G.81 - . F. In case of choosing m0 extension file. A dialog open to select m0 or cp64 extension file. Click download button. this one is compressed in a cp64 extension file. DOWNLOAD E. Before the download. Once load is finished. In order to choose the target SW that you want to download. Select your TargetSW using check box.5.

1 and change Serial Port Configuration from COM port to USB before you install USB driver. You can use “Add new hardware” from control panel or Plug and Play function to install the driver.1 Objective This document is for installation of USB host driver when using FlashRW USB version. (Refer to the Removal of Driver) .sys and LG_G8000_usb04.inf file is for installation and *.3.3. *. .82 - .sys for driver.For instance. delete data about previous driver file or installation file in Registry and WinNT system relative Folder. Insert USB cable to PC or Notebook and cell phone. Me OS.5.2 Windows Driver Installation * Windows Driver Installation with Care Only one driver relative to the USB device should be installed First of all. 5. This can lead to a Blue Screen. It’s for Windows 2000.Download FlashRW ver2. . You never install this driver on Windows 98. 2) First of all.2.3 USB Driver Installation / Removal 5. DOWNLOAD 5. here we install LG03_KJHusb.inf.Put “ram_flashwriter_usb_v100.m0” into a flash writer code Select opening in FlashRW tool. (Refer to the FlashRW manual in detail) . 1) Copy those files into a temporary folder. Power on the phone then you can see the picture 1 below.

5. DOWNLOAD

Proceed after Picture 1.
1) Be careful the new hardware installation pop-up magic tool beforepower on the cell phone. Just cancel it.

Figure. 5-14 2) Select “No, Select new hardware from the item”.

Figure. 5-15 - 83 -

5. DOWNLOAD

. 3) Select other device from Picture 3. This is recommended.

Figure. 5-16 4 ) Click “Select from Disk” and select LG_G8000_usb04.inf file from the folder you made.

Figure. 5-17 5) How to check whether the driver file is installed properly or not: Go and check if G8000_usb is a new device from the control panel. - 84 -

5. DOWNLOAD

5.3.3 Windows Driver Removal
How to remove driver information registered on Registry : Use lg_02Cusb.sys on this document for example. 1) Let the Registry window pop on with regedt32 keyword input.

Figure. 5-18

- 85 -

Figure. Vid is Vendor ID and Pid is Product ID. Only administrator is authorized to edit registry in Windows 2000. If you see the message which tells no authority to you. . DOWNLOAD 2) Delete the contents in the 3 folders within the square box from the picture2.5. then click Security (blue colored circle in the picture 3) from the menu and terminate it.86 - . Refer to the Vid and Pid in order to delete the folders relative to the device. 5-19 3) Picture3 shows the contents to be deleted from the folders.

5-20 Figure. 5-21 .5.87 - . DOWNLOAD Figure.

Figure. (Mostly oem.inf/pnf files) .inf. 7 ) Delete *. Controlser002. DOWNLOAD 5 ) Delete LG03_usb folder from the folders in the Service. 5-22 6 ) Repeat from 3) to 5) for the (Controlset001. Currentcontrolset) folders.sys file relative to the USB in the WINNT\System and drivers folders. If you delete the contents within the Services. 8 ) Delete *.5. . then you do not need to give any authority.88 - .pnf files relative to the USB in the WINNT\inf folder. Warning! Do not really care whether there are all the folders we refer here or not.

TROUBLE SHOOTING Figure. 6-1 shows a measurement set-up. Figure 6-1. TROUBLE SHOOTING 6. Measurement set-up .89 - .6.

TROUBLE SHOOTING TOP & BOTTOM SW101 N101 U101 FL103 FL101 U102 D101 Fig 6-2 FL101 FL104 U105 FL105 Fig 6-3 .6.90 - .

1 Rx Trouble (EGSM) Set up Test with CalMon (62CH. R502.4MHz FL105 pin 4. R506 or Peripheral circuit Rework Calibration (Over G_MAGIC 170) . 6 RF signal is over -66dBm NO Check FL105 or Peripheral circuit YES @ 1854. R506 I/Q signal is over 60mV YES NO Check R501. 7 LO signal is over -26dBm NO Check FL102 or Peripheral circuit YES Sector Power -85dBm U105 18. 19.8MHz FL102 pin 5. AGC 24dB (High Frequency Probe) FL103 : FL105 : FL101 : FL102 : U105 : Antenna S/W Rx SAW Filter Dual VCO Balun RF Main Chip @ 947. TROUBLE SHOOTING 6. R502.4MHz FL103 pin 2 RF signal is over -63dBm NO Check FL103 or Peripheral circuit YES @ 947. R505. Sector Power-60dB.6. 21 I/Q signal is over 60mV NO Check U105 (Oscilloscope) R501.91 - . 20. R505.8MHz FL101 pin 3 LO signal is over -23dBm NO Check FL101 or Peripheral circuit YES @ 1854.

R505. R506 or Peripheral circuit YES Rework Calibration (Over G_MAGIC 170) . R502. 7 LO signal is over -26dBm NO Check FL102 or Peripheral circuit YES Sector Power -85dBm U105 pin 18. R502. R505.8MHz FL104 pin 4. 21 I/Q signal is over 60mV (Oscilloscope) NO Check U105 YES R501.2 Rx Trouble (DCS) Setup Test with CalMon (700CH. TROUBLE SHOOTING 6. R506 I/Q signal is over 60mV NO Check R501.4MHz FL101 pin 4 LO signal is over -23dBm NO Check FL101 or Peripheral circuit YES FL102 @ 921. Sector Power -60dBm.8MHz FL103 pin 6 RF signal is over -63dBm NO Check FL103 or Peripheral circuit YES @ 1842. 19.92 - .4MHz FL102 pin 5. 20. 6 RF signal is over -63dBm NO Check FL104 or Peripheral circuit YES @ 921. AGC 24dB) (High Frequency Probe) FL103 : FL105 : FL101 : FL102 : U105 : Antenna S/W Rx SAW Filter Dual VCO Balun RF Main Chip @ 1842.6.

Is it the same as Fig 7-15. DAC value 700 Power Level: GSM 5. DAC value 600 DCS:512CH. 12. Fig. DATA. D102 and peripheral circuit YES Check the voltage level of U105 (pin59) and FL101 (pin 9).K? NO Check or change U503 or U501 and peripheral circuit YES Check CLK. NO Check or change U503 and peripheral circuit YES Check theTx IQ Signal level of U105 (pin18~21) (R501. Can you observe RF Signal? (GSM : 1319.(GSM). DCS 0 Test DC Voltage : 4.93 - . 2. 12). TROUBLE SHOOTING 6.6. Is it similar to Fig.502. 13) of U105 Are the signals similar to Fig 7-13. D103 and peripheral circuit YES Check Main VCO RF Signal (pin 35) of U105. Can you observe RF Signal(GSM : 858.2MHz. EN(pin 11. Are they the same as the truth table? YES 1 . 11.2MHz) NO Check or change U105.0 V U503 : CALYPSO (BB Digital Main Chip) U501 : NAUSICA_CS (BB Analog Main Chip) U101 : PAM (PF08122B) U105 : RF Main Chip (TRF6150) FL101 : Dual VCO (ENFVF382S18) FL103 : Antenna S/W (SHS-M090B) N101 : Directional coupler (LCD15D190A0007A) D101 : Shottky Diode (BAT 15-05W) D103 : Dual VaractorDiode (SMV1233-074) D102 : Varactor Diode (HVC369B) Check all VCC level of U105 Are they all O. NO Check or change U501 and peripheral circuit YES Check Aux VCO RF Signal (pin 23 or 24) of U105.506). 64) HBSW pin 11 LBSW pin 10 Check the switch pins of FL101 pin(10.3 Tx Trouble Setup Test with CalMon GSM:1CH. DCS : 1294.(DCS)? NO Check or change U105 and peripheral circuit between U105 (pin 59) and FL101 (pin 9) Truth Table GSM Low High Low DCS Low Low High YES TXRXSW pin 12 NO Check or change U105 (pin1.505. DCS: 832MHz)? NO Check or change U105.

DCS pin8) over -2dBm? (GSM 890.5V? Is the input power of FL103 (GSM:pin10. TROUBLE SHOOTING 1 Is the Modulated RF signal of FL101 (GSM:pin1.2MHz.94 - . DCS:pin8) over 25dBm? NO YES YES YES Check calibration calibration change FL103 Check or change D101 and peripheral circuit. DCS:pin5) over 27dBm? NO NO YES Is the PA_ON signal level of U105 ( pin 9) high( about 2. Change U105 Change U503 Change U501 Change U101 Check or change peripheral circuit between U105 (pin 48) and U101(pin 2) . DCS 1710.2MHz) NO Check or change peripheral circuit between output pins of FL101 and input pins of U101 YES YES Is the output voltage level of (pin 48) over 1.5V (DCS) ? NO Is the input voltage level of U101(pin 2) over 1.6. 1.2MHz) NO Check or change FL101 and peripheral circuit YES Is the Modulated RF signal of U101 (GSM:pin1.5V? Is the amplified RF signal of U101 (GSM:pin4.2V (GSM).2MHz. DCS pin6) over 3dBm? (GSM 890.8V)? NO YES NO Is the PA_Level signal voltage of U105 (pin 8) over 1. DCS 1710.

4 Voice Function Trouble A. Receiver START Connect the phone to network Equipment and setup call.6. Does sine wave apper at C523? Yes No Change the Main B'D Does sine wave apper at number 3 pin in key B'd CN2 No Change the Key B'D Yes Receiver Sodering OK? Yes No Resoldering Receiver Change the FPCB B.95 - . TROUBLE SHOOTING 6.0volt? Yes Change the Key Board Yes Yes Resoldering or Change U810 Does sine wave apper at number 4 pin in key B'd CN2 No Change the Key B'd Yes Receiver Sodering OK? Yes No Resoldering Change the FPCB . Speaker START Connect the phone to network Equipment and setup call. Setup 1KHz tone out. Does sine wave apper at R814? Yes No Change the Main Board Does sine wave apper at C850? No U809 Regulator output=3. Setup 1KHz tone out.

3v ? Yes No Rwsoldering of R815.96 - .=0. C814. Yes Check the MIC bias level at pad of MIC+ Yes Is the level of MIC+ =2. MIC. C817 and Reass the phone Change the MIC . R849. C815 after putting audio signal in MIC Yes A fwe hundred of mV of sivgnal are measured? Yes No Resoldering of C809. Microphone START Yes Connect the phone to network and setup call.0V. R848 Cheak the signal level at C809. TROUBLE SHOOTING C.6.

6. TROUBLE SHOOTING 6.97 - . Check the connection between FPCB and main board Connection OK ? No Reconnect FPCB or LCD module Yes Check the data line at the LCD connector Does data appear on the data line ? No Resoldering LCD connector Yes Change LCD module . LCD START Is power supplied to circuit ? Yes No Refer to power-on trouble Check the connection between LCD module and FPCb.5 Display Function Trouble A.

6. Camera START Check the connection of the Camera module and Main Board Coonection OK ? No Reconnect camera module Yes Check the signal lines at the Camera connector Do signals appear on the data line ? No Change Camera module Yes Any Other Problem . TROUBLE SHOOTING B.98 - .

R825 and change Q804. R826.99 - . TROUBLE SHOOTING 6. Q805 Yes Does high level state appear at number 30 pin in Key B'd No Change the key board Yes Vibrator soldering OK? No Resolding vibrator Yes Change the FPCB .6. Vibrator START Enter into UI menu and Select the vibrator Does high level state appear at number 3 pin of Q805? No Resolding R827.6 Other Function Trouble A. R829.

Charger START Check the pin and battery connect terminals of I/O connector Connection OK ? No Change I/O connector Yes No Is the TA voltage 5.2V ? Change TA Yes Is it charging properly after changing Q501 ? No Is it charging properly after changing D501 ? No Yes End Yes End Change the board .100 - .6. TROUBLE SHOOTING B.

pin4)? Yes USB pullup(U811.6.3V? Yes Change the board No Check host USB port or USB cable No Change U 810 No Change Q 809 No Resoldering R 877 .3V? Yes High level on USB detect(Q809. USB START (Measure during the state of USB madule running) Input power(U801.101 - . pin1) is 5V? Yes Output power(U810. pin5) is 3. TROUBLE SHOOTING C. pin5) is 3.

2. STAND ALONE TEST AND TEST POINTS 7. Receiver Testing Set-up To check the receiver the following conditions have to be set: 1. Set the DC power supply to 4.18) . output a CW signal of amplitude = -60 dBm at either: 947. QN (see Figure 7-16. 7-3 and compares your measurements with those shown in the diagram. 13MHz(see Figure 7-12) 5.1 Received RF Level and Checks This section shows the typical RF levels expected throughout the receiver path. EN (see Figure 7-13) 6. It will also be necessary to ensure that all the following power supplies and signals are present which control this part of the receiver circuit: 1.19) 7. 7-3. Testing Receiver Using a suitable high frequency probe measure the RF levels at the relevant points shown in Figure. STAND ALONE TEST AND TEST POINTS 7. The Control Signal of Antenna switch (see Figure 7-11 ) 2. QP. DATA.1 Testing Set-up 7. CLK.0 V. RX IP. Vtune(see Figure 7-17. Vreg 1.1. 2V85_VCTCXO (see Figure 7-8) 4. Note: All RF values shown are only intended as a guide figure and may differ from readings taken with other test equipment and leads. A block diagram showing the locations of the RF measurement points and levels is shown in Figure.4 MHz (CH62) when testing the GSM RX path or 1842.102 - . Lead and connector losses should always be taken into account when performing such RF measurements. If there are any major difference between the readings taken and those indicated then further investigation of that particular point will be required. On a signal generator or a GSM/DCS test box.7. IN. 6 MHz (CH699) when testing the DCS RX path.3 (see Figure 7-7 ) 3.2.

Set DAC ‘600’ for EGSM900 or ‘700’ for DCS1800 on service software.2 Transmitted RF Level and Checks This section shows the typical RF levels expected throughout the transmitter path. Note: All RF values shown are only intended as a guide figure and may differ from readings taken with other test equipment and leads. 2V85_VTCXO (see Figure. Vreg 1. 7-9. Select Channel. Select GSM or DCS mode on service software. 6. 10) 2. Set the DC power supply 4.7. IN.3 (see Figure. 7-7) 3.103 - . 4. Power up the GSM/DCS test set and then establishing a call with an attached mobile on active mode. 7-8) 4. It will also be necessary to ensure that all the following power supplies and signals are present which control this part of the transmitter circuit: 1. 7-14) 6.1. QN (see Figure. 2. Set the DC Power supply to 4. 13 MHz (see Figure. 3. Set the GSM/DCS test equipment to be stand-alone mode (asynchronous mode). Set the BCH and TCH ARFCN ‘62’ for EGSM900 or ‘700’ for DCS1800 on GSM/DCS test equipment. Lead and connector losses should always be taken into account when performing such RF measurements. 7-12) 5.2. 7-5 and compare your measurements with those shown in the diagram. TX IP. 5. Set TCH and BCH value to be same with GSM/DCS test equipment on service software. Vapc (see Figure. 8. TX Level and Input Level according to which parameter is required. STAND ALONE TEST AND TEST POINTS 7. Initialize target on service software. A block diagram showing the locations of the RF measurement points and levels is shown in Figure 7-5. 3.0 V. Transmitter Testing Set-up To check the transmitter the following conditions have to be set: 1. 7. PA_ON. 7-15) . QP. If there are any major difference between the readings taken and those indicated then further investigation of that particular point will be required. Click Test.0volts. 2. PA_LEVEL. 1. Testing Transmitter Using a suitable high frequency probe measure the RF levels at the relevant points shown in Fig. Configure the testing equipments as Figure equipment setup. The Control Signal of Antenna Switch(see Figure. 9.

1 RF components 7. RF components (Top side) .1 TOP Side FL102 FL104 U105 D103 D102 FL105 Figure 7-1-1. STAND ALONE TEST AND TEST POINTS 7.2 Testing Points 7.2.1.7.2.104 - .

2 Bottom Side SW101 N101 U101 FL101 FL103 U102 D101 U104 U103 X101 Figure 7-1-2. RF components (Bottom side) .7.2. STAND ALONE TEST AND TEST POINTS 7.1.105 - .

RF components Reference U105 FL103 U101 N101 U102 U103 U104 D102 Reference FL101 X101 FL102 FL105 FL104 SW101 D101 D103 RF main chipset Antenna Switch PAM Coupler NOR Gate Inverter LDO Varactor Diode Dual RF VCO VCTCXO Balun GSM RF SAW Filter DCS RF SAW Filter Mobile Switch Dual Schottky Diode Varactor Diode 7.2 Test point of RX Levels 5 6 4 3 1 2 Figure 7-2. Test point of RX Levels . STAND ALONE TEST AND TEST POINTS Table 7-1.2.7.106 - .

64dBm GSMlnan 90 o RXmixQp RXmixQn RXmixIp RXmixIn TESTvco DECRXmix . STAND ALONE TEST AND TEST POINTS Figure 7-3.3MHz TX .3MHZ RFout_rx = (P*A + B + FN/13)*1.62.13dBm RXLON LBswitch 16/17 P/P+1 4bits FN CLK13M RXLOP 4bits B 7bits A VC1 VC2 TXRXswitch HBswitch FL102 Balun VR4in CLK LBRX R3 TXRXcp MAINspup2 R2 Serial Control Logic & Resisters DATA EN RESETZ Vreg3 SHS-M090B LF 5 . Recevier RE Levels .0V 0.0V 0.6V 0.0V VC2 0.GSM:CH.63dBm x2 /2 4 .0V 0.107 :5/10 RX QP GSM :2 CRF AFC DCS TX RX TX RX VC1 2. -60dBm DCS:CH.10dBm HBRX CLARA TRF6150 HBswitch LBswitch TXRXswitch Vreg3 BIASref 7.0V 6 .0V 2.5~940 MHz 1850~1920 MHz 2.6/1. -60dBm 1 .699.62dBm GSMlnap 2 EGSM : 925~960 MHz SAESD942MCL0T00 DCSlnan 90 o DCS : 1805~1880 MHz HG42UP3 DCSlnap IN 3 902.66dBm IP QN .6V 0.

3 Test point of TX Levels 5 4 6 12 3 9 10 11 13 1. STAND ALONE TEST AND TEST POINTS 7.7 2. Test point of TX Levels .2.8 Figure 7-4.7.108 - .

0V) ~ 124Ch (1. Ch.62.5dBm 8 832~858 MHz 8/9 P/P+1 3bits B 6bits A /2 416-429MHz ATT1 LF R 3 TXRXc p MAINspup2 I N PFD 90 o R2 I P LDC15D190A0007A ATT2 PF08122B HBR X Q N Q P 12 32dBm 31. Transmitter RF Level .5dBm 9 10 -2dBm 2dBm GSM : 975CH (1.1V) 11 CLARA TRF6150 7. 29dBm MAINspup 1 LF MAINcp T X :5/10 R X :2 CR F VC 1 VC 2 1294~1356 MHz MAINvco 1 13 4 0dBm GSM : 15dBm DCS : 18dBm 7 2 2dBm TANK LF -3dBm TANK 16/17 P/P+1 4bits FN 4bits B 7bits A DCS EGSM Delay BAT15-05W BAT15-099 . 32dBm DCS : Pwr Lvl 0.700.6V) ~ 885Ch (1.109 3 6dBm APC OMIXrf 6 5 34dBm 33.GSM : 32dBm DCS : 29dBm GSM : Pwr Lvl 5. Ch. STAND ALONE TEST AND TEST POINTS Figure 7-5.5V) DCS : 512CH (0.

85V LB_SW HB_SW TXRX_SW Vapc PA_LEVEL PA_ON CLK. STAND ALONE TEST AND TEST POINTS 7.110 - .EN I/Q Figure 7-6.2.4 Control signal test points Vtune VC1 VC2 13MHz Regulator_2.DATA. Control signal test points .7.

3 Output Figure 7-8.111 - . 2V85_Vreg 1.7. 2V85_VCTCXO Supply Voltage . 2. STAND ALONE TEST AND TEST POINTS Figure 7-7.

112 - . Antenna S/W control voltage in DCS_TX .7. STAND ALONE TEST AND TEST POINTS Figure 7-9. Antenna S/W control voltage in EGSM_TX Figure 7-10.

7. Antenna S/W control voltage in RX Figure 7-12. STAND ALONE TEST AND TEST POINTS Figure 7-11.113 - . 13MHz Clock .

PA_ON. CLK. DATA. STAND ALONE TEST AND TEST POINTS Figure 7-13. PA_LEVEL. VAPC (GSM Tx Level=7) . EN Figure 7-14.114 - .7.

7. Tx I / Q Signal Figure 7-16. Rx I / Q Signal . STAND ALONE TEST AND TEST POINTS Figure 7-15.115 - .

DCS 512CH) . STAND ALONE TEST AND TEST POINTS Figure 7-17. PA_ON.116 - . Vtune (U105pin 9. GSM 1CH) Figure 7-18. Vtune (U105 pin 9.7. PA_ON.

117 - .7. STAND ALONE TEST AND TEST POINTS Figure 7-19. RX I/Q Signal (Extended) .

8. Removing Battery Cover 2. DiSASSEMBLY INSTRUCTION 8-1 Disassembly Instruction 1. Removing Screws . DiSASSEMBLY INSTRUCTION 8. Figure 8-1. 2 1 Figure 8-2. Remove the battery cover . Remove the battery pack and screws.118 - .push lockers at both end sides and slide down the battery cover.

and detach the camera FPCB from the main PCB 2 1 3 Figure 8-3.8. Disassembling Rear Cover 4. DiSASSEMBLY INSTRUCTION 3. 2 1 Figure 8-3. Remove the SIM connector and bracket. Detaching SIM Connector and FPCB . then detach them carefully with both hands. Detach the rear cover -use a thin plastic sheet to open the gap between front and rear covers.119 - .

First. 1 2 3 Figure 8-5. Then. detach FPCB as shown in the Fig. remove the main PCB and lift the camera out to detach the frame shield.8. Detaching Main PCB .120 - . DiSASSEMBLY INSTRUCTION 5. 8-5.

8. DiSASSEMBLY INSTRUCTION 6. Remove the antenna and window IrDA. Removing Antenna and Antenna-bushing.121 - . . and push away the antenna-bushing using a sharp awl. Disassembling Keypad and Mike 7. 1 2 3 Figure 8-7. Figure 8-6. Detach the keypad and mike.

8.122 - . Use a thin plastic sheet to open the gap between the cover folder upper and cover folder lower. Figure8-8. DiSASSEMBLY INSTRUCTION 8. Removing Cap Screws 9. Detaching Upper Cover . then detach the cover folder upper carefully with both hands 2 1 Figure8-9. Use a pin to remove Cap Screw and remove screws.

Use a sharp awl to remove the hinge. Detaching Front Cover . Figure 8-11.8. DiSASSEMBLY INSTRUCTION 10. Figure8-10.123 - . Removing Hinge 11. Detach the front cover from the lower cover.

.124 - . Remove FPCB from the slit of the lower cover. Figure 8-13. Detaching LCD and FPCB *Note:When you change FPCB. Figure 8-12. remove 'tape' and 'solder' firstly. Removing FPCB 13. Detach LCD very carefully and remove FPCB from the connector of LCD Module. DiSASSEMBLY INSTRUCTION 12.8.

125 - . When placing the main PCB on the frame shield. DiSASSEMBLY INSTRUCTION 8-2.8. push the center of it not to override the top button. insert the camera into the main FPCB before assembling them. 2 1 3 Figure 8-14. Assembly Note 14. Figure 8-15. First. Assembling Camera Main PCB 15. Assembling Main PCB .

Main Block diagram.127 - .1 Baseband Blockdiagram (Memory & Audio path) Figure 9-1-1.1. .9. BLOCK DIAGRAM 9.1 Main Board 9. BLOCK DIAGRAM 9.

BLOCK DIAGRAM 9.1.2 Baseband Blockdiagram (UART path) Figure 9-1-2. Main Block diagram.9. .128 - .

2 LCD Module Figure 9-2.9. . BLOCK DIAGRAM 9.129 - . FPCB Block diagram.

9. BLOCK DIAGRAM

9.3 RF

Figure 8-3. RF Block diagram. - 130 -

9. CIRCUIT DIAGRAM

9. CIRCUIT DIAGRAM
Main PCB Circuit (1/5)
1 2
TP505 TP503 TP501 TP502 R508 R507 0 TP521

3

4

5

6

7

8

9

10

11

12

CAL_TDO CAL_TCK CAL_TMS CAL_TDI A DTC_SENSE BAT_SENSE
R527 200K
R537

100K VRRTC R535 R536 R533 R531 SN74CBTLV3257DGVRU502 VCC S _OE 1A 2A C527 10p C517 10p UPR

A

R538

120K

VRIO

TP504

C524 0.1u

220K

10K

10K

crystalX501

R515

HEL_UART_DATA_RTS HEL_UART_DATA_CTS HEL_UART_DATA_TX HEL_UART_DATA_RX PC_UART_CTS PC_UART_RTS PC_UART_RX PC_UART_TX PWL_MAIN_LCD_BL
R543

2 5 11 14

1B1 2B1 3B1 4B1

R503

4 7

R510

R504

R521

VRMEM

R516

16 1 15

R544

100K

CCK13M CCK32K ONNOFF

10K

TP524

1

4

CAL_NTRST _RPWON

32.768KHz

0

3 6 10 13

1B2 2B2 3B2 4B2

3A 4A GND

9

R552 0

12 8

R518

ONNOFF_TO_BUF
C514 220n C505 18p

_END_ONOFF
VRIO

B

2

3

B

HEL_UART_CNTL_TX ONNOFF_BUF CCK32K HEL_UART_CNTL_RX
R545
R549 0

VRIO U504 NL27WZ126US 1 8 OE1 VCC 2 3 4 A1 Y2 GND OE2 Y1 A2 7 6 5

CCK32K_CUT PA_ON TSPEN TSPCLK TSPDATA RESETCL
C528 1000p

R523

CAL_TX_MBOX _HEL_SYS_RST C HEL_TX_MBOX
R517 0

TCXO_EN CLK13M PA_LEVEL RADIO_TEMP HEL_MCSI_CLK HEL_MCSI_FS HEL_MCSI_DI HEL_MCSI_DO

C

MMAUDIO_CAL_HEL
R563 10K

R548

100K

R547

L10 M10 N10 K9

0

A14 C13

B13

E13 F12 C12

A13 A12

N11 P11 L4 M4 N3 P3

B9 A9 E8 C9 D9

C8 D8 C7 A8 B8

N2 M2

K8 M9 P9 L9 N9

K7 L7

VRMEM VRIO

BU LT

MCSI_TXD MCSI_RXD MCSI_CLK MCSI_FSYNCH

NRESET_OUT IDDQ

MOTOR_EN EAR_SPEAKER_SW D CAL_UART_DCD CAL_UART_DSR MMAUDIO_CAL_HEL
R561 0 H10 H11 J14 H13 H12 H14 G12 M12 M14 L12 L13 J10 K11 K13 K12 K14 J11 J12 J13
CAL_ADD(22) CAL_ADD(21)

OSC32K_OUT

CLKTCXO CLK13M_OUT CLK32K_OUT

BCLKX BCLKR IO2 IO3 IO0 IO1

TX_IRDA RX_IRDA TXIR_IRDA RXIR_IRDA SD_IRDA

TX_MODEM RX_MODEM RTS_MODEM CTS_MODEM DSR_MODEM

RFEN TCSOEN

SDO SDI SCLK NSCS0 NSCS1

VSSO OSC32K_IN

1SS388

VBACKUP

TSPDI TSPDO TSPCLKX TSPEN0 TSPEN1 TSPEN2 TSPEN3 TSPACT0 TSPACT1 TSPACT2 TSPACT3 TSPACT4 TSPACT5 TSPACT6 TSPACT7 TSPACT8 TSPACT9 TSPACT10 TSPACT11 ADD21 ADD20 ADD19 ADD18 ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

R524

10K

D551

R556

R550

100K

TDR TEN

OSCAS PWON RPWON TESTRESETZ

CK13M

F1 B10 A10 F2

A4

J4 K4

NIBOOT

N1

D515 1SS388 R546 270

D511 1SS388 D10 F6 D7 H4 F7

C516 0.033u DAC AFC APC BULIP BULIM BULQP BULQM BDLIP BDLIM BDLQP BDLQM F10 F8 F9 C9 C10 D8 D9 E7 E8 E9 E10 K8 J8 K9 H9 H8 J9 J10 H7 G8 J7 B5 A5 E6 D6 C6 C5 A6 B6 A2 D4 B4 D5 A3 A1 B1 C3 J3 E5 E4 E3 K10 G2 G3 G4 H2 H3 J2 UPR C507 0.022u
5 4 G S

D

F10 ON_OFF D12 RESPWRONZ B14 IT_WAKEUP M3 EXT_IRQ EXT_FIQ P1 TP525 D11 B11 E10 D10 C10 B10 E9

ON_OFF RESPWRONZ RTC_ALARM INT2 INT1 TEST1 TEST2 TEST3 TEST4 TDO TDI TCK TMS BFSK BDX BFSR BDR VDR VDX VFS VCK UDX UDR UEN

AFC
R502 R501 R506 R505 36 36 36 36

IP
C501 270p C502 270p

C906 0F

U555 NC7SB3157P6X 1 B1 S 2 GND VCC 3 B0 A 6 5 4

VRIO

NBSCAN NEMU0 NEMU1 TDI TDO TCK TMS

C8 B8 A9 B9 C7 A7 B7 A8 J5 K5 G5 H5 K7 G6 G7 H6 J6 K6 F5

QP IM QM MICP MICN MICBIAS EAR_PIECEP EAR_PIECEM
C523 100p

E

DAI_SYNC DAI_CLK DAI_RX DAI_TX

CAL_ADD(20)

R562

CAL_ADD(19) CAL_ADD(18) CAL_ADD(17) CAL_ADD(16) CAL_ADD(15) CAL_ADD(14) CAL_ADD(13) CAL_ADD(12) CAL_ADD(11) CAL_ADD(10) CAL_ADD(9)

R598

CAL_ADD(7) CAL_ADD(6) CAL_ADD(5) CAL_ADD(4) CAL_ADD(3) CAL_ADD(2)

N7 MCUDI M7 MCUDO M8 MCUEN0 P8 MCUEN1 L8 MCUEN2 G13 SIM_IO F13 SIM_CLK G10 SIM_RST SIM_PWRCTRL SIM_CD NC F14 G11 C11 R528 R530 20K 10K VRIO

62K

C508

1u

R519

1M

20K

R511 R541 R542 0 0 CN803 1 G8000 2 3 4 5 6 7 8 9 10

CAL_ADD(1:22)

CAL_ADD(1)

CAL_DATA(15)

F

CAL_DATA(14) CAL_DATA(13) CAL_DATA(12) CAL_DATA(11) CAL_DATA(10) CAL_DATA(9) CAL_DATA(8) CAL_DATA(7) CAL_DATA(6) CAL_DATA(5) CAL_DATA(4) CAL_DATA(3) CAL_DATA(2) CAL_DATA(1) CAL_DATA(0)

D1

D2

D3 6 D4

VDDS_MIF1 VDDS_MIF2 VDDS_MIF3 VDDS_MIF4 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD_PLL VDDS_1_1 VDDS_1_2 VDDS_2 VDDANG VDDS_RTC VDDRTC

D5

D6

B3 A3 D4 C4 B4 E5 D5 B5 C5 E6 C6 A6 D6 E7 D7 B7

B2 C4 B3 VBAT_2 K2 K3 D2 G9

SDIO3 SCLK3 SRST3 VCC11 VCC12 VCC2 VCC3

SVDD SDIO5 SCLK5 SRST5 VAUX VS2 VS1 UPR VBACKUP VBAT VCHG ICTL BUZZOP NC1 NC2 NC3 NC4 NC5 NC6

PT501

HS_HF_SW

CAL_ADD(8)

L3 L2 L1 J5 K4 K2 K3 J4 J3 J2 J1 H5 H4 H2 H3 H1 G3 G2 G4 G5 F2 F3

U503 XF741979BGGH

L11 BFSR K10 BDR P12 BFSX M11 BOX P14 VDX N13 VDR M13 VSFRX N12 VCLKRX

MICIP MICIN MICBIAS EARP EARN AUXOP U501 AUXON AUXI PTWLR3012BGGM AUXGND AGNDA1 ADIN1 ADIN2 ADIN3 ADIN4_TSCXP ADIN5_TSCYP LCDSYNC TSCYM TSCXM

R526 R525

0 0

E

AUXOP AUXON AUXI

R599 10K

C521 10p

C522 10p

C509 C506 220n

1u

F

C542 C541 0F 0F 3G 3G

SP6

SP7

UPR

D512

1SS388

R569 1K

J1 10K R509 E2 D3 H1 E1 H10 C1 D1

FDBK VR2IN VR2SEL VR1OUT VR2OUT VR3OUT VR1BOUT VR2BOUT

R513

100K

CHARGER

VBACKUP VBAT VBAT_2 VBAT_RF

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSSPLL VSSANG VSSRTC

CAL_DATA(0:15)
RNW NFWE NFOE NBHE NBLE KBC4 KBC3 KBC2 KBC1 KBC0 CS4 NCS3 NCS2 NCS1 NCS0 FDP KBR4 KBR3 KBR2 KBR1 KBR0

Q501 NTHS5441T1

1

2

3

7

REFGND

8

GRND1

GRND2

GRND3

IBIAS

VREF

D501 CRS08

G1

K1

C2

G10

F3

F4

G

TP522

BAT501

B1 F1 K1 P2 P4 N8 P10 P13 G14 A10 A7 A2 E14 E12 C14

D1 G1 B6 A4 E1 M1 P7 N14 B12 A5 F11 N5 L14 A11 E11 D13 D14

B2 E3 E2 F5 E4

D2 D3 C1 C3 C2 F4

M5 P5 L5 K5 N4

L6 N6 P6 M6 K6

R512 0.2

SP8

SP9

C503 0.1u

G

120K

TP526

0.1u

C504 0.1u TP523 VRRTC

VRRTC VRABB VR1B

R520

_CAL_WR _CAL_RD _CAL_BHE

C519

U505 S-817A18ANB-CUH-T2
3 VOUT NC VIN VSS 2 1

1SS388

D510

_CAL_BLE

VRDBB

VRMEM

VRIO

C599 0.1u

4

H

_CAL_CS1 _CAL_CS0 _CAL_FDP
C520 0.1u C526 0.1u C518 0.1u C529 0.1u C525 0.1u C513 10u C511 10u C512 10u C515 15uF C510 10u

Engineer:
JS Lee

COMPANY NAME
Address City TITLE:
CALYPSO_IOTA 12 1 8 A

H

Drawn by:
mentor

R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Changed by:
mentor

Size:
A2

Date Changed:
Tuesday, December 11, 2001

Time Changed:
5:38:35 pm

QA CHK:

REV:

Drawing Number:

Page:
2

1

2

3

4

5

6

7

8

9

10

11

12

- 131 -

9. CIRCUIT DIAGRAM

Main PCB Circuit (2/5)
1 2 3 4 5 6 7 8 9 9 10 11 12

HEL_PLL_1.5V

VBAT_2 HEL_IO_MEM_2.8V HEL_IO_MEM_2.8V C652 0.1u C653 0.1u HEL_CORE_1.5V

A
C605 1u
R602 51K R646 1 2 3 4 5 10K 10 9 8 7 6 R658 470

A

R628

R629

100K

4.7

U601 A3212ELH 1 VDD 3 GND OUT 2

MAIN_LCD_LED+

R627

U602 SC600BIMSTR
VOUT CF1+ VIN FID0 FID1 CF2+ CF1GND CF2EN

SP42

R680

C606 1u R645

HEL_IO_MEM_2.8V 10p C601

C651 10u

C602 0.1u

C617 0.1u

C616 C608 0.1u 0.1u

C607 0.1u

C610 0.1u

C615 0.1u

C609 0.1u

C618 0.1u

MAIN_LCD_BACKLIGHT PWL_MAIN_LCD_BL
R606 R609 10K 10K

C612

R647

100K

C676

1u

USB_DETECT USB_VDD USB_DP USB_DM USB_VBUS B

B

220p

HEL_IO_MEM_2.8V

HEL_IND_LED_O
V20 T18 R19 R18 M15 AA17 E2 G1 F20 Y3 Y15 W20 W10 V5 V12 U20 U2 R21 N1 K20 K2 J20 B7 B5 B2 B18 B16 B1 AA7 AA21 AA1 A21 A13 A11 AA11 V2 R1 P3 L1 H2 E1 C2 B12 B10 A7 A5 A1 Y7 AA2 Y16 U21 L21 E21 A19 A15 Y21 Y20 Y1 R20 P12 M2 J21 F2 B20 B13 AA3 A9 A3 P9 R8 W4 V18 E5

SDA SCL GPIO_1 GPIO_0 GPIO_7 ARM_BOOT VSS26 VSS28 VSS27 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VDDSHV6 VDDSHV5_7 VDDSHV5_6 VDDSHV5_5 VDDSHV5_4 VDDSHV5_3 VDDSHV5_2 VDDSHV5_1 VDDSHV4_5 VDDSHV4_4 VDDSHV4_3 VDDSHV4_2 VDDSHV4_1 VDDSHV3 VDDSHV2 VDDSHV1_6 VDDSHV1_5 VDDSHV1_4 VDDSHV1_3 VDDSHV1_2 VDDSHV1_1 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 USB_DP USB_DM USB_CLKO CONF NC

VBAT_2 LCD_1.8V HEL_IO_MEM_2.8V CN602 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

C

CONN_21FXL_RSM_TB CN601 3 VDD_H 2 VDD_L 5 SCL 8 SDA 17 D0 14 D1 15 D2 18 D3 PC_UART_TX 11 D4 PC_UART_RX 12 D5 CAL_TMS 9 D6 CAL_TCK 10 D7 CAL_TDO 20 CKIN CAL_TDI 7 HS CAL_NTRST 16 DCK HEL_FOLDER_DET 6 XRST 13 VS 1 NC1 _END_ONOFF 21 NC2 KEY_ROW0 4 GND1 KEY_ROW1 19 GND2 KEY_ROW2 22 GND3 KEY_ROW3 23 GND4 KEY_ROW4

HEL_FADD(1:23)
HEL_FADD(1:23)

R664 R665 R667 R668 R669 R670 R671 R672 R673 R674 R675 R914 R677 R678 R679

270 270 270 270 270 270 270 270 270 270 270 270 270 270 270

_YMU762_RST
SP31 SP32 SP33 SP34 SP38 SP35 SP36 SP37 SP39 SP40 SP41

C604 0.1u

C603 0.1u

C908 18p

C909 18p

C910 18p

C905 18p

MAIN_LCD_RES MAIN_LCD_CD_SEL MAIN_LCD_DATA SUB_LCD_RES SUB_LCD_CD_SEL UWIRE_SDO

MAIN_LCD_CLK MAIN_LCD_DATA MAIN_LCD_CS MAIN_LCD_RES _YMU762_IRQ CAL_TX_MBOX STEREOJACK_DET MAIN_LCD_CD_SEL HEL_MCSI_CLK HEL_MCSI_DI HEL_MCSI_DO
R663 10K

HEL_IO_MEM_2.8V
C

D

LOUD_SPKP EAR_PIECEP MOTOR_BATT EAR_PIECEM LOUD_SPKM

Q666 DTC144EE
E

B

EL_ONOFF

R610

HEL_MCSI_FS SUB_LCD_CD_SEL

MAIN_LCD_LED+ UWIRE_SCLK SUB_LCD_CS MAIN_LCD_CLK MAIN_LCD_CS KEY_COL0 KEY_COL1 KEY_COL2 _END_ONOFF KEY_COL3 KEY_COL4 KEY_COL5 KEY_LEDHEL_EMU0 HEL_EMU1 HEL_NTRST HEL_TDI HEL_TDO HEL_TCK HEL_TMS PC_UART_RTS PC_UART_CTS
VBAT 1SS388 D699

KEY_COL0 KEY_COL1 KEY_COL2 KEY_COL3 KEY_COL4 KEY_COL5 KEY_ROW0 KEY_ROW1 KEY_ROW2 KEY_ROW3 KEY_ROW4 KEY_ROW0 HEL_UART_CNTL_RX HEL_UART_CNTL_TX HEL_UART_IRDA_RX HEL_UART_IRDA_TX HEL_UART_DATA_CTS HEL_UART_DATA_RTS HEL_UART_DATA_RX HEL_UART_DATA_TX HEL_UART_PC_CTS HEL_UART_PC_RTS HEL_TDI HEL_TDO HEL_TMS HEL_TCK HEL_NTRST HEL_EMU0 HEL_EMU1 HF_CALL_OFF_ON EL_ONOFF HF_DET

E

R681

R682

F

LD603

LD602

LD601

HEL_IO_MEM_2.8V

HEL_IO_MEM_2.8V TP666 R613 R605 10K

LNJ717W80RA1

LNJ717W80RA1

LNJ717W80RA1

U18 w21 V19 P15 N14 H15 G20 G21 H20 H18 Y8 W8 N20 M20 T19 Y9 W12 100K R12 Y2 W3 W16 Y4 Y12 P19 N15 V15 G19 W15 W19 R13 Y13 P13 100K AA20 B14 C14 G12 D13 C13 H11 D12 C12 G11 D11 C11 H10 G10 B9 G9 C8 G8 B8 D8 C7 D7 B6 C6 H8 C5 D6 B4 C4 D5 D10 C10 D9 C9 D4 B3 A2 H9 C3 C15

WIRE_SDI WIRE_SDO WIRE_SCLK WIRE_NSCS3 WIRE_NSCS0 PCM_SYNC PCM_CLKS PCM_BIT_CLK PCM_DATA_IN PCM_DATA_OUT GPIO_8 GPIO_9 GPIO_11 GPIO_15 ARMIO_4 COM_MCLK_OUT OSC32K_IN OSC32K_OUT OSC1_IN OSC1_OUT TI_RESERVED4 TI_RESERVED6 CLK32K_OUT GPIO_6 ARMIO_2 MPU_NRESET NRESETPWRON NRESET_OUT EXT_FIQ BT_MCLK_REQ BT_MCLK_OUT CLK32K_IN CLK32K_CTRL SADD_0 SADD_1 SADD_2 SADD_3 SADD_4 SADD_5 SADD_6 SADD_7 SADD_8 SADD_9 SADD_10 SADD_11 SADD_12 SDATA_0 SDATA_1 SDATA_2 SDATA_3 SDATA_4 SDATA_5 SDATA_6 SDATA_7 SDATA_8 SDATA_9 SDATA_10 SDATA_11 SDATA_12 SDATA_13 SDATA_14 SDATA_15 SBANK_1 SBANK_0 SDCLK_EN SDCLK NSDQMU NSDQML NSRAS NSCAS NSWE LCD_PCLK

L19 K14 K15 K19 K18 J14 J19 J18 H19 L15 J15 M19 L18 V8 V7 P10 W6 Y6 AA5 W7 U19 M14 V10 V11 P11 W11 R11 P20 Y10 AA9 W9 10K R10 V9 P14 N18 F18 D20 D19 E18 C21 C20 G18 F19 H14 E20 E19 P18 R14 AA15 V14 Y14 L14 M18 Y5 W5 R9 V6 AA13 V13 W13 W14 Y19 AA19 V17 W18 Y18 V16 W17 Y17 N19 N21 T20

CAM_D_0 CAM_D_1 CAM_D_2 CAM_D_3 CAM_D_4 CAM_D_5 CAM_D_6 CAM_D_7 CAM_EXCLK CAM_HS CAM_LCLK CAM_RSTZ CAM_VS ARMIO_3 COM_SPI_CLKR COM_SPI_DIN COM_SPI_RSYNC COM_SPI_CLKX COM_SPI_DOUT COM_SPI_XSYNC ARMIO_1 GPIO_2 MEDIA_CMD MEDIA_CLK MEDIA_CS MEDIA_DI MEDIA_DO GPIO_4 COM_PCM_CLK COM_PCM_DIN COM_PCM_DOUT COM_MCLK_REQ COM_PCM_SYNC COM_SHUTDOWN GPIO_12 KBC_0 KBC_1 KBC_2 KBC_3 KBC_4 KBC_5 KBR_0 KBR_1 KBR_2 KBR_3 KBR_4 GPIO_3 CTS1 RTS1 RX1 TX1 RX TX CTS2 RTS2 RX2 TX2 BT_PCM_BCLK BT_PCM_SYNC BT_PCM_DIN BT_PCM_DOUT TDI TDO TMS TCK NTRST NEMU0 NEMU1 NBSCAN GPIO_13 GPIO_14 ARMIO_5

U603 OMAP1510

FADD_1 FADD_2 FADD_3 FADD_4 FADD_5 FADD_6 FADD_7 FADD_8 FADD_9 FADD_10 FADD_11 FADD_12 FADD_13 FADD_14 FADD_15 FADD_16 FADD_17 FADD_18 FADD_19 FADD_20 FADD_21 FADD_22 FADD_23 FADD_24 FDATA_0 FDATA_1 FDATA_2 FDATA_3 FDATA_4 FDATA_5 FDATA_6 FDATA_7 FDATA_8 FDATA_9 FDATA_10 FDATA_11 FDATA_12 FDATA_13 FDATA_14 FDATA_15 NFCS_0 NFCS_1 NFCS_2 NFCS_3 NFBE_0 NFBE_1 NFOE NFWE NFRDY NFWP NFRP NFADV FCLK LCD_PIXEL_0 LCD_PIXEL_1 LCD_PIXEL_2 LCD_PIXEL_3 LCD_PIXEL_4 LCD_PIXEL_5 LCD_PIXEL_6 LCD_PIXEL_7 LCD_PIXEL_8 LCD_PIXEL_9 LCD_PIXEL_10 LCD_PIXEL_11 LCD_PIXEL_12 LCD_PIXEL_13 LCD_PIXEL_14 LCD_PIXEL_15 LCD_VSYNC LCD_HSYNC LCD_AC

J8 D3 C1 E4 D2 F4 E3 J7 F3 G4 G3 G2 K8 H4 H3 K7 J2 J4 J3 J1 L8 K4 K3 L7 N4 N2 N7 P2 P4 P7 R2 R3 R4 T2 T3 P8 U1 U3 T4 V3 M7 M3 M4 N8 L3 M8 U4 W2 H7 V4 W1 L4 N3 D18 B21 C19 G14 H13 A20 B19 C18 D17 D16 C17 B17 G13 A17 C16 D15 D14 H12 B15

HEL_FADD(1) HEL_FADD(2) HEL_FADD(3) HEL_FADD(4) HEL_FADD(5) HEL_FADD(6) HEL_FADD(7) HEL_FADD(8) HEL_FADD(9) HEL_FADD(10) HEL_FADD(11) HEL_FADD(12) HEL_FADD(13) HEL_FADD(14) HEL_FADD(15) HEL_FADD(16) HEL_FADD(17) HEL_FADD(18) HEL_FADD(19) HEL_FADD(20) HEL_FADD(21) HEL_FADD(22) HEL_FADD(23)

C

HEL_DATA(0:15)
HEL_DATA(0) HEL_DATA(1) HEL_DATA(2) HEL_DATA(3) HEL_DATA(4) HEL_DATA(5) HEL_DATA(6) HEL_DATA(7) HEL_DATA(8) HEL_DATA(9) HEL_DATA(10) HEL_DATA(11) HEL_DATA(12) HEL_DATA(13) HEL_DATA(14) HEL_DATA(15)

HEL_DATA(0:15)

D

HEL_NFCS_0 HEL_NFCS_1 HEL_NFCS_2 HEL_NFCS_3 HEL_NFBE_0 HEL_NFBE_1 HEL_NFOE HEL_NFWE HEL_NFRDY HEL_NFWP HEL_NFRP HEL_NFADV HEL_FCLK

E

TP606

TP605

TP603

TP607

TP601

TP604

TP602

TP608

F

10

3

10

3

1

3

1

1

10K

R636

_HEL_SYS_RST
HEL_IO_MEM_2.8V TP667

HEL_CLK_12M_OUT

R615

R666

10K

2

2

2

10K

R635

4

4

4

G

R616

G

HEL_TX_MBOX HEL_FOLDER_DET SUB_LCD_RES

PC_IRDA_SEL HEL_IND_LED_B MAIN_LCD_BACKLIGHT

UWIRE_SDO UWIRE_SCLK SUB_LCD_CS

SPEAKER_EN

CCK32K_CUT

HEL_FADD(1) HEL_NFOE HEL_NFWE

1K 470 470 1K

1K

R626

R622

R601

150

R607

10K

33

56

R640 R641 R642 R643

R644

R689

6

5

4

6

5

4

VBAT C671

R620

ONNOFF
Q602 NC7SB3157P6X

2.7K

20K

R611

HEL_IND_LED_G

R623

HEL_IND_LED_G
100
1 2 3 1 2 3

H

CHARGER

R619 10K

R624

10K

SP43

R612 12

Q601 EMX18

97SMX

12MHz

C614 18p

HEL_IND_LED_O

1 B1 S 2 GND VCC 3 B0 A

6 5 4

C673 C674 C675

47p 47p 18p

12

X601
1 2 3

C613 18p

EMX1 Q603

EMX1 Q604

C672

0F

R614

100K

Engineer:
Y.J. SEOK

R661

C666 0.1u

R621

COMPANY NAME
Address City TITLE:
OMAP1509 12 1 8 A

H

2.7K

47K

Drawn by:
Y.J. SEOK
6 5 4

SW601 2 4 R625 20K 1 3

SW602 24 1 3

SW603 2 4 1 3

R&D CHK: DOC CTRL CHK:

Size:
A2

HEL_IND_LED_B

KEY_LEDChanged by:
mentor

MFG ENGR CHK: Date Changed:
Monday, December 10, 2001

Time Changed:
5:25:44 pm

QA CHK:

REV:
0

Drawing Number:
9

Page:

1

2

3

4

5

6

7

7

8

9

10

11

12

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8V CAL_ADD(1) CAL_ADD(2) U702 J3 G4 K4 H5 H6 K7 G7 J8 K3 H4 J4 K5 J7 H7 K8 H8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CAL_DATA(0) CAL_DATA(1) CAL_DATA(2) CAL_DATA(3) CAL_DATA(4) CAL_DATA(5) CAL_DATA(6) CAL_DATA(7) CAL_DATA(8) CAL_DATA(9) CAL_DATA(10) CAL_DATA(11) CAL_DATA(12) CAL_DATA(13) CAL_DATA(14) CAL_DATA(15) VCCF1 VCCF2 VCCS J5 G5 J6 CAL_ADD(3) CAL_ADD(4) CAL_ADD(5) CAL_ADD(6) CAL_ADD(7) HEL_NFCS_0 D H2 F5 H3 C6 H9 _CEF1 _CEF2 _OE _WE _BYTE VSS0 VSS1 J9 G3 C701 0.8V HEL_IO_MEM_2.1u VRMEM _CAL_CS1 _CAL_RD _CAL_WR _CEF _OE _WE _BYTE _CAL_FDP E5 C5 D5 RY_BY _WP_ACC _RESET _CAL_BLE _CAL_BHE C704 0. 2001 Time Changed: 5:53:17 pm QA CHK: REV: Drawing Number: Page: 3 1 2 3 4 5 6 7 8 9 10 11 12 .1u G3 K3 G4 K4 K5 G5 K6 G6 H3 J3 H4 J4 H5 J6 H6 J7 H2 C5 J2 U703 TC58FVB641XB-70 HEL_DATA(0) HEL_DATA(1) HEL_DATA(2) HEL_DATA(3) HEL_DATA(4) HEL_DATA(5) CAL_ADD(8) CAL_ADD(9) CAL_ADD(10) CAL_ADD(11) CAL_ADD(12) CAL_ADD(13) HEL_NFCS_1 E5 RY_BY C5 _WP_ACC D5 _RESET HEL_NFBE_0 HEL_NFBE_1 C4 D4 J2 D6 K6 G8 _LB _UB _CE1S CE2S DU1 DU2 NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 A1 A10 B1 B10 C1 F1 F6 F9 F10 G1 G6 G10 L1 L10 M1 M10 10K HEL_DATA(6) HEL_DATA(7) HEL_DATA(8) HEL_DATA(9) R718 HEL_DATA(10) HEL_DATA(11) HEL_DATA(12) HEL_DATA(13) HEL_DATA(14) HEL_DATA(15) DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 _CE _WE _OE VDD J5 _CAL_CS0 HEL_FADD(1) HEL_FADD(2) HEL_FADD(3) HEL_FADD(4) HEL_FADD(5) HEL_FADD(6) HEL_FADD(7) HEL_FADD(8) HEL_FADD(9) HEL_FADD(10) HEL_FADD(11) HEL_FADD(12) HEL_FADD(13) HEL_FADD(14) HEL_FADD(15) HEL_FADD(16) HEL_FADD(17) HEL_FADD(18) HEL_FADD(19) HEL_FADD(20) HEL_FADD(21) HEL_FADD(22) CAL_ADD(14) CAL_ADD(15) CAL_ADD(16) E HEL_NFCS_2 HEL_NFWE HEL_NFOE H7 _BYTE C4 RY_BY D5 _RESET D4 G7000 EUASV _WP_ACC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 VSS1 VSS2 G2 F2 E2 C2 D2 F3 E3 C3 D6 C6 E6 F6 D7 C7 E7 F7 G7 D3 E4 F5 F4 E5 K2 K7 CAL_ADD(17) CAL_ADD(18) CAL_ADD(19) CAL_ADD(20) CAL_ADD(21) CAL_ADD(22) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 G2 F2 E2 D2 F3 E3 D3 C3 C7 E7 F7 C8 D8 E8 F8 D9 G9 F4 E4 D7 E6 E9 R797 R705 D J5 VCCF J6 VCCS A21 H2 H3 C6 H9 J9 VSS0 G3 VSS1 C702 0.8V R798 10K 10K 10K G HEL_NFRDY G H Engineer: JS Lee COMPANY NAME Address City TITLE: Memory 12 1 8 A H Drawn by: mentor R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Changed by: mentor Size: A2 Date Changed: Tuesday. CIRCUIT DIAGRAM Main PCB Circuit (3/5) 1 2 3 4 5 6 7 8 9 10 11 12 A A B B HEL_FADD(1:23) HEL_DATA(0:15) HEL_DATA(0:15) TH50VPF5781AASB HEL_FADD(1) HEL_FADD(2) HEL_FADD(3) HEL_FADD(4) HEL_FADD(5) U701 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 J3 G4 K4 H5 H6 K7 G7 J8 K3 H4 J4 K5 J7 H7 K8 H8 HEL_DATA(0) HEL_DATA(1) HEL_DATA(2) HEL_DATA(3) HEL_DATA(4) HEL_DATA(5) HEL_DATA(6) HEL_DATA(7) HEL_DATA(8) HEL_DATA(9) HEL_DATA(10) HEL_DATA(11) HEL_DATA(12) HEL_DATA(13) HEL_DATA(14) HEL_DATA(15) C HEL_IO_MEM_2.1u C4 D4 J2 D6 K6 G8 NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 _LB _UB _CE1S CE2S DU1 DU2 A1 A10 B1 B10 C1 F1 F9 F10 G1 G10 L1 L10 M1 M10 E NC8 NC9 NC10 NC11 NC12 NC13 HEL_NFRP F _HEL_SYS_RST R712 R711 0 F R708 R789 HEL_NFWP R710 0 HEL_IO_MEM_2.9.133 - . December 11.8V HEL_FADD(6) HEL_FADD(7) HEL_FADD(8) HEL_FADD(9) HEL_FADD(10) HEL_FADD(11) HEL_FADD(12) HEL_FADD(13) HEL_FADD(14) HEL_FADD(15) HEL_FADD(16) HEL_FADD(17) HEL_FADD(18) HEL_FADD(19) HEL_FADD(20) HEL_FADD(21) HEL_FADD(22) G2 F2 E2 D2 F3 E3 D3 C3 C7 E7 F7 C8 D8 E8 F8 D9 G9 F4 E4 D7 E6 E9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 CAL_DATA(0:15) C CAL_ADD(1:22) 10K 10K TH50VPF5683DASB HEL_IO_MEM_2.

9.1u U810 HF_SPK_N MOTOR_EN R825 2K B AUXOP AUXON R813 R814 R812 0 0 C3 COM1 A3 NC1 E A1 GND COM2 NC2 G2 USB_PWR C808 10p 100K R869 1 2 3 VIN GND VEN LP3985IM5X-3.8V Q809 UMC4N USB_DETECT 4 3 R896 4 3 1K R802 100K 2 5 R824 R801 R823 100K 10K 5 1K AVDD STEREOJACK_DET 3 4 B E U805 B4 Q810 DTC144EE E UMC4N Q808 C KEY_ROW1 1 1 2 E 2 5 R822 R828 1K MAX4684EBC C2 C806 10u B2 DAI_TX R804 C904 0.1u 0 H USB_VDD Engineer: DJ Jung R877 SPOUT2 2 C846 10u C849 0.5V C900 10u R829 10 R827 AVDD 47K C ONNOFF_BUF SPEAKER_EN MOTOR_BATT C856 10u U803 B4 UMT2907A Q805 B2 U809 1 5 IN OUT 2 GND 3 4 EN ADJ MIC5219BM5 C858 470p C R855 180K AVDD C855 R826 R857 270K MAX4684EBC HS_HF_SW C2 IN1 A2 IN2 G1 V+ C4 NO1 A4 NO2 C1 HF_SPK_P C 0 10u SPK_VDD Q804 DTC144EE C832 0.8V 5 D6 D5 3 4 P4 P2 4.134 - .2K C851 33u 2 LCD_1.8V D HEL_IO_MEM_2.1u COMPANY NAME Address City TITLE: AUDIO 12 1 8 A H Drawn by: mentor R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Changed by: mentor Size: A2 Date Changed: Friday.2K R835 8.8V R868 10K HEL_IO_MEM_2.3 5 VOUT USB_VDD C804 10p C807 10p B1 B3 BYPASS 4 C863 0.8V R819 B 220n C810 EAR_SPEAKER_SW AUXI 220n C821 C819 47p R871 470 R859 100 5 2 3 R847 10K 100 C3 A3 A1 GND COM2 NC2 C889 10uF G2 R846 0 UMC4N Q806 10K COM1 NC1 R803 0 E 10K 1 SMF05C D1 D2 D3 D4 D5 C802 47p C813 47p SP13 SP14 SP15 R881 R882 R883 R884 0 0 0 0 R816 DAI_RX CAL_UART_DSR CHARGER HF_MIC HF_CALL_OFF_ON HF_SPK_N HF_SPK_P HEL_UART_PC_RX HEL_UART_PC_TX R873 R872 470 F R888 R870 470 R867 R864 R863 R861 470 470 0 0 0 HEL_IO_MEM_2.1u 1 2 3 4 5 6 J801 R850 BAT_SENSE C 4 1 G1 V+ 1K 15 C4 IN1 A2 IN2 NO1 A4 NO2 C1 HF_MIC Q803 UMD2N 6 _RPWON Q807 DTC144EE HEL_IO_MEM_2.47u 1B2 2B2 3B2 4B2 3 6 10 13 2 1B1 2B1 3B1 4B1 2 5 11 14 3 4 5 LEDA LEDK C S 5 MBRM120LT3 R844 0 Q802 DTC144EE C853 330p MICBIAS 0.3K C843 DTC_SENSE R876 VREF 15 SPVDD IOVDD VDD 16 SPVSS VSS 9 R818 32 7 8 C828 0.1u 1000p 4 D-IC D- 3 GND D1 1 LOUD_SPKP R834 6 3.1u C809 R815 1K PC_IRDA_SEL R849 1K TXD SHIELD RXD SD VCC GND CIM-80S7B-T U801 U813 A VCC R821 8 10K C888 0F B R878 MICP OBG-15S44-C2 C814 27p C854 10u C857 27p HEL_UART_IRDA_RX C812 27p 12K HEL_UART_IRDA_TX E VBAT U812 NCP500SN18T1 5 1 VIN VOUT 2 GND 3 4 EN NC 12 8 MIC801 1 HEL_UART_PC_TX HEL_UART_PC_RX 6 7 D802 R811 100K D4 6 D3 3 D2 2 D1 1 G NTHS5441T1 4 Q801 GND L801 VFB 3 4 RUN A C852 47uF R843 2.01u C861 10u D HEL_IO_MEM_2.8V C866 10u 0.5V 20K 1M A R810 300K 1 U802SN74CBTLV3257DGVR 16 1 15 4 7 9 VCC S _OE 1A 2A 3A 4A GND C801 0. December 14.022u 12 13 C847 390p 14 2 19 R841 C850 47p 0 R840 SPK_VDD 0 18 HPOUT_R HPOUT_L EQ1 EQ2 G CLK1 _RST 30 A0 31 _RD 29 _CS 5 NC _WR _IRQ 28 3 27 26 25 24 23 22 21 20 1 4 HEL_CLK_12M_OUT _YMU762_RST HEL_FADD(1) HEL_NFOE HEL_NFCS_3 R817 R858 R856 R854 R853 470 620 620 620 620 470 R833 0 R894 0 R892 R890 R889 R887 U807 YMU762 FB111 1000p 1000p HEL_DATA(2) HEL_DATA(3) HEL_DATA(4) HEL_DATA(5) HEL_DATA(6) HEL_DATA(7) R865 SP10 SP22 SP26 SP28 SP20 SP27 SP21 SP19 SP25 SP11 SP4 SP2 SP3 SP1 VBUS GND SP5 5 2 SP29 SP30 LED MTR LOUD_SPKM 17 D803 SPOUT1 D0 D1 D2 D3 D4 D5 D6 D7 PLLC HEL_DATA[0] HEL_DATA(1) HEL_DATA(0:15) EQ3 U811 STF203-22 USB_DP 6 D+IC D+ 1 1000p HEL_NFWE _YMU762_IRQ HEL_DATA(0:15) 82K VBAT 0 CN802 25 VBAT_GND_1 26 VBAT_GND_2 1 BATT_ID 2 HF_MODE 3 DSR 4 PWR_+5V_1 5 PWR_+5V_2 6 ON_SW1 7 PCM_RXA_IN 8 PCM_CLK 9 PCM_SYNC 10 USB_RX 11 PCM_TXA_OUT 12 PWR_GND_1 13 RXD 14 CRS08 TXD 15 D804 USB_TX 16 USB_PWR 17 DCD 18 RI_TMS 19 PWR_GND_2 20 RFR_RTS 21 PWR_+4_2V_1 22 PWR_+4_2V_2 23 CTS 24 DTR 27 V_BAT_1 28 V_BAT_2 29 V_BAT_3 30 GND1 31 GND2 R851 D801 GND R862 B1 B3 1 3 4 5 6 F 2 G R837 C899 33u C867 10u SMF05C 6 5 4 3 D2 C859 C860 C862 D5 D4 D3 USB_DM 0 C844 0.1u C815 VRIO U804 1 5 IN OUT 2 GND 3 4 EN ADJ C829 10u MIC5219BM5 C830 470p B MICN R848 1K C817 27p 2 1 5 R808 B GND SP17 R906 SP18 R905 3 Y 4 150K ONNOFF_TO_BUF 2 HEL_IO_MEM_2. 2001 Time Changed: 3:09:32 pm QA CHK: REV: Drawing Number: Page: 4 1 2 3 4 5 6 7 8 9 10 11 12 .2K C845 0.8V C831 10u B TC7SZ08AFE R807 U890 1 5 VDD VOUT 2 GND 3 4 CE NC VBAT R1111N151B-TR 200K HEL_PLL_1. CIRCUIT DIAGRAMΩ Main PCB Circuit (4/5) 1 2 3 4 5 6 7 8 9 1 0 11 12 VBAT HEL_IO_MEM_2.8V USB_PWR CAL_UART_DCD HEL_UART_PC_RTS DAI_SYNC DAI_CLK HEL_UART_PC_CTS R860 470 C848 68n 11 10 R836 8.7uH R875 R842 8 7 U808 LTC1701BES5 1 VIN SW P3 P1 1 2 HEL_CORE_1.

7u TP111 TP110 TP109 C144 0.2p L104 12nH C163 0F C165 47p RESETCL R129 1K C143 12p 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 7 VC1 VC2 1 3 5 TP101 TP102 C138 27p C137 27p VC2 VC1 QM QP IM IP R140 2.1u 3G U105 TRF6150PAP 1 3 5 VBAT_RF PA_LEVEL PA_ON VRIO TSPCLK TSPDATA TSPEN CRF VR4I R105 R126 R125 R127 R124 R123 R128 C146 100nH 0 1K 0 1K 1K 1K 1000p C141 4.9.1u C139 R913 1K X101 13MHz 3 OUT 2 VR4I R122 1 2 0 R130 C147 2.9nH 8 DCS_TX GND1 10 EGSM_TX GND2 GND3 C192 47p 6 2 GND4 DCS_RX GND5 EGSM_RX GND6 2 C169 0F C173 0F C158 0.1u C157 0.135 - .2nH D101 BAT15-05W L152 SW101 KMS-502 L151 G1 RF G2 ANT DETD DETR L107 1.8 3 VEN GND VOUT VIN 4 BYPASS 5 C149 0.1u 100nH VBAT_RF R136 0 R112 0 C128 4.5nH C162 0F C160 47p 4 6 O1 O2 IN 2 C168 0F C172 0F C109 0F G1 G2 G3 47p 0 OUT101 C161 0F FL103 SHS-M090B 4 C155 0F ANT L101 15nH 3 5 9 11 12 13 15nH L102 C156 2.7u 3G C188 0F 3G C114 0.5K HBSW TRXSW VC1 1 2 3 4 A1 B1 Y2 GND VCC Y1 B2 A2 8 7 6 5 VREG3 VC2 LBSW TRXSW A1 1 C178 0F R142 2.9nH_1608 C167 1.5nH R138 C159 47p C199 1.3K GND10 GND9 VDD1 VDD2 R106 470 100nH 3G C115 4.1u C129 4.2p L103 12nH C166 47p 4 6 FL105 SAFSD942MCL0T00 O1 IN O2 G1 G2 G3 C171 3.2K C177 12p R137 680 RADIO_TEMP C183 1.2n_1608 C175 1.1u D102 HVC369B L105 3.8nH_1608 6.7u VAPC LBSW HBSW TRXSW R116 300K C131 33p HBSW VAPC DETD DETR 0F C107 R103 51 C135 7p 1.1K 0 R182 15K R183 RADIO_TEMP Engineer: Drawn by: R&D CHK: DOC CTRL CHK: MFG ENGR CHK: TITLE: GPRS 12 1 8 A COMPANY NAME Address City Size: A2 Changed by: mentor Date Changed: Monday. CIRCUIT DIAGRAM Main PCB Circuit (5/5) 2 3 4 5 6 7 8 9 10 11 12 VTUNE FL101 ENFVF382S18 FL102 LDB25D500A0004A C121 27p 5 B1 13 L153 100nH 7 8 9 10 11 12 G2 UB1 UB2 GND2 RF_4 SW_2 TX_RX_SW 14 FB112 C104 0F 8 GND5 C122 27p 6 NC2 7 B2 G1 C103 47p C102 0F 1 2 3 4 5 6 NC1 RF_1 GND1 RF_2 RF_3 GND4 VREG3 C110 10u 4 VT GND3 VCC SW_1 2 3 LBSW HBSW TRXSW 1 VTUNE C116 220p R107 47 C118 8200p R110 120 R111 1.2K R143 2.8K C117 220p C124 0F C105 47p C106 0F VBAT C130 C154 C125 C153 1000p 1000p 470u 470p R109 3.5nH C136 DETR LBSW VCC5 VREG3 VBAT3 R3 TXRXCP R2 MAIN_SPUP2 GND_TXCP VCC6 RX_LOP RX_LON VCC4 OMIXRF VBAT1 VREG1 GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 65 C198 0F C112 4.1u L110 L109 6.76K_1% C184 18n_3216 C181 0F C189 0F R139 1.2u GND VCONT R131 TP119 0 AFC PT101 U8000 R181 R180 5. 2001 Time Changed: 3:07:35 pm QA CHK: REV: Drawing Number: Page: 3 2 3 4 5 6 7 8 9 10 11 12 .7nH C164 2.1u C126 0.8nH_1608 C180 0F C151 C152 1000p 1000p C182 0.2u U104 LP3985IBPX-2. December 10.2p FL104 SAFSD1G84CB0T00 C170 2.1u RESETZ QN QP IN IP VCC7 AUX_VCOP AUX_VCON RX_MIXQP RX_MIXQN RX_MIXIP RX_MIXIN TEST_VCO DECRX_MIN BIAS_REF BANDGAP C145 27p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HBSW TXRXSW VCC10 MAIN_SPUP1 MAIN_CP VBAT2 VREG2 APC APCEN VR4IN CLK DAT EN AUX_CP VCC9 CRF VAPC FILT DETD DETR DCS_INAN DCS_INAP VCC3 PCS_INAN PCS_INAP GND_INA VCC2 GSM_INAN GSM_INAP MAINVCO VCC1 VCC8 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 L106 1.5n_1608 C174 10n_2012 C185 22p R145 1K D103 SMV1233-074 U102 NC7WZ02K8X A2 2 C176 12p CAT 3 R144 9.7u C127 0.2n_1608 R121 150K C140 1000p TP120 R132 0 CLK13M 4 Y GND A 3 2 CRF TCXO_EN 5 VCC NC 1 U103 TC7SZ04AFE 0.7u C113 0.01u VCC 4 1 C142 1u VBAT_RF C148 2.2K R141 0 C179 0.3nH C186 18p 8 GND8 GND7 GND6 GND5 R113 L150 U101 PF08107B 18 17 3 6 16 15 14 13 C133 47p 8 7 6 5 N101 LDC15D190A007A 1 IN1 COU_OUT 2 B_OUT1 GND1 3 IN2 GND2 4 TERM B_OUT2 4 5 GSM_1 DCS_1 GSM_0 DCS_0 R119 68 GND4 12 GND3 11 GND2 10 GND1 9 VCTL 7 VAPC 2 C132 7p C120 27p C134 22p R120 220 R117 82 VREG3 R115 3G C111 4.1u L108 4.7u C123 10p R114 470 R134 180 R133 30 R135 180 C150 47p 10nH C191 10p C119 47p 1 L191 3.

CIRCUIT DIAGRAM Keypad PCB Circuit (1/1) 1 2 3 4 5 6 7 8 9 10 11 12 KEY_ROW4 KEY_ROW3 KEY_ROW2 KEY_ROW1 V2.8 VBAT 10K 10K 10K KB18 KB2 10K V1.1u C3 0.8 R9 2K R8 R7 R6 R5 KB25 KB8 KB16 B C D E CN1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PC_UART_CTS PC_UART_RTS HEL_TMS HEL_TCK HEL_TDO HEL_TDI HEL_NTRST HEL_EMU1 HEL_EMU0 KEY_LEDKEY_COL5 KEY_COL4 KEY_COL3 KEY_COL2 KEY_COL1 KEY_COL0 MAIN_LCD_CS MAIN_LCD_CLK SUB_LCD_CS UWIRE_SCLK MAIN_LCD_LED+ LOUD_SPKM EAR_PIECEM MOTOR_BATT EAR_PIECEP LOUD_SPKP EL_ONOFF UWIRE_SDO SUB_LCD_CD_SEL SUB_LCD_RES MAIN_LCD_DATA MAIN_LCD_CD_SEL MAIN_LCD_RES KEY_ROW4 KEY_ROW3 KEY_ROW2 KEY_ROW1 KEY_ROW0 _END_ONOFF HEL_FOLDER_DET CAL_NTRST CAL_TDI CAL_TDO CAL_TCK CAL_TMS PC_UART_RX PC_UART_TX KEY_COL0 B V1.8 G R11 51K HEL_FOLDER_DET C1 10p G C2 0.8 CN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 KB23 KB24 KB20 KB1 KB13 EAR_PIECEP LOUD_SPKP R15 270 _END_ONOFF KEY_COL1 EL_ONOFF UWIRE_SDO SUB_LCD_CD_SEL SUB_LCD_RES MAIN_LCD_DATA MAIN_LCD_CD_SEL MAIN_LCD_RES MAIN_LCD_CS MAIN_LCD_CLK SUB_LCD_CS UWIRE_SCLK R14 R16 R18 R19 270 270 270 270 C KB21 KB6 KB9 KB14 R21 R22 R23 R24 270 270 270 270 KEY_COL2 MAIN_LCD_LED+ LOUD_SPKM EAR_PIECEM MOTOR_BATT D KEY_COL3 C4 C6 C8 R17 C12 C14 10K 47p 47p C11 C13 C15 47p 47p 47p C5 47p R20 C9 KB4 KB5 KB19 KB7 10K 47p 47p 47p 47p KB17 KB10 KB22 KB3 KEY_COL4 E KB26 KB15 KB11 KB12 KEY_COL5 F F VBAT V2.9. SEOK 39 39 U1 A3212ELH 1 VDD 3 GND OUT 2 LD13 LD14 LD15 LD10 LD11 LD12 LD16 LD3 LD1 LD2 LD4 LD5 LD6 LD7 LD8 LD9 COMPANY NAME Address City TITLE: KEYPADS 12 1 8 A H Drawn by: Y.8 KEY_ROW0 A A V2.136 - .8 V2.1u R1 R2 R4 R3 39 39 KEY_LEDH Engineer: Y. J . SEOK R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Changed by: mentor Size: A2 Date Changed: Thursday. 2001 Time Changed: 7:30:44 pm QA CHK: REV: Drawing Number: Page: 10 1 2 3 4 5 6 7 8 9 10 11 12 . J . December 13.

CIRCUIT DIAGRAM SIM PCB Circuit (1/1) J1 1 VCC 2 RST 3 CLK 6 GND 5 VPP 4 I_O CN1 1 2 3 4 5 6 7 8 9 10 .137 - .9.

PCB LAYOUT 10.138 - .10. PCB LAYOUT Main PCB Layout (1/2) .

PCB LAYOUT Main PCB Layout (2/2) .10.139 - .

10.140 - . PCB LAYOUT Keypad PCB Layout (1/2) .

141 - .10. PCB LAYOUT Keypad PCB Layout (2/2) .

142 - . PCB LAYOUT SIM PCB Layout (1/2) .10.

10.143 - . PCB LAYOUT SIM PCB Layout (2/2) .