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Page 5.01
CHAPTER 5 – CMOS AMPLIFIERS
Chapter Outline 5.1 Inverters 5.2 Differential Amplifiers 5.3 Cascode Amplifiers 5.4 Current Amplifiers 5.5 Output Amplifiers 5.6 HighGain Architectures Goal To develop an understanding of the amplifier building blocks used in CMOS analog circuit design. Design Hierarchy
Functional blocks or circuits (Perform a complex function)
Chapter 5
Blocks or circuits (Combination of primitives, independent)
Subblocks or subcircuits (A primitive, not independent)
Fig. 5.01
CMOS Analog Circuit Design Chapter 5 – Introduction (2/25/03) © P.E. Allen  2003 Page 5.02
Illustration of Hierarchy in Analog Circuits for an Op Amp
Operational Amplifier
Biasing Circuits
Input Differential Amplifier
Second Gain Stage
Output Stage
Current Current Current Source Mirrors Sink
Inverter Source Current Coupled Pair Mirror Load
Current Sink Load
Source Follower
Current Sink Load
Fig. 5.02
CMOS Analog Circuit Design
© P.E. Allen  2003
Chapter 5 – Introduction (2/25/03)
Page 5.03
Active Load Amplifiers What is an active load amplifier?
VDD
+ V T+ 2VON + VT+VON 
VCC
+ VEB + VEB + VEC(sat) 
MOS Loads IBias IBias
BJT Loads
IBias
IBias
+ V T+ 2VON  V+ T+VON MOS Transconductors BJT Transconductors
+ VBE + VCE(sat) + VBE Fig32001
It is a combination of any of the above transconductors and loads to form an amplifier. (Remember that the above are only some of the examples of transconductors and loads.)
CMOS Analog Circuit Design Chapter 5 – Section 1 (2/25/03) © P.E. Allen  2003 Page 5.11
SECTION 5.1  CMOS INVERTING AMPLIFIERS
Characterization of Amplifiers Amplifiers will be characterized by the following properties: • Largesignal voltage transfer characteristics • Largesignal voltage swing limitations • Smallsignal, frequency independent performance  Gain  Input resistance  Output resistance • Smallsignal, frequency response • Other properties  Noise  Power dissipation  Etc.
CMOS Analog Circuit Design
© P.E. Allen  2003
Chapter 5 – Section 1 (2/25/03)
Page 5.12
Inverters The inverting amplifier is an amplifier which amplifies and inverts the input signal. The inverting amplifier generally has the source on ac ground or the commonsource configuration. Various types of inverting CMOS amplifiers:
M2 M2 ID vIN vOUT M1 vIN ID vOUT M1 ID vIN vOUT M1 M2 VDD
VGG2
vIN
M2 ID I vOUT vIN D M1
M2 vOUT M1
Active Active Depletion NMOS Load PMOS Load NMOS Load Inverter Inverter Inverter
Current Source Load Inverter
Pushpull Inverter
Fig. 5.11
We will consider: • Active PMOS Load Inverter (active load inverter) • Current Source Load Inverter • Pushpull Inverter
CMOS Analog Circuit Design Chapter 5 – Section 1 (2/25/03)
© P.E. Allen  2003 Page 5.13
Voltage Transfer Characteristic of the Active Load Inverter
vIN=5.0V vIN=4.5V vIN=4.0V 0.5 vIN=3.5V K JI H vIN=3.0V 0.4
G
5V vIN=2.5V M2 W2 = 1µm L2 1µm ID + vOUT W1 = 2µm L1 1µm 
ID (mA)
0.3 0.2 0.1
F E
vIN=2.0V
M1 + vIN
M2
D
vIN=1.5V
C A,B

0.0
0
1
2
vOUT
3
4
5
vIN=1.0V 5 4
A B C
M2 cutoff M2 saturated
vOUT
3 2 1
d ate r u D at ve 1 s cti M 1a M E
F G H I J K
Fig. 32002
0 0
1
2v 3 IN
4
5
The boundary between active and saturation operation for M1 is vDS1 ≥ vGS1  VTN → vOUT ≥ vIN  0.7V
CMOS Analog Circuit Design © P.E. Allen  2003
Chapter 5 – Section 1 (2/25/03)
Page 5.14
LargeSignal Voltage Swing Limits of the Active Load Inverter Maximum output voltage, vOUT(max): vOUT(max) ≅ VDD  VTP (ignores subthreshold current influence on the MOSFET) Minimum output voltage, vOUT(min): Assume that M1 is nonsaturated and that VT1 = VT2 = VT. vDS1 ≥ vGS1  VTN → vOUT ≥ vIN  0.7V The current through M1 is
2 vDS1 (vOUT)2 = β (V − V )(v ( v − V ) v − ) − iD = β1 T DS1 T OUT GS1 2 1 DD 2
and the current through M2 is iD = 2 (vSG2 − VT)2 = 2 (VDD − vOUT − VT)2 = 2 (vOUT + VT − VDD)2 Equating these currents gives the minimum vOUT as, VDD − VT vOUT(min) = VDD − VT − 1 + (β2/β1)
CMOS Analog Circuit Design Chapter 5 – Section 1 (2/25/03) © P.E. Allen  2003 Page 5.15
β2
β2
β2
SmallSignal Midband Performance of the Active Load Inverter The development of the smallsignal model for the active load inverter is shown below:
VDD
S2=B2 rds2 + vout + vin gm1vin Rout + vout Fig. 32003
gm2vgs2 M2 ID vOUT G1 D1=D2=G2 + vIN vin gm1vgs1 M1 S1=B1
rds1
rds1
gm2vout
rds2
Sum the currents at the output node to get, gm1vin + gds1vout + gm2vout + gds2vout = 0 Solving for the voltage gain, vout/vin, gives K'NW 1L2 −gm1 vout gm1 1/2 = ≅ − = − K' L W vin gds1 + gds2 + gm2 gm2 P 1 2 The smallsignal output resistance can also be found from the above by letting vin = 0 to get, 1 1 Rout = gds1 + gds2 + gm2 ≅ gm2
CMOS Analog Circuit Design © P.E. Allen  2003
Chapter 5 – Section 1 (2/25/03)
Page 5.16
Frequency Response of the MOS Diode Load Inverter VDD Incorporation of the parasitic Cgs2 capacitors into the smallsignal model: M2 Cbd2 If we assume the input voltage has a Vout small source resistance, then we can Cgd1 Cbd1 write the following: CL
Vin M1
CM + Vin gmVin + Rout Cout Vout 
sCM(VoutVin) + gmVin Cgs1 + GoutVout + sCoutVout = 0 ∴ Vout(Gout + sCM + sCout) =  (gm – sCM)Vin
s sCM − g R 1 1 gm m out z Vout (gm – sCM) 1 = = g R = m out 1+ sRout(CM + Cout) Vin Gout+ sCM + sCout s
Fig. 32004
1  p1
where gm = gm1, and 1 Rout = [gds1+gds2+gm2]1 ≅ gm2 , CM = Cgd1 , and Cout = Cbd1+Cbd2+Cgs2+CL
CMOS Analog Circuit Design Chapter 5 – Section 1 (2/25/03) © P.E. Allen  2003 Page 5.17
−1 p1 = Rout(Cout+CM) ,
gm1 and z1 = CM
Frequency Response of the MOS Diode Load Inverter  Continued If p1 < z1, then the 3dB frequency is approximately equal to [Rout(Cout+CM)]1.
dB 20log10(gmRout) z1 p1 ≈ ω3dB
0dB
log10f
Fig. 5.14A
Observation: The poles in a MOSFET circuit can be found by summing the capacitance connected to a node and multiplying this capacitance times the equivalent resistance from this node to ground and inverting the product.
CMOS Analog Circuit Design
© P.E. Allen  2003
and the 3 dB frequency of active load inverter if (W1/L1) is 2 µm/1 µm and W2/L2 = 1 µm/1 µm. Cbd1 = 200fF.2 MHz.B vIN=1.2003 Page 5. the 3 dB frequency is 10.5V vIN=1.0 0 1 2 vOUT 3 4 5 vOUT M2 active 3 M2 saturated 2 E ed rat u t a ve 1 s ti M 1 ac M F G H I J K 1 0 0 1 2v 3 IN 4 5 Fig.3 volts vOUT(min) = 0. Thus. Cgd1 = 100fF. Cgs2 = 200fF.E.11 .4 ID (mA) 5V vIN=2.10x109 rads/sec p1 = 64.3 0.5V W2 = 2µm L2 1µm ID + vOUT W1 = 2µm L1 1µm  0.15 Regions of operation for the transistors: M1: vDS1 ≥ vGS1 VTn → vOUT ≥vIN .0V 0.0V M2 M1 + vIN M2 D C A.5 vIN=3.92V/V Rout = 9.VTp CMOS Analog Circuit Design → vOUT ≤ 3.VTp → VDD .0V vIN=4.5V vIN=2.E.Performance of an Active ResistorLoad Inverter Calculate the outputvoltage swing limits for VDD = 5 volts.1x106 rads/sec.17 kΩ including gds1 and gds2 and 10 kΩ ignoring gds1 and gds2 z1 = 2.0.12. using the parameters in Table 3.5V vIN=4.2V © P.vOUT ≥VDD VGG2 . CMOS Analog Circuit Design Chapter 5 – Section 1 (2/25/03) © P. the output resistance. Allen .7V M2: vSD2 ≥ vSG2 . Cbd2 = 100fF. and ID1 = ID2 = 100µA.5V v IN=3.2003 . Solution From the above results we find that: vOUT(max) = 4. CL = 1 pF.18 Example 5.418 volts Smallsignal voltage gain = 1.0V 0.Chapter 5 – Section 1 (2/25/03) Page 5.1 KJIH F G E 2. the smallsignal gain.2 0.0V 5 A B C 4 D  0. 5. Allen .19 Voltage Transfer Characteristic of the Current Source Inverter vIN=5.
E. Allen .16 © P. vOUT(max): vOUT (max) ≅ VDD Minimum output voltage.1µA 1µA CMOS Analog Circuit Design Strong inversion 10µA 100µA 1mA 10mA ID Fig. 5. The minimum output voltage is.110 LargeSignal Voltage Swing Limits of the Current Source Load Inverter Maximum output voltage. 5.VT2 2 VDD .VGG .VT1) 1  1 β2 β1 VDD . Allen .Chapter 5 – Section 1 (2/25/03) Page 5. vOUT(min) = vOUT(min) = (VDD .E. CMOS Analog Circuit Design Chapter 5 – Section 1 (2/25/03) © P. vOUT(min): Assume that M1 is nonsaturated.111 SmallSignal Midband Performance of the Current Source Load Inverter SmallSignal Model: VDD M2 vOUT G1 + vin M1  S2=B2 rds2 D1=D2 gm1vgs1 S1=B1=G2 + vout + vin gm1vin Rout + vout Fig.VT1 This result assumes that vIN is taken to VDD.2003 Page 5.15B VGG2 vIN ID rds1 rds1 rds2 Midband Performance: 2K'NW 1 vout −gm1 1 1 1 1/2 −1 ∝ = = !!! and R = ≅ out vin gds1 + gds2 L1ID λ1 + λ2 ΙD gds1 + gds2 ID(λ1 + λ2) logAv Amax Amax 10 Amax 100 Weak inversion Amax 1000 0.2003 .
z 1 Vout(s) Vin(s) = s 1 . if p1<z1. Rout = 38.26V and v OUT (min) = 0V. is K N ’W 1 110·1 ID = 2L1 (VGG1VTN)2 = 2·1 (30. CMOS Analog Circuit Design © P.17 as a current source CMOS inverter with PMOS parameters for the NMOS and NMOS parameters for the PMOS and use NMOS equations.12 . L1 = 1 µm. VGG1 = 3 volts. Use the capacitor values of Example M2 5. Using a prime notation to designate the results of the current source CMOS inverter that exchanges the PMOS and NMOS model parameters. vout/vin = −9.Chapter 5 – Section 1 (2/25/03) Page 5.7 2 = 0.Performance of a CurrentSink Inverter VDD + A currentsink inverter is shown in Fig.11 (Cgd1 = Cgd2). these limits are subtracted from 5V to get vOUT(max) = 4. Allen . first calculate the dc current. ID.7)2 = 291µA and f3dB = 2.7) 1.2V/V.113 Example 5. To find the small signal performance. Calculate the outputswing limits and VGG1 the smallsignal performance. 5.14 gm −1 gm = gm1. 5.E. To attain the output signalswing limitations. and the parameters of Table 3. 110·1 30. p1 = Rout(Cout+CM) .2003 Page 5.17 Current sink CMOS inverter. then the −3 dB frequency response can be expressed as gds1 + gds2 ω3dB ≈ ω1 = C gd1 + Cgd2 + Cbd1 + Cbd2 + CL CMOS Analog Circuit Design Chapter 5 – Section 1 (2/25/03) © P. Assume VSG1 that W 1 = 2 µm. W 2 = 1 µm. VDD = 5 vIN M1 volts.17.p1 where Cgd2 Cgd1 Vin Fig. L2 = 1µm.1 50·2 500. 5. we treat Fig.78 MHz. then we can write the following: s −gmRout 1 .112 Frequency Response of the Current Source Load Inverter Incorporation of the parasitic VDD capacitors into the smallsignal Cgs2 model (x is connected to VGG2): x M2 Cbd2 Vout Cbd1 M1 CL CM + Vin gmVin + Rout Cout Vout  If we assume the input voltage has a small source resistance.1 kΩ. Allen .12 ID vOUT describe M1 and M2.2003 . and z1 = CM 1 and Cout = Cgd2 + Cbd1 + Cbd2 + CL CM = Cgd1 and Rout = gds1 + gds2 Therefore.74V vOUT(max)’ = 5V and vOUT(min)’ = (50.E. Solution Figure 5.7 In terms of the current sink CMOS inverter. The dc current.
115 SmallSignal Performance of the PushPull Amplifier 5V CM M2 + vin M1 + vout Fig. Allen .0V A B C D E + vIN 0.0 0 H I G F vIN=3.2 0.5V E D vIN=2.0V v =4.B 5 4 vOUT 3 2 1 0 0 ve cti ted 2 a tura M sa 2 M ed rat u t a ve 1 s ti M 1 ac M F G Note the railtorail output voltage swing H I J K 1 2v 3 IN 4 5 Fig.19 + vin  gm1vin rds1 gm2vin rds2 Cout + vout   Smallsignal analysis gives the following results: K' (W /L ) + vout −(gm1 + gm2) K'P(W2/L2) N 1 1 = = − (2/ I ) D vin λ1 + λ2 gds1 + gds2 1 Rout = g + g ds1 ds2 gm1+gm2 gm1+gm2 z = CM = Cgd1+Cgd2 and −(gds1 + gds2) p1 = Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL If z1 > p1. 5.0.0V vIN=1.5V vIN=1.5V vIN=5.6 vIN=2.0V vIN=3.0V vIN=3.2003 Page 5.E.VT1 → vOUT ≥ vIN .E.4 0.5V J.5V vIN=0.0V IN vIN=4.8 vIN=2.7V M2: vSD2 ≥ vSG2VT2 → VDD vOUT ≥ VDD vINVT2 → vOUT ≤ vIN + 0. then gds1 + gds2 ω3dB = C + C + C + C + C gd1 gd2 bd1 bd2 L CMOS Analog Circuit Design © P.Chapter 5 – Section 1 (2/25/03) Page 5. Allen .114 Voltage Transfer Characteristic of the PushPull Inverter 1. 5.5V vIN=1.2003 .5V vIN=4.0V 5V W2 = 2µm L2 1µm ID + vOUT W1 = 1µm L1 1µm  ID (mA) 0.5V vIN=3.5V M2 vIN=2.18 Regions of operation for M1 and M2: M1: vDS1 ≥ vGS1 .0V vIN=1.7V CMOS Analog Circuit Design Chapter 5 – Section 1 (2/25/03) © P.0 0.K 1 M1  2 vOUT 3 4 C A.
VDD = 5 volts. and use the parameters of Table 3.245µS vin = 12µS + 15µS = 18.12 to model M1 and M2.117 Noise Analysis of Inverting Amplifiers Noise model: VDD en22 Noise Free MOSFETs eout2 M1 vin VDD M2 eeq2 Noise Free MOSFETs eout2 M1 Fig. L2 = 1µm. Therefore: vout 257µS . we will make the important assumption that both transistors are operating in the saturation region.6V/V Rout = 37 kΩ f3dB = 2.) Substitute the type of noise source. Assume that W 1 = 1 µm. 4. CMOS Analog Circuit Design © P. (This step assumes that the MOSFET is the common source configuration.116 Example 5.) Calculate the outputvoltagenoise spectral density. L1 = 1 µm.2003 . W 2 = 2 µm. Solution The output swing is seen to be from 0V to 5V.) Assume a meansquare inputvoltagenoise spectral density en2 in series with the gate of each MOSFET.13 . Allen . 1/f or thermal.2003 Page 5. Use the capacitor values of Example 5. Allen .110 * en12 vin M2 * * Approach: 1.86 MHz and z1 = 399 MHz CMOS Analog Circuit Design Chapter 5 – Section 1 (2/25/03) © P.) 2. Calculate the outputswing limits and the smallsignal performance assuming that ID1 = ID2 = 300µA.E.) Refer the outputvoltagenoise spectral density back to the input to get equivalent input noise eeq2. In order to find the small signal performance.E.Performance of a PushPull Inverter The performance of a pushpull CMOS inverter is to be examined. 5.Chapter 5 – Section 1 (2/25/03) Page 5.11 (Cgd1 = Cgd2). 3. eout2 (Assume all sources are additive).
) eeq2 = en12 1 + g e en12 eeq2 m1 n1 vin M1 M1 Up to now. 5. it was assumed that the gain was unity. Allen . Noise Noise VDD VDD g m1 2 Free Free 2 e 2 2 2 n 2 2.Chapter 5 – Section 1 (2/25/03) Page 5. 5.Continued When calculating the contribution of en22 to eout2.) Make L2>>L1.2003 Page 5.118 Noise Analysis of the Active Load Inverter 1. To verify this assumption consider the following model: en22 * + vgs2 gm2vgs2 rds1 rds2 + eout2 _ Fig. B1 K'2B2 L1 1/2 1/2 2 eeq(1/f) = 1 + fW L K' B L 1 1 1 1 2 To minimize 1/f noise.E.111 We can show that.2003 . CMOS Analog Circuit Design Chapter 5 – Section 1 (2/25/03) © P. maximize the gain of the inverter.119 Noise Analysis of the Active Load Inverter . W L K ' 1/2 8kT 21/2 2 1 eeq(th) =3[2K'1(W/L)1I1]1/2 1+ L2W 1K '1 To minimize thermal noise.110 1/f Noise KF B Substituting en2= 2fCoxWLK’ = fWL . Allen . 2.) choose M1 as a PMOS.) See model to the right.E. 1. vin * * Fig. the type of noise is not defined. eout2 gm2(rds1rds2) 2 = ≈ 1 en22 1 + gm2(rds1rds2) CMOS Analog Circuit Design © P. into the above gives.) eout = en1 g + en2 MOSFETs MOSFETs m2 M2 M2 * gm2 en2 2 2 eout2 eout2 3.) increase the value of W1 and 3. Thermal Noise 8kT Substituting en2= 3gm into the above gives.
Allen .E.Chapter 5 – Section 1 (2/25/03) Page 5. 5.) CMOS Analog Circuit Design © P. The total noise contribution can only be reduced by reducing the noise contribution of each device.2003 Page 5. eout2 = (gm1rout)2en12 + (gm2rout)2en22 or 2 gm2 2 en2 (gm2rout)2 eeq2 = en12 + (gm1rout)2en22 = en12 2 1 + gm1 en1 This result is identical with the active load inverter.120 Noise Analysis of the Current Source Load Inverting Amplifier Model: VDD en22 Noise Free MOSFETs eout2 M1 vin VDD M2 eeq2 Noise Free MOSFETs eout2 M1 Fig. CMOS Analog Circuit Design Chapter 5 – Section 1 (2/25/03) © P.2003 . Thus the noise performance of the two circuits are equivalent although the smallsignal voltage gain is significantly different.E. * vin en12 M2 * The equivalent inputvoltagenoise spectral density of the pushpull inverter can be found as eeq = m1 n1 2 m2 m1 g e g +g + g m2 n2 2 m2 m1 g e +g If the two transconductances are balanced (gm1 = gm2).121 Noise Analysis of the PushPull Amplifier Model: VDD en22 Noise Free MOSFETs eout2 M1 Fig.113. Allen . VGG2 vin * en12 M2 * * The outputvoltagenoise spectral density of this inverter can be written as. (Basically. both M1 and M2 act like the “load” transistor and “input” transistor. so there is no defined input transistor that can cause the noise of the load transistor to be insignificant.112. 5. then the noise contribution of each device is divided by two.
Chapter 5 – Section 1 (2/25/03) Page 5.5vID v + v 2 vID 1 vOUT = AVDvID ± AVCvIC = AVD(v1 . vIC. Allen . inputreferred.E. is the voltage difference between v1 and v2.v2) ± AVC 2 2 + where + vID vIC vOUT 2 AVD = differentialmode voltage gain AVC = commonmode voltage gain Fig. The commonmode input voltage.21A v1 and v2 are called singleended voltages.E. vID. vOUT v2 Differential and common mode voltages: Fig.DIFFERENTIAL AMPLIFIERS What is a Differential Amplifier? + A differential amplifier is an amplifier that amplifies the + + difference between two voltages and rejects the average or + v 1 common mode value of the two voltages. is the average value of v1 and v2 . 5. CMOS Analog Circuit Design Chapter 5 – Section 2 (2/25/03) © P.2003 .21 SECTION 5.2003 Page 5. Allen . v1+v2 ∴ vID = v1 .5vID and v2 = vIC . They are voltages referenced to ac ground.meansquare noise voltage en12 gm2 2 + en22 g m1 gm2 2 + en22 g m1 en12 gds1+gds2 CBD1+CGD1+CDG2+CBD2 en12 gm2 2 + en22 g m1 gmb2+gds1+gds2 CBD1+CGD1+CGS2+CBD2 gds1+gds2 CBD1+CGD1+CGS2+CBD2 en1 2 + gm2 2 en2 g 2 m1 gm1en1 gm1en1 2 2 g + g g g m2 m1 m2 m1 + + Inverting configurations we did not examine. 5.21B CMOS Analog Circuit Design © P.122 Summary of CMOS Inverting Amplifiers Inverter pchannel active load inverter nchannel active load inverter Current source load inverter nchannel depletion load inverter PushPull inverter AC Voltage Gain gm1 gm2 gm1 gm2+gmb2 gm1 gds1+gds2 gm1 ~ gmb2 (gm1+gm2) gds1+gds2 AC Output Resistance 1 gm2 1 gm2+gmb2 1 gds1+gds2 1 gmb2+gds1+gds2 1 gds1+gds2 Bandwidth (CGB=0) gm2 CBD1+CGS1+CGS2+CBD2 gm2+gmb2 CBD1+CGD1+CGS2+CBS2 Equivalent.2 .0.v2 and vIC = 2 ⇒ v1 = vIC + 0. The differentialmode input voltage.
5. 2. but modulation of VT. the ICMR is defined by the commonmode voltage range over which all MOSFETs remain in the saturation region. CMOS Analog Circuit Design © P. • Input offset voltage (VOS(in) = VOS) The input offset voltage is equal to the output offset voltage divided by the differential voltage gain. 5. Allen .2003 Page 5.E. VOS(out) VOS = AVD CMOS Analog Circuit Design Chapter 5 – Section 2 (2/25/03) © P.23 1. y n+ p+ n+ pwell v IBias ID M4 M3 ISS n+ Fig. • Output offset voltage (VOS(out)) The output offset voltage is the voltage which appears at the output of the differential amplifier when the input terminals are connected together.E. If the technology is nwell CMOS. there is no choice. CMOS technology.) Bulks connected to the sources: No modulation of VT but large common mode parasitic capacitance. The bulks must be connected to ground.) Bulks connected to ground: Smaller common mode parasitic capacitors.Chapter 5 – Section 2 (2/25/03) Page 5.23 Transconductance Characteristic of the Differential Amplifier Consider the following nchannel differential amplifier (sometimes called a sourcecoupled pair): VDD iD1 iD2 M2 v G2 + vGS2 VBulk Fig. Typically. • Input commonmode range (ICMR) The input commonmode range is the range of commonmode voltages over which the differential amplifier continues to sense and amplify the difference signal with the same gain. Allen .22 vG1 M1 + vGS1  Where should bulk be connected? Consider a pwell.2003 .22 Differential Amplifier Definitions • Common mode rejection rato (CMRR) AVD CMRR = A VC CMRR is a measure of how well the differential amplifier rejects the commonmode input voltage in favor of the differentialinput voltage. D1 G1 S1 n+ S2 G2 D2 VDD n+ nsubstrate y . .
The shortcircuit.4 0.0 1. transconductance is given as K '1 I SS W 1 diOUT 1/2 gm = dvID (VID = 0) = (βISS)1/2 = L 1 CMOS Analog Circuit Design © P.0 K '1 I SS W 1 diD1 1/2 gm = dvID(VID = 0) = (βISS/4)1/2 = (half the gm of an inverting amplifier) 4L1 CMOS Analog Circuit Design Chapter 5 – Section 2 (2/25/03) © P.Continued Defining equations: 2iD1 1/2 2iD2 1/2 vID = vGS1 − vGS2 = β and ISS = iD1 + iD2 − β Solution: ISS ISS βvID β2vID 1/2 iD1 = 2 + 2 ISS − 2 4ISS which are valid for vID < 2(ISS/β)1/2.6 0. We will select a current mirror load as illustrated below.8 0. Allen .25 Voltage Transfer Characteristic of the Differential Amplifier In order to obtain the voltage transfer characteristic.0 0.E. 5.0 1. VDD 2µm 1µm 2µm 1µm M3 iD3 2µ m 1µm M4 iD4 iOUT 2µm 1µm iD1 M1 iD2 vGS2 + + VDD 2 vOUT + M2 ISS M5 vGS1 vG1   2µm 1µm vG2 Fig.5 Fig.2003 Page 5. Allen . 5.414 0.25 VBias Note that output signal to ground is equivalent to the differential output signal due to the current mirror.414 2.E.24 Transconductance Characteristic of the Differential Amplifier .Chapter 5 – Section 2 (2/25/03) Page 5. a load for the differential amplifier must be defined.2003 .2 iD1 iD2 vID (ISS/ß)0. Illustration of the result: 2 4 and ISS ISS βvID β2vID 1/2 iD2 = 2 − 2 ISS − 2 4ISS 2 4 iD/ISS 1.24 Differentiating iD1 (or iD2) with respect to vID and setting VID =0V gives 2.
2003 .E.0.2003 Page 5. 33001 Regions of operation of the transistors: M2 is saturated when.27  CMOS Analog Circuit Design © P.E. 2·50 Note: VSG4 = 50·2 +VTP = 1 + VTP ⇒ vOUT ≤ 5 .7 = 4V CMOS Analog Circuit Design Chapter 5 – Section 2 (2/25/03) © P. vDS2 ≥ vGS2VTN → vOUTVS1 ≥ VIC0.5 1 Fig. M4 is saturated when.vGS2 vOUT vG2  M2 saturated M2 active 0. vSD4 ≥ vSG4 .1 .Chapter 5 – Section 2 (2/25/03) Page 5.26 Voltage Transfer Function of the Differential Amplifer with a Current Mirror Load VDD = 5V 2µm 1µm 2µm 1µm 5 4 iD3 2µm 1µm M3 iD1 M1 M4 iD4 iOUT 2µm 1µm M4 active M4 saturated VIC = 2V iD2 + vOUT (Volts) 3 2 1 0 1 0.5vIDVS1VTN → vOUT ≥ VICVTN where we have assumed that the region of transition for M2 is close to vID = 0V. Allen .27 Differential Amplifier Using pchannel Input MOSFETs VDD M5 VBias + vG1 vSG1 + M1 iD1 iD3 M3  IDD M2 vSG2 + iD2 iOUT iD4 M4 + vOUT + vG2 Fig.5 0 vID (Volts) + M2 ISS M5 vGS1  vG1 VBias 2µm 1µm + .7 + 0.VTP → VDDvOUT ≥ VSG4VTP → vOUT ≤ VDDVSG4+VTP The regions of operations shown on the voltage transfer function assume ISS = 100µA. Allen . 5.
2003 Page 5. 33003 + vout   Differential Transconductance: Assume that the output of the differential amplifier is an ac short.28 Input Common Mode Range (ICMR) ICMR is found by setting vID = 0 and varying vIC until one of the transistors leaves the saturation. Allen . VDD M3 iD3 iD1 M1 vid M5 VBias ISS M2 vout M4 iD4 iout iD2 + D1=G3=D3=G4 G1 + vid + vg1 G2 + vg2 C1 rds1 i3 1 gm3 rds3 S3 G2 G1 + vid + + vgs2 vgs1 gm1vgs1 D1=G3=D3=G4 i3 1 rds1 rds3 gm3 C3 C1 gm2vgs2 S1=S2=S3=S4 i3 rds2 rds4 C2 gm1vgs1 C3 S1=S2 rds5 rds2 gm2vgs2 i3 D2=D4 rds4 C2 S4 D2=D4 iout' + vout Fig.2003 . Allen .29 Example 5. CMOS Analog Circuit Design Chapter 5 – Section 2 (2/25/03) © P.SmallSignal Analysis of the DifferentialMode of the Diff. Highest Common Mode Voltage Path from G1 through M1 and M3 to VDD: VIC(max) =VG1(max) =VG2(max) =VDD VSG3 VDS1(sat) +VGS1 or VIC(max) = VDD . CMOS Analog Circuit Design © P.E.21 . However. 33002 VBias VIC(max) = VDD . we will continue to use the assumption regardless. Amp A requirement for differentialmode operation is that the differential amplifier is balanced†. gm1gm3rp1 iout’ = 1 + g r vgs1 − gm2vgs2 ≈ gm1vgs1 − gm2vgs2 = gmdvid m 3 p1 where gm1 = gm2 = gmd. rp1 = rds1rds3 and i'out designates the output current into a short circuit.VSG3 + VTN1 VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2 Lowest Common Mode Voltage (Assume a VSS for generality) where we have assumed that VGS1 = VGS2 during changes in the input common mode voltage.VSG3 + VTN1 Path from G2 through M2 and M4 to VDD: VIC(max)’ =VDD VSD4(sat) VDS2(sat) +VGS2 =VDD VSD4(sat) + VTN2 ∴ VDD 2µm 1µm 2µm 1µm M3 iD3 2µm 1µm M4 iD4 iOUT 2µm 1µm iD1 M1 iD2 vGS2 + + VDD 2 vOUT + M2 ISS M5 vGS1 vG1   2µm 1µm vG2 Fig. † It can be shown that the current mirror causes this requirement to be invalid because the drain loads are not matched.Chapter 5 – Section 2 (2/25/03) Page 5.E.
6V/V (104.444MΩ (2.27V/V) 1 1 rout = gds2 + gds4 = 25µA·0. output due to mode Output = due to vic M1M3M4 path M2 path Therefore: • The common mode output voltage should ideally be zero.2003 .210 SmallSignal Analysis of the DifferentialMode of the Diff.Continued Output Resistance: Differential Voltage Gain: vout gmd 1 rout = gds2 + gds4 = rds2rds4 Av = vid = gds2 + gds4 If we assume that all transistors are in saturation and replace the small signal parameters of gm and rds in terms of their largesignal model equivalents.2003 Page 5.22MΩ) CMOS Analog Circuit Design Chapter 5 – Section 2 (2/25/03) © P. we achieve vout (K'1ISSW1/L1)1/2 K '1 W 1 2 1 1/2 Av = vid = (λ2 + λ4)(ISS/2) = λ2 + λ4 ISSL1 ∝ ISS Note that the smallsignal gain is inversely vout proportional to the square root of the bias vin Stong Inversion current! Weak InversExample: ion If W1/L1 = 2µm/1µm and ISS = 50µA log(IBias) ≈ 1µA (10µA). VDD M3M4 1 M M3 M4 M2 + v ≈ 0V M2 out M1 vic + VBias  M5 Fig. Allen . then Fig.E.28A Total common Common mode Common mode output due to . 5. Amplifier .09V1 = 0. 33004 Av(nchannel) = 46.23V/V) Av(pchannel) = 31. Allen . • Any voltage that exists at the output is due to mismatches in the gain between the two different paths.4V/V (70.Chapter 5 – Section 2 (2/25/03) Page 5.211 Common Mode Analysis for the Current Mirror Load Differential Amplifier The current mirror load differential amplifier is not a good example for common mode analysis because the current mirror rejects the common mode signal.E. CMOS Analog Circuit Design © P.
Allen .2003 Page 5. vo1.2003 . 33005 DifferentialMode Analysis: gm1 vo2 gm2 vo1 ≈ and ≈ + vid 2gm3 vid 2gm4 Note that these voltage gains are half of the active load inverter voltage gain.E. as a function of vic can be written as gm1[rds3(1/gm3)] (gm1/gm3) gds5 vo1 = ≈ ≈ 1 + 2gm1rds5 1 + 2gm1rds5 vic 2gm3 CommonMode Rejection Ratio (CMRR): vo1/vid gm1/2gm3 CMRR = v /v  = g /2g = gm1rds5 o1 ic ds5 m3 How could you easily increase the CMRR of this differential amplifier? CMOS Analog Circuit Design © P. 33006 Solving for vgs1 gives vic vgs1 = 1 + 2g r m1 ds5 The singleended output voltage. ∴ vgs1 = vg1vs1 = vic . we need a different type of load so we will consider the following: VDD VDD VDD M3 vo1 M4 vo2 M2 vid 2 vo1 v1 M3 M4 vo2 v2 vo1 M3 M4 vo2 M1 vid 2 M1 M2 ISS M5 ISS 2 vic M2 M1 1 M5x 2 ISS 2 vic VBias VBias Differentialmode circuit General circuit Commonmode circuit Fig.212 SmallSignal Analysis of the CommonMode of the Differential Amplifier The commonmode gain of the differential amplifier with a current mirror load is ideally zero.2gm1rds5vgs1 + vgs1 2rds5 gm1vgs1 rds1 rds3 1 gm3 + vo1  Fig.Chapter 5 – Section 2 (2/25/03) Page 5.213 SmallSignal Analysis of the CommonMode of the Differential Amplifier – Cont’d CommonMode Analysis: Assume that rds1 is large and can be + ignored (greatly simplifies the vic analysis).E. Allen . CMOS Analog Circuit Design Chapter 5 – Section 2 (2/25/03) © P. To illustrate the commonmode gain.
4. 5. Allen . C2 = Cbd2 + Cbd4 + Cgd2 + CL and C3 = Cgd4 If C3 ≈ 0.) Multiply this resistance by the current to get the voltage at this node to ground.) Repeat this process until the output is reached.214 Frequency Response of the Differential Amplifier Back to the current mirror load differential amplifier: Cbd3 Cgd1 vid VDD Cgs3+Cgs4 M4 M3 Cgd4 Cbd1 Cbd2 M1 M5 VBias M2 Cbd4 Cgd2 + vout CL G2 G1 D1=G3=D3=G4 + vid + + i3 C3 vgs2 vgs1 1 gm1vgs1 gm3 C1 gm2vgs2 S1=S2=S3=S4 D2=D4 i3 rds2 rds4 C2 iout' + vout  Fig.Vgs2(s) s + ω where ω2 ≈ C2 ds2 ds4 2 If we further assume that gm3/C1 >> (gds2+gds4)/C2 = ω2 then the frequency response of the differential amplifier reduces to Vout(s) gm1 ω2 ≅ (A more detailed analysis will be made in Chapter 6) Vid(s) gds2 + gds4 s + ω2 CMOS Analog Circuit Design Chapter 5 – Section 2 (2/25/03) © P.2003 .) Identify the transistor(s) that convert the input voltage to current (these transistors are called transconductance transistors).2003 Page 5.E. Allen . 2.210C vo1 = (gm1vin) R1 → vout = (gm2vo1)R2 CMOS Analog Circuit Design → vout = (gm1R1gm2R2)vin © P. then we can write ω2 gm3 ggs2 + gds4 gm 1 Vout(s) ≈ g + g gm3 + sC1 Vgs1(s) . C1 = Cgd1 + Cbd1 + Cbd3 + Cgs3 + Cgs4. Cgd2 and Cgd4.) Trace the currents to where they flow into an equivalent resistance to ground. 33007 Ignore the zeros that occur due to Cgd1. Simple Example: VDD VDD M2 R1 gm1vin vin vo1 gm2vo1 M1 vout R2 Fig.Chapter 5 – Section 2 (2/25/03) Page 5. Intuitive Analysis (or Schematic Analysis) Technique: 1. 3.215 An Intuitive Method of Small Signal Analysis Small signal analysis is used so often in analog circuit design that it becomes desirable to find faster ways of performing this important analysis.E.
Allen .216 Intuitive Analysis of the CurrentMirror Load Differential Amplifier VDD M3 gm1vid gm1vid 2 2 M1 gm1vid gm2vid 2 2 + vid 2 M5 VBias M4 rout + M2 vid vout + 2 Fig.) ∴ vout = (0.) i1 = 0.E.) The resistance at the output node. is rds2rds4 or g CMOS Analog Circuit Design Chapter 5 – Section 2 (2/25/03) © P.(gm2rds1)vgs2 ⇒ vgs2 = 1+gm2rds1 gm2vin Thus. 5.) Approximate the output resistance of any cascode circuit as Rout ≈ (gm2rds2)rds1 where M1 is a transistor cascoded by M2.) i4 = i3 = 0.5gm1vid 3.211 + vid 1. 5.) If there is a resistance.217 Some Concepts to Help Extend the Intuitive Method of SmallSignal Analysis 1.2003 . iout = 1+gm2rds1 = gm2(eff) vin CMOS Analog Circuit Design © P.5gm1vid and i2 = 0.Chapter 5 – Section 2 (2/25/03) Page 5.5gm2vid 2.) i3 = i1 = 0.5gm1vid+0. Allen .5gm2vid )rout =gds2+gds4 = gds2+gds4 ⇒ vin = gds2+gds4 4.vs2 = vin .211A M2 vin VBias M1 vin rds1 vin ∴ vgs2 = vg2 .E. R.2003 Page 5. let the effective transconductance be gm gm(eff) = 1+gmR Proof: gm2(eff)vin gm2(eff)vin gm2vgs2 iout M2 vin + vgs2 rds1 Smallsignal model Fig. rout. in series with the source of the transconductance transistor. 2.5gm1vid 1 + ds2 gds4 gm1vin gm2vin vout gm1 5.
ISS IDD SR = C = C ⇒ If CL = 5pF and ISS = 10µA.219 Noise Analysis of the Differential Amplifier VDD M5 M5 VBias VBias VDD M5 en22 eeq2 en12 * M3 M1 en32 en42 M2 ito2 * M4 Vout * M1 M2 vOUT * * M3 M4 Fig. L L (For the BJT differential amplifier slewing occurs at ±100mV whereas for the MOSFET differential amplifier it can be ±2V or more.E.211C Solve for the total outputnoise current to get. gm3 2 2 2 eeq2 = en12 + en22 + g en3 + en4 m1 Thermal Noise (en12=en22 and en32=en42): 1/f Noise (en12=en22 and en32=en42): K’N BN L1 W 3 L 1 K '3 2BP 16kT 2 1/2 eeq(1/f)= fW L 1 + K’ B L eeq(th)= 3[2K' (W/L) I ]1/2 1+ L3W 1K '1 1 1 P P 3 1 1 1 CMOS Analog Circuit Design © P.218 Slew Rate of the Differential Amplifier Slew Rate (SR) = Maximum outputvoltage rate (either positive or negative) dvOUT It is caused by. ito 2 = gm12en12 + gm22en22 + gm32en32 + gm42en42 This outputnoise current can be expressed in terms of an equivalent input noise voltage. 5. 5.211B vG1  Note that slew rate can only occur when the differential input signal is large enough to cause ISS (IDD) to flow through only one of the differential input transistors.) CMOS Analog Circuit Design Chapter 5 – Section 2 (2/25/03) © P. When iOUT is a constant. given as ito2 = gm12eeq2 Equating the above two expressions for the total outputnoise current gives.2003 . Allen . iOUT = CL dt . differential amplifiers: VDD M3 iD3 iD1 + M1 vGS1 ISS M5 VBias VDD M4 iD4 iOUT iD2 + CL vOUT M5 VBias M2  vGS2 + vG2  vSG1 + M1 + iD1 vG1 M3 iD3  IDD M2 vSG2 + iD2 iOUT iD4 M4 CL + + vG 2 vOUT Fig. Consider the following currentmirror load.E. Allen .Chapter 5 – Section 2 (2/25/03) Page 5. the slew rate is SR = 2V/µs. the rate is a constant.2003 Page 5. eeq2.
Chapter 5 – Section 2 (2/25/03) Page 5.213 © P. VDD vDS1 0 0 VSD3<VSD(sat) (b. a problem occurs if I1 ≠I3 or if I2 ≠ I4.) I1>I3. • With large values of output voltage. Consider the following solution to the previous problem. Current I3 I1 Current I3 I1 0 0 VDS1<VDS(sat) (a. the upper input commonmode range is extended. VDD M3 X1 M7 IBias M6 X1 v1 v3 X1 I3 I1 M4 X1 I4 I2 X1 M2 I5 X2 Fig.212 v4 v2 M1 X1 M5 Also.) I3>I1. • The current in MC3 provides the negative feedback to drive the common mode output voltage to the desired level. CMOS Analog Circuit Design © P. VDD M3 IBias MC3 Commonmode feedback circuit MC4 IC4 MC2A v1 MC2B MC5 MB v3 M4 I3 I4 v4 Selfresistances of M1M4 v2 IC3 MC1 VCM M1 M5 M2 VSS Fig.E. Allen .214 Operation: • Common mode output voltages are sensed at the gates of MC2A and MC2B and compared to VCM. However. DifferentialInput Amplifier Probably the best way to solve the current mismatch problem is through the use of commonmode feedback.220 CurrentSource Load Differential Amplifier Gives a truly balanced differential amplifier. 5.221 CMOS Analog Circuit Design Chapter 5 – Section 2 (2/25/03) A DifferentialOutput.2003 . Allen . VDD vDS1 Fig. 5. 5.E.2003 Page 5. this common mode feedback scheme has flaws.
Continued The following circuit avoids the large differential output signal swing problems.VSG3 + VTN1 VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2 SR = ISS/CL Pdiss = (VDD+VSS)xAll dc currents flowing from VDD or to VSS vout CL ALA20 CMOS Analog Circuit Design © P. Allen .2003 . Allen .2003 Page 5.Output.E.223 Design of a CMOS Differential Amplifier with a Current Mirror Load Design Considerations: VDD Specifications Constraints Power supply Smallsignal gain M3 M4 Technology Frequency response (CL) Temperature ICMR Slew rate (CL) + vin M1 M2 Power dissipation Relationships I5 Av = gm1Rout M5 VBias ω3dB = 1/RoutCL VSS VIC(max) = VDD . CMOS Analog Circuit Design Chapter 5 – Section 2 (2/25/03) © P. 5.Input Amplifier .Chapter 5 – Section 2 (2/25/03) Page 5. Diff.222 CommonMode Stabilization of the Diff. VDD M3 IBias MC3 Commonmode feedback circuit MC4 IC4 MC2 v3 RCM1 RCM2 v1 MC5 MB M4 I3 I4 v4 Selfresistances of M1M4 v2 IC3 MC1 VCM M1 M5 M2 VSS Fig.2145 Note that RCM1 and RCM2 must not load the output of the differential amplifier.E.
5)2 = 8 gm1 W1 W 2 2·110µA/V2(W1/L1) W1 = 23. the design procedure is illustrated as shown: Procedure: 1.225 Example 5.7 W3 W4 2 ∴ L3 = L4 = (0. Pdiss M5 VSS ALA20 CMOS Analog Circuit Design Chapter 5 – Section 2 (2/25/03) © P.VSG3 + 0. VTN=0. Allen .5V≤ICMR≤2V and Pdiss ≤ 1mW. a small signal gain of 100V/V. 1. if not change ISS or modify circuit 3. with a Current Mirror Load Design the currents and W/L values of the current mirror load MOS differential amplifier to satisfy the following specifications: VDD = VSS = 2.5 . f3dB ≥ 100kHz (CL=5pF).Continued Max.) 100=gm1Rout=gds2+gds4 = L1 L1 = L2 =18.) Design W5/L5 to satisfy the lower ICMR 6.7V.) Check to see if Rout will satisfy the frequency response.Chapter 5 – Section 2 (2/25/03) Page 5.7V.4 (0. ω3dB.31 → 4.E. Solution 1. λN=0. VTP=0.) To meet the slew rate.) VIC(max) = VDD . Therefore Rout = (λN+λP)ISS ≤ 318kΩ ∴ ISS ≥ 70µA Thus. For maximum Pdiss.VSG3 + VTN1 → 2V = 2.) Pick ISS to satisfy the slew rate knowing CL or the power dissipation 2. Allen .04+0.05V1.2V = 50µA/V2(W3/L3) + 0.22 . Use the parameters of KN’=110µA/V2. SR ≥ 10V/µs (CL=5pF).) Design W1/L1 (W2/L2) to satisfy the gain 5.7 2·50µA VSG3 = 1. KP’=50µA/V2.05) 50µA CMOS Analog Circuit Design © P. 2 2.) f3dB of 100kHz implies that Rout ≤ 318kΩ. ICMR + VBias  I5 = SR·CL.2003 Page 5.5V.04V1 and λP=0.) Iterate where necessary M3 M4 vout gm1Rout + vin CL M2 M1 I5 Min.Design of a MOS Differential Amp. pick ISS = 100µA 3.E. ISS ≥ 50µA. ICMR VSG4 + VDD Schematicwise.) Design W3/L3 (W4/L4) to satisfy the upper ICMR 4.224 Design of a CMOS Differential Amplifier with a Current Mirror Load . ISS ≤ 200µA.2003 .
5 = 2. • It reduces the Miller effect when the driving source has a large source resistance.2003 Page 5.3 .31 SECTION 5.Chapter 5 – Section 2 (2/25/03) Page 5. If we choose W1/L1 = 40.3 . Allen .Continued 5. Allen .) CMOS Analog Circuit Design Chapter 5 – Section 3 (2/25/03) © P.22 . then W5/L5 = 9.7 W5 2ISS VDS5(sat) = 0.4) + 0.226 Example 5.222 = 0.CASCODE AMPLIFIER Why Use the Cascode Amplifier? • Can provide higher output resistance and larger gain if the load is also high resistance. The cascode amplifier eliminates this dominant pole by keeping the value of v1/vin small by making the value of R2 to be approximately 2/gm2.) VIC(min) = VSS +VDS5(sat)+VGS1 → 1.0777!! ⇒ L5 = KN’VDS5(sat)2 = 300 We probably should increase W1/L1 to reduce VGS1 and allow a smaller W5/L5. VDD M3 VGG3 + VGG2 RS vS + vIN  Cgd1 M2 Rs2 + vOUT Fig.E. 5. (Larger than specified gain should be okay.31 v1 M1  The Miller effect causes Cgd1 to be increased by the value of 1 + (v1/vin) and appear in parallel with the gatesource of M1 causing a dominant pole to occur. CMOS Analog Circuit Design © P.5+VDS5(sat)+ 2·50µA 110µA/V2(18.2003 .E.0.
and vIN = VDD.0V 0.0 0  1 2 vOUT 3 4 5 4 E vOUT 3 2 M3 active M3 saturated M2 saturated M2 active F 1 Fig. as 2 vDS1 iD1 = β1 (VDD .B vIN=2.2 ≈ β1(VDD .0V vIN=3.5(VGG2+VTN) where VGS1=VGS2 M2 sat. when VGG2VGS2 ≥ VGS1VT → vIN ≤ 0.5 0. Solving for vOUT by realizing that iD1 = iD2 = iD3 and β1 = β2 we get.2003 Page 5. M1 through M3. Allen .VT2)(vOUT . β3 1 1 + vOUT(min) = 2β2 (VDD − VGG3 − VT3)2 VGG2 − VT2 VDD − VT1 CMOS Analog Circuit Design © P.3 K JIH G F E 0.E.VT2)(vOUT .E.1 M3 D A.3V 5V M3 W3 2µm = L3 1µm ID M2 + W2 2µm = L2 1µm vOUT W1 2µm = L1 1µm  0. when VDS2≥VGS2VTN → vOUTVDS1≥VGG2VDS1VTN → vOUT ≥VGG2VTN M3 is saturated when VDDvOUT ≥ VDD .VGG3 .vDS1) 2 ≅ β2(VGG2 .5V vIN=1.VT1)vDS1 .vDS1) and β3 iD3 = (VDD − VGG3 − VT3)2 2 where we have also assumed that both vDS1 and vOUT are small. vOUT(min): Referencing all potentials to the negative power supply (ground in this case).vDS1 .vDS1)2 iD2 = β2 (VGG2 .Chapter 5 – Section 3 (2/25/03) Page 5.4V M1 vIN=1. Allen .5V vIN=3.VT1)vDS1 (vOUT .0V vIN=2.2003 . vOUT(max): vOUT(max) = VDD Minimum output voltage.32 G H I J K 0 0 M1 saturated M1 active 1 2v 3 IN 4 5 M1 sat.vDS1 .4 ID (mA) vIN=4. 5. we may express the current through each of the devices.0V 5 A B C D C + vIN 0.5V 2.32 LargeSignal Characteristics of the Cascode Amplifier vIN=5.2 0.33 LargeSignal Voltage Swing Limits of the Cascode Amplifier Maximum output voltage.VTP → vOUT ≤ VGG3 + VTP CMOS Analog Circuit Design Chapter 5 – Section 3 (2/25/03) © P.0V 3.5V vIN=4.
Allen . We note that simulation gives a value of about 0. 5. CMOS Analog Circuit Design Chapter 5 – Section 3 (2/25/03) © P. the calculated value is 0.Calculation of the Min. rout = [rds1 + rds2 + gm2rds1rds2]rds3 ≅ rds3 CMOS Analog Circuit Design −gm1 ≅ gds3 = − 2 K '1 W 1 L1IDλ23 © P.E. For the cascode amplifier of Fig.VSD3(sat) and the corresponding minimum output voltage is vOUT(min) = VDS1(sat) + VDS2(sat) .Chapter 5 – Section 3 (2/25/03) Page 5.) Using the previous result gives. Consequently. Allen .) Assume the values and parameters used for the cascode configuration plotted in the previous slide on the voltage transfer function and calculate the value of vOUT(min). C1 rds2 D1=S2 D2=D3 G1 + + + vin 1 v1 g v gm1vin C r C v m 2 1 2 ds 3 3 out rds1 gm2 Simplified equivalent model of the above circuit.50 volts. Output Voltage for the Cascode Amplifier (a.7V.0V and 2. (b. we can write.34 Example 5.2003 Page 5. 5.31 .75 volts. (b.) The largest output voltage for which all transistors of the cascode amplifier are in saturation is given as vOUT(max) = VDD .2003 . the range over which all transistors are saturated is quite small for a 5V power supply. If we include the influence of the channel modulation on M3 in the previous derivation.33 D1=S2 Using nodal analysis. vOUT(min) = 0. Solution (a. [gds1 + gds2 + gm2]v1 − gds2vout = −gm1vin −[gds2 + gm2]v1 + (gds2 + gds3)vout = 0 Solving for vout/vin yields vout −gm1(gds2 + gm2) = vin gds1gds2 + gds1gds3 + gds2gds3 + gds3gm2 The smallsignal output resistance is. these limits are 3.) Find the value of vOUT(max) and vOUT(min) where all transistors are in saturation. The difference is attributable to the assumption that both vDS1 and vOUT are small.32. Fig.62 volts which is closer.E.35 SmallSignal Midband Performance of the Cascode Amplifier Smallsignal model: gm2vgs2= gm2v1 G1 D2=D3 rds2 + + + vin = v1 r v ds3 out vgs1 gm1vgs1 rds1 S1=G2=G3 Smallsignal model of cascode amplifier neglecting the bulk effect on M2.
2003 . CMOS Analog Circuit Design Chapter 5 – Section 3 (2/25/03) © P. gds2+gds3 −gm1 v1 −gm1(gds2+gds3) − 2gm1 W 1L 2 = ≈ ≅ = − 2 vin gds1gds2+gds1gds3+gds2gds3+gds3gm2 gds3 gm2 gm2 L 1W 2 If the W/L ratios of M1 and M2 are equal and gds2 = gds3.gm2vs2)rds2 + i1rds3 = i1(rds2 + rds3) .gm2 rds2vs2 Solving this equation for the ratio of vs2 to i1 gives vs2 rds2 + rds3 Rs2 = i1 = 1 + gm2rds2 We see that Rs2 equals 2/gm2 if rds2 ≈ rds3.E. −(gm1 − sC1)(gds2 + gm2) Vout(s) 1 2 g + g ( g + g + g ) Vin(s) = g 1 + as + bs ds 1 ds 2 ds 3 m 2 ds 1 ds 2 where C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3) a= gds1gds2 + gds3(gm2 + gds1 + gds2) and C3(C1 + C2) b = gds1gds2 + gds3(gm2 + gds1 + gds2) CMOS Analog Circuit Design D2=D3 rds3 C3 + vout  Fig. vs2 rds2 Fig.2003 Page 5. From the previous nodal equations. and C3 = Cbd2+Cbd3+Cgd2+Cgd3+CL The nodal equations now become: (gm2 + gds1 + gds2 + sC1 + sC2)v1 − gds2vout = −(gm1 − sC1)vin and −(gds2 + gm2)v1 + (gds2 + gds3 + sC3)vout = 0 Solving for Vout(s)/Vin(s) gives.37 Frequency Response of the Cascode Amplifier Smallsignal model (RS = 0): C1 rds2 D1=S2 where G1 + + C1 = Cgd1.34 vs2 = (i1 . then v1/vin is approximately −2. 5.E.34A © P. Allen . Allen .Continued It is of interest to examine the voltage gain of v1/vin. 5.Chapter 5 – Section 3 (2/25/03) Page 5. Note that: rds3 =0 that Rs2≈1/gm2 or rds3=rds2 that Rs2≈2/gm2 or rds3≈rds2gmrds that Rs2≈rds!!! Principle: The smallsignal resistance looking into the source of a MOSFET depends on the resistance connected from the drain of the MOSFET to ac ground. Why is this gain 2 instead of 1? gm2vs2 iA R s 2 Consider the smallsignal model looking into the i1 i B source of M2: rds3 The voltage loop is written as. if gm1 ≈ gm2. Thus. vin 1 v gm2v1 gm1vin 1 rds1 gm2 C2 C2 = Cbd1+Cbs2+Cgs2.36 SmallSignal Analysis of the Cascode Amplifier . the voltage gain v1/vin ≈ 2.
Note that there is a righthalf plane zero at z1 = gm1/C1. Allen . Therefore the approximation of p2 >> p1 is valid. G3 = gds1 + gds2. CMOS Analog Circuit Design Chapter 5 – Section 3 (2/25/03) © P. [G1 + s(C1 + C2)]V1 − sC2Vout = Iin and (gm1−sC2)V1+[G3+s(C2+C3)]Vout = 0 where G1 = Gs (=1/Rs). to be decreased by a value of gm1R3. −gm1C2 −1 −1 p1 = R1(C1+C2)+R3(C2+C3)+gm1R1R3C2 ≅ gm1R1R3C2 and p2 ≅ C1C2+C1C3+C2C3 The Miller effect has caused the input pole. C2. C1 = Cgs1.Chapter 5 – Section 3 (2/25/03) Page 5. then p1 is smaller than p2. Solving for Vout(s)/Vin(s) gives (sC2−gm1)G1 Vout(s) = Vin(s) G1G3+s[G3(C1+C2)+G1(C2+C3)+gm1C2]+(C1C2+C1C3+C2C3)s2 or Vout(s) − gm 1 [1−s(C2/gm1)] = Vin(s) G3 1+[R1(C1+C2)+R3(C2+C3)+gm1R1R3C2]s+(C1C2+C1C3+C2C3)R1R3s2 Assuming that the poles are split allows the use of the previous technique to get. 1/R1C1.E.E. then P(s) can be simplified as s s2 P(s) ≈ 1 − p1 + p1p2 Therefore we may write p1 and p2 in terms of a and b as −1 −a p1 = a and p2 = b Applying this to the previous problem gives.2003 Page 5.2003 . and gm2 is greater than gds3. Rs R3 = rds1rds2 C C = Fig. CMOS Analog Circuit Design © P.38 A Simplified Method of Finding an Algebraic Expression for the Two Poles Assume that a general secondorder polynomial can be written as: 1 s s 1 s2 P(s) = 1 + as + bs2 = =1−s 1 − p1 1 − p2 p1 + p2 + p1p2 Now if p2 >> p1. Allen .The Miller Effect VDD C2 Examine the frequency M2 response of a currentsource + + Vin VGG2 vout C V V load inverter driven from a 3 C 1 R out 1 s R3 Rs gm1V1 high resistance source: M1 vin C1 ≈ Cgs1 C3 = Cbd1 + Cbd2 + Cgd2 Rs Assuming the input is Iin. −[gds1gds2 + gds3(gm2 + gds1 + gds2)] −gds3 p1 = C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3) ≈ C3 The nondominant root p2 is given as −[C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3)] −gm2 ≈ p2 = C1 + C2 C3(C1 + C2) Assuming C1.35 2 gd1 the nodal equations are. and C3 are the same order of magnitude.39 Driving Amplifiers from a High Resistance Source . 5. C2 = Cgd1 and C3 = Cbd1+Cbd2 + Cgd2.
5. then both M3 VGG3 high output resistance gm2v1 gmbs2v1 rds2 gm3v4 vout and high voltage gain is M2 D1=S2 G1 Rout achieved. CMOS Analog Circuit Design Chapter 5 – Section 3 (2/25/03) © P. Allen . Allen . R3.5 λ1λ2 λ3λ4 + 2 K '2 ( W / L ) 2 2 K '3 ( W / L ) 3 1 .2003 Page 5. the gain is simply 2 K '1 ( W / L ) 1 I D Av = −gm1rout ≅ −gm1{[gm2rds1rds2][gm3rds3rds4]} ≅ λ1λ2 λ3λ4 + 2 K '2 ( W / L ) 2 2 K '3 ( W / L ) 3 CMOS Analog Circuit Design © P. VGG2 vin M1 + + vin gm1vin v1 rds1 + gmbs3v4 rds3 D4=S3 + v4 rds4 Fig. −1 ∴ p1(cascode) = 2 2 R1(C1+C2)+ gm(C2+C3)+gm1R1 g C2 m = −1 −1 ≈ 2 R1(C1+3C2) R1(C1+C2)+ g (C2+C3)+2R1C2 m Thus we see that p1(cascode) >> p1(inverter).311 High Gain and High Output Resistance Cascode Amplifier V If the load of the cascode M4 DD D2=D3 amplifier is a cascode VGG4 current source.36 vout G2=G3=G4=S1=S4 The output resistance is. rout ≅ [gm2rds1rds2][gm3rds3rds4] = Knowing rout.Chapter 5 – Section 3 (2/25/03) Page 5. can be approximated as 2/gm of the cascoding transistor (assuming the drain sees an rds to ac ground).E.2003 ID 1.E.310 How does the Cascode Amplifier Solve the Miller Effect? The dominant pole of the inverting amplifier with a large source resistance was found to be −1 p1(inverter) = R1(C1+C2)+R3(C2+C3)+gm1R1R3C2 Now if a cascode amplifier is used.
VSD3(sat) 2I =VDD KP(W3/L3) I= K PW 3 2 2L3 (VDD .312 Example 5. 5. Allen . Allen . and CL = 1 pF. cascode amplifier and the highgain. the dominant pole. cascode amplifier has the following smallsignal performance: Av = −414V/V Rout = 1.VGG3VTP) VGG3 VDD M3 + M2 VGG2 VGG2 = VDS1(sat) + VGS2 + vIN Fig.E.Chapter 5 – Section 3 (2/25/03) Page 5.37 vOUT(min) =VDS1(sat) + VDS2(sat) 2I 2I = + KN(W1/L1) KN(W2/L2) I M1 vOUT I = Pdiss = (SR)·Cout VDD  g W1/L1) Av = g m1 = 2KN( 2 ds3 λP I CMOS Analog Circuit Design © P. output resistance. Cgs = 30 fF. and the nondominant pole for the lowgain. the drain of M2 is shorted to ground by the load capacitance. Solution The lowgain.E. Cbsn = Cbdn = 24 fF.5 fF.313 Designing Cascode Amplifiers Pertinent design equations for the simple cascode amplifier.22 MHz p2 ≈ gm2/(C1+C2) → 605 MHz. cascode amplifier has the following smallsignal performance: Av = −37. Cbsp = Cbdp = 12 fF. The highgain.40 MΩ p1 ≈ 1/RoutC3 → 108 kHz p2 ≈ gm2/(C1+C2) → 579 MHz (Note at this frequency.Comparison of the Cascode Amplifier Performance Calculate the smallsignal voltage gain. Assume that ID = 200 microamperes. cascode amplifier.2003 .1V/V Rout = 125kΩ p1 ≈ gds3/C3 → 1.2003 Page 5. CL) CMOS Analog Circuit Design Chapter 5 – Section 3 (2/25/03) © P. vOUT(max) = VDD .32 . and that the parameters of Table 3. that all W /L ratios are 2µm/1µm.12 are valid. The capacitors are assumed to be: Cgd = 3.
314 Example 5.E.05)2(150) Next.8V+ 0. we will first calculate VDS1(sat) and use the vOUT(min) specification to 2I 2·150 VDS1(sat) = = define VDS2(sat). Solution The slew rate requires a current greater than 100µA while the power dissipation requires a current less than 200µA. Beginning with M3.VTP KP(W3/L3) = 5 .2V CMOS Analog Circuit Design Chapter 5 – Section 4 (2/25/03) © P. RS >> Rin and Rout >> RL Advantages of current amplifiers: • Currents are not restricted by the power supply voltages so that wider dynamic ranges are possible with lower power supply voltages. Current Amplifier Differential input.1 50·6 = 3V W1 (Avλ)2I (50·0. KN(W1/L1) 110·4. W2 2I 2·150 ∴ L2 = KNVDS2(sat)2 = 110·0.4 . VDD=5V.2003 .8V Subtracting this value from 1.CURRENT AMPLIFIERS What is a Current Amplifier? • An amplifier that has a defined outputinput current relationship • Low input resistance • High output resistance Application of current amplifiers: ii ii Ai iS RS io iS RL RS ii + Ai io RL Fig.72 = 5. The slew rate with a 10pF load should be 10V/µs or greater. Allen .33 .7V.41 Current Amplifier Singleended input.5V gives VDS2(sat) = 0.E.2003 Page 5.5V. and Pdiss=1mW. • 3dB bandwidth of a current amplifier using negative feedback is independent of the closed loop gain.7V + 0. vOUT(max) = 4V.73 L1 = 2KN = 2·110 To design W2/L2.26 = 0.Chapter 5 – Section 3 (2/25/03) Page 5. Allen . W3 2I 2·150 L3 = KP[VDDvOUT(max)]2 = 50(1)2 = 6 2I 2·150 From this find VGG3: VGG3 = VDD . vOUT(min) = 1. Compromise with 150µA.Design of a Cascode Amplifier The specs for a cascode amplifier are Av = 50V/V.57 2I Finally. = 2.7V = 2.41 SECTION 5. VGG2 = VDS1(sat) + KN(W2/L2) + VTN = 0. CMOS Analog Circuit Design © P. 5.
R2 R2 R2Ao GB = Av(0) ω3dB = R1(1+Ao) · ωA(1+Ao) = R Ao·ωA = R GBi 1 1 where GBi is the unitygainbandwidth of the current amplifier.210 Note that GB2 > GB1 > GBi The above illustration assumes that the GB of the voltage amplifier realizing the voltage buffer is greater than the GB achieved from the above method.2003 . Allen .2003 Page 5. CMOS Analog Circuit Design © P. Illustration: R Voltage Amplifier. Allen . vin i io = Ai(i1i2) = Ai R o 1 Solving for io gives Ai vin R2 Ai → v = R i = vin io = 1+A R out 2 o R 1+ A i 1 1 i Ao If Ai(s) = s . R2 > K R2 Ao 1 dB R2 R1 1+Ao Voltage Amplifier.E.Chapter 5 – Section 4 (2/25/03) Page 5. then ωA + 1 Ao vout R2 1 R2 R2 Ao 1 = = = 1 R1 s s vin R1 R1 1+Ao ωA +(1+Ao) 1+ Ai(s) ωA(1+Ao) +1 ∴ ω3dB = ωA(1+Ao) Fig.42 Frequency Response of a Current Amplifier with Current Feedback Consider the following current amplifier with resistive i2 . then increasing R2/R1 (the voltage gain) increases GB.43 Bandwidth Advantage of a Current Feedback Amplifier The unitygainbandwidth is.42 CMOS Analog Circuit Design Chapter 5 – Section 4 (2/25/03) © P. Note that if GBi is constant.R2 negative feedback applied. 5. i R1 1 + Ai io vout Assuming that the smallsignal resistance looking into vin the current amplifier is much less than R1 or R2.E. 7. R = K >1 1 Ao dB K 1+Ao Current Amplifier Ao dB (1+Ao)ωA 0dB Magnitude dB ωA GBi GB1 GB2 log10(ω) Fig.
45 Example 5. 5. Allen . is approximately 1/gm1 and is 1 1 Rin ≈ = 46. and Cgs2 = 50fF. (R removes Cgs1 from p1) CMOS Analog Circuit Design Chapter 5 – Section 4 (2/25/03) © P.7 MHz CMOS Analog Circuit Design © P. and the 3dB frequency in Hertz for the current amplifier of Fig.9µS = 21.E. the output resistance.4x106 radians/sec. → f3dB = 28. Solution Ignoring channel modulation and mismatch effects.E. Frequency response: (gm1+gds1) (gm1+gds1) g m1 p1 = C1+C2 = Cbd1+Cgs1+Cgs2+Cgd2 ≈ Cbd1+Cgs1+Cgs2+Cgd2 Note that the bandwidth can be almost doubled by including the resistor. 5.Chapter 5 – Section 4 (2/25/03) Page 5.43 Current Amplifier 1 1 Rin = gm1 Rout = λ1Io and W 2/L 2 Ai = W 1/L 1 . Cgs1 = Cgs2 = 100fF.2003 . the smallsignal current gain. R. Rin.3kΩ 2KN(1/1)10µA The smallsignal output resistance is equal to 1 Rout = λNI2 = 250kΩ.2003 Page 5.Performance of a Simple Current Mirror as a Current Amplifier Find the smallsignal current gain. Rin. Ai. Allen .44 Current Amplifier using the Simple Current Mirror VDD VDD iin M1 I1 R I2 iout M2 iin + vin gm1vin C2 rds1 C1 gm2vin rds2 C3 iout RL ≈0 Fig. The 3dB frequency is 46. Rout.43(a) if 10I1 = I2 = 100µA and W 2/L2 = 10W1/L1 = 10µm/1µm.9µS ω3dB = 260fF = 180. 1 1 The smallsignal input resistance. W 2 /L 2 Ai = W /L ≈ 10A/A. Assume that Cbd1 = 10fF. the input resistance.41.
1V. Rout = 164. the smallsignal current gain is W 2/L 2 Ai = W 1 /L 1 = 1 Simulation results using the level 1 model for this example give Rin=1. Allen . Thus R = 1kΩ. the small signal output resistance should be Rout ≈ gm4rds4rds2 = (2001µS)(250kΩ)(250kΩ) = 125MΩ Because VDS1 = VDS2.E.2003 .7MΩ and Ai = 1. R has been designed to give a VON of 0. m1 Rout ≈ rds2gm4rds4. Cascode Current Mirror Assume that I1 and I2 of the selfbiased cascode current mirror are 100µA. 5.000 A/A.47 Example 5. CMOS Analog Circuit Design © P.5kΩ From our knowledge of the cascode configuration.44 1 Rin ≈ R + g . Allen . Find the value of Rin.Current Amplifier Implemented by the SelfBiased. Solution The input resistance requires gm1 which is 2·110·182·100 = 2mS ∴ Rin ≈ 1000Ω + 500Ω = 1.2003 Page 5. Rout.497kΩ. and W 2/L 2 Ai = W /L 1 1 CMOS Analog Circuit Design Chapter 5 – Section 4 (2/25/03) © P.46 SelfBiased Cascode Current Mirror Implementation of a Current Amplifier VDD VDD iin + I1 I2 iout + R M3 M4 vin M1 M2 vout  Current Amplifier Fig. and Ai if the W/L ratios of all transistors are 182µm/1µm.E.4 2 .Chapter 5 – Section 4 (2/25/03) Page 5.
46 i1+i2 iO = AIDiID ± AICiIC = AID(i1 . input currents of the differentialinput current amplifier.48 LowInput Resistance Current Amplifier To decrease Rin below 1/gm VDD requires the use of negative.47 CMOS Analog Circuit Design © P. iin I1 shunt feedback. Allen .2003 Page 5. Consider the following example.Chapter 5 – Section 4 (2/25/03) Page 5.(gm3 vgs3rds3) = vin(1+gm3rds3) 1 ∴ iin = gm1(1+gm3rds3)vin + gds1vin ≈ gm1gm3rds3vin ⇒ Rin ≈ gm1gm3rds3 CMOS Analog Circuit Design Chapter 5 – Section 4 (2/25/03) © P.45 M2 VGG3 Feedback concept: Input resistance without feedback ≈ rds1.) rds1 1 ∴ Rin = 1 + Loop gain ≈ g r g r = m1 ds1 m3 ds3 gm1gm3rds3 Small signal analysis: iin = gm1vgs1 . 5. 5.gds1vgs3 and vgs3 = vin vgs1 = vin .E. iID.i2) ± AIC 2 Implementations: + iO i2  VDD I i1 i2 M1 M2 i2 VDD 2I VDD iO i1i2 M5 I M3 VDD M4 iO M1 i1 VGG1 M2 i2 M6 M3 M4 VGG2 Fig.49 Current Amplifier DifferentialInput. and commonmode.2003 . iIC. i1 iIC 2 iID iIC 2 Fig. ds1 ds3 Rin(no fb.E. M3 M1 I3 VDD I2 iout iin + vin . gm1 gm3 Loop gain ≈ g g assuming that the resistances of I1 and I3 are very large. Allen .gm1vgs1 rds1 vgs3 + gm3vgs3 rds3 i=0 + vgs1 Fig. Current Amplifiers Definitions for the differentialmode. 5.
3.5 . 2.E. Allen . all feedback loops have internal poles that cause the benefits of negative feedback to vanish at high frequencies. Allen .) Avoid signal distortion.E.) Types of Output Amplifiers: 1.51 SECTION 5. and a defined outputinput current relationship • Input resistances less than 1/gm require feedback However. these feedback loops can have a slow time constant from a polezero pair. In addition.410 Summary • Current amplifiers have a low input resistance.) Provide protection from abnormal conditions (short circuit.) Pushpull amplifiers 4. high output resistance.) Source followers 3.) Class A amplifiers 2.) Provide sufficient output power in the form of voltage or current.2003 Page 5.Chapter 5 – Section 4 (2/25/03) Page 5. • Voltage amplifiers using a current amplifier have high values of gainbandwidth • Current amplifiers are useful at low power supplies and for switched current applications CMOS Analog Circuit Design Chapter 5 – Section 5 (2/25/03) © P. etc.2003 .OUTPUT AMPLIFIERS General Considerations of Output Amplifiers Requirements: 1.) Amplifiers using negative shunt feedback CMOS Analog Circuit Design © P.) Substrate BJT amplifiers 5.) Be efficient 4. over temperature.
CMOS Analog Circuit Design Chapter 5 – Section 5 (2/25/03) © P.E.) iD1 Smaller RL VDD+VSS RL Minimum RL for maximum swing IQ 0 Larger RL VSS IQ R L 0 IQ R L vDS1 VDD Fig.52 Class A Amplifiers Current source load inverter: VGG2 IQ iD1 VDD M2 iOUT VDD+VSS RL vOUT iD IQ RL dominates as the load line RL vOUT M1CL A Class A circuit has current vIN IQRL IQRL VDD VSS flow in the MOSFETs during Fig. Allen . the signal swing can be symmetrical or asymmetrical.51 VSS the entire period of a sinusoidal signal. Allen .Chapter 5 – Section 5 (2/25/03) Page 5. 04003 CMOS Analog Circuit Design © P.2003 .E.53 Optimum Value of Load Resistor Depending on the value of RL. Characteristics of Class A amplifiers: • Unsymmetrical sinking and sourcing • Linear • Poor efficiency vOUT(peak)2 vOUT(peak)2 vOUT(peak) 2RL 2RL PRL 2 Efficiency = PSupply = (VDDVSS)IQ = (VDDVSS) = V V DD SS (VDD VSS) 2RL Maximum efficiency occurs when vOUT(peak) = VDD = VSS which gives 25%. 5. (This ignores the limitations of the transistor.2003 Page 5.
E.Chapter 5 – Section 5 (2/25/03) Page 5.IQ • Maximum sourcing current is.VT1)2 . The modified smallsignal model: C1 + vin gm1vin rds1 rds2 RL C2 + vout Fig. K '2 W 2 + IOUT = 2L2 (VDD .2003 Page 5. Allen . 5.VGG2 .2003 .54 Specifying the Performance of a Class A Amplifier Output resistance: 1 1 rout = g + g = (λ +λ )I ds1 ds2 1 2 D Current: • Maximum sinking current is.55 SmallSignal Performance of the Class A Amplifier Although we have considered the smallsignal performance of the Class A amplifier as the current source load inverter.E. CMOS Analog Circuit Design Chapter 5 – Section 5 (2/25/03) © P. Allen . let us include the influence of the load. K '1 W 1 IOUT= 2L1 (VDD VSS .52 The smallsignal voltage gain is: g m 1 vout = vin gds1+gds2+GL The smallsignal frequency response includes: A zero at gm1 z = Cgd1 and a pole at (gds1+gds2+GL) p = Cgd1+Cgd2+Cbd1+Cbd2+CL CMOS Analog Circuit Design © P.VT2)2 ≤ IQ Requirements: • Want rout << RL • IOUT > CL·SR vOUT(peak) • IOUT > RL The maximum current is determined by both the current required to provide the necessary slew rate (CL) and to provide a voltage across the load resistor (RL).
Let L = 2 µm and assume that Cgd1 = 100fF.3)2 2µm and 2IOUT+ W2 2000 15µm = ≈ L2 = K ’(V V 2µm P DD GG2VTP)2 50·(2.57 Broadband Harmonic Distortion The linearity of an amplifier can be characterized by its influence on a pure sinusoidal input signal. Allen . 2(IOUT+IQ) W1 4000 3µm = = ≈ L1 KN’(VDD+VSS VTN)2 110·(5. Vin(ω) = Vp sin(ωt) The output of an amplifier with distortion will be Vout(ω) = a1Vp sin (ωt) + a2Vp sin (2ωt) +.21 V/V (includes RL = 20kΩ) and rout = 50kΩ The roots are. CL·SR = 109·106 = 1000µA iOUT(peak) = ±2V/20kΩ = ±100µA and Since the slew rate current is so much larger than the current needed to meet the voltage specification across RL. Assume VDD = VSS = 3V and VGG2 = 0V.59GHz and pole = 1/[(RLrout)CL)] ⇒ 11..Design of a Simple ClassA Output Stage Use Table 3. Assume the input is.2003 2 2 2 . zero = gm1/Cgd1 ⇒ .E. Solution Let us first consider the effects of RL and CL. THD can be expressed as [a2 + a3 +.2003 Page 5. we can safely assume that all of the current supplied by the inverter is available to charge CL. Thus.. Allen .56 Example 5.E.+ anVp sin(nωt) Harmonic distortion (HD) for the ith harmonic can be defined as the ratio of the magnitude of the ith harmonic to the magnitude of the fundamental.12 to design the W/L ratios of M1 and M2 so that a voltage swing of ±2V and a slew rate of ≅1 V/µs is achieved if RL = 20 kΩ and CL = 1000 pF.51 ...+ an]1/2 THD = a1 The distortion of the class A amplifier is good for small signals and becomes poor at maximum output swings because of the nonlinearity of the voltage transfer curve for largesignal swing CMOS Analog Circuit Design © P. Using a value of ±1 mA. secondharmonic distortion would be given as a2 HD2 = a1 Total harmonic distortion (THD) is defined as the square root of the ratio of the sum of all of the second and higher harmonics to the magnitude of the first or fundamental harmonic.Chapter 5 – Section 5 (2/25/03) Page 5.3)2 The smallsignal performance is Av = 8. For example.14kHz CMOS Analog Circuit Design Chapter 5 – Section 5 (2/25/03) © P.
VGS1 CMOS Analog Circuit Design Chapter 5 – Section 5 (2/25/03) © P.6612. γ12 γ1 γ12+ 4(VDDVSSVON1VT01) 2 vOUT’(max) ≈ 4 .2003 Page 5.5 = 0.8661V CMOS Analog Circuit Design © P. VT1 = VT01 + γ[ 2φF vBS. Allen .4V1/2. vOUT’(max)+γ1 vOUT’(max)(VDDVSS VON1VT01)=0 Solving the quadratic gives.Chapter 5 – Section 5 (2/25/03) Page 5.2V.2003 . 04001 Triode VSS+VON2 VSS Fig.7V. VTN1= 0. then vOUT’(max) = 3.59 Output Voltage Swing of the Follower The previous results do not include the bulk effect on VT1 of VGS1. 04002 Maximum output voltage swings: vOUT(min) ≈ VSS . Allen .661V and vOUT(max) = 3.E.VON2 (if RL is large) vOUT(max) = VDD . Therefore.2φF] ≈ VT01+γ vSB = VT01+γ1 vOUT(max)VSS ∴ vOUT(max)VSS ≈VDDVSSVON1VT1 = VDDVSSVON1VT01γ1 vOUT(max)VSS Define vOUT(max)VSS = vOUT’(max) which gives the quadratic. and VON1 = 0.5V.E. γN = 0.2 γ1 +4(VDDVSSVON1VT01) + 4 If VDD = 2.58 ClassA Source Follower NChannel Source Follower with current sink bias: VDD IQ vIN M1 VSS M3 VSS M2 VSS iOUT vOUT VDD Voltage transfer curve: vOUT VDD VDDVON1 Triode VDDVGS1 VSS+VON2+VGS1 VGS1 VDDVON1+VGS1 IQRL<VSS+VON2 vIN RL Fig.VON1 (if vIN > VDD) or or vOUT(min) ≈ IQRL (if RL is small) vOUT(max) ≈ VDD .
Allen . the current rapidly decreases. then VT1 = 1.11 mA.2003 . Comments: • Maximum efficiency occurs for the minimum value of RL which gives maximum swing.VT)2 and IQRL IQ vOUT vOUT iD = IQ . V 2VT VT 0 VT 2VT 3VT 4VT VDD Q L SS Plotting β iD = 2 (vIN .E.5V . CMOS Analog Circuit Design © P. Allen .E. Maximum Sinking Current: For the current sink load.08V ⇒ IOUT equal to 1. 040035 Efficiency = vOUT(peak)2 vOUT(peak)2 vOUT(peak) PRL 2RL 2RL 2 (VDDVSS) = PSupply = (VDDVSS)IQ = V V DD SS (VDD VSS) 2RL Maximum efficiency occurs when vOUT(peak) = VDD = VSS which gives 25%. as vOUT increases above 0V. thus IQ iOUT K ’1W 1 VSS vOUT IOUT(sourcing) = 2L1 [VDD − vOUT− VT1]2IQ M3 M2 where vIN is assumed to be equal to VDD.511 Efficiency of the Source Follower iD Assume that the source follower vIN I R = VSS input can swing to power supply.vOUT . IOUT(sinking) = IQ RL CMOS Analog Circuit Design Chapter 5 – Section 5 (2/25/03) © P. • Other values of RL result in less efficiency (and smaller signal swings before clipping) • We have ignored the fact that the dynamic Q point cannot travel along the full length of the load line because of minimum and maximum voltage limits.2003 Page 5. However. 04001 If W1/L1 =10 and if vOUT = 0V. the sinking current is whatever the sink is biased to provide. VSS VSS Fig.Chapter 5 – Section 5 (2/25/03) Page 5.510 Maximum Sourcing and Sinking Currents for the Source Follower Maximum Sourcing Current (into a short circuit): VDD VDD We assume that the transistors are in saturation and vIN M1 VDD = VSS = 2.R VSS VSSVT 3VT 2VT VT VT 2VT 3VT VDDVT VDD L Fig.
C1 and p ≈ . then For the current sink load follower (RL = ∞): Vout Vout = 0.Chapter 5 – Section 5 (2/25/03) Page 5. then Vin Vin = 0.Continued The output resistance is: 1 Rout = g + g m1 mbs1 + gds1 + gds2 For the current sink load follower: Rout = 830Ω The frequency response of the source follower: (gm1 + sC1) Vout(s) = Vin(s) gds1 + gds2 + gm1 + gmbs1 + GL + s(C1 + C2) where C1 = capacitances connected between the input and output ≈ CGS1 C2 = Cbs1 +Cbd2 +Cgd2(or Cgs2) + CL gm 1 gm1+GL z = . and ID = 500 µA.2003 . RL = 1000Ω: Vout Vin = 0.E.5V. Allen .513 Small Signal Performance of the Source Follower . W2/L2 = 1µm/1 µm. W1/L1 = 10µm/1 µm. if the bulk effect were ignored. CMOS Analog Circuit Design © P.869V/V.E.C1+C2 The presence of a LHP zero leads to the possibility that in most cases the pole and zero will provide some degree of cancellation leading to a broadband response.2003 Page 5.512V/V CMOS Analog Circuit Design Chapter 5 – Section 5 (2/25/03) © P. Allen .512 Small Signal Performance of the Source Follower v Smallsignal model: + gs1 + vin + + vin C1 gm1vgs1 vgs1 rds1 gmbs1vout rds2 RL C2 + vout gmbs1vbs1 rds1 rds2 RL C2 + vout  C1 gm1vin gm1vout Fig. Vout = 0V.963V/V For a finite load. 04004 gm1 gm1RL Vout gm1 = ≅ ≅ Vin gds1 + gds2 + gm1 + gmbs1+GL gm1 + gmbs1+GL 1 +gm1RL If VDD = VSS = 2.
there is quiescent current flowing in M1 and M2 for Class AB Note that there is significant distortion at vIN =0V for the Class B pushpull follower CMOS Analog Circuit Design © P. 06001 VSS VSS • Class B .514 PushPull Source Follower Can both sink and source current and provide a slightly lower output resistance. VSS Fig.each transistor has current flow for more than 180° of the sinusoid.2003 Page 5.5% • Class AB . source follower 1 1mA 2V 2 1 vout vG2 vG1 1mA iD1 0mA 2V 1V 0V 1V iD2 0 2 1 Vin(V) Class AB.one transistor has current flow for only 180° of the sinusoid (half period) vOUT(peak)2 PRL 2RL π vOUT(peak) ∴ Efficiency = P = = 2vOUT(peak) 2 VDD VSS 1 VDD (VDD VSS) πRL 2 Maximum efficiency occurs when vOUT(peak) =VDD and is 78. Allen . 06002 Comments: • Note that vOUT cannot reach the extreme values of VDD and VSS • • • IOUT+(max) and IOUT(max) is always less than VDD/RL or VSS/RL For vOUT = 0V.Chapter 5 – Section 5 (2/25/03) Page 5.E. pushpull. Maximum efficiency is between 25% and 78.2003 . Allen . source follower (RL = 1kΩ): 2V 1V 0V 1V iD2 2V 2 0 2 1 Vin(V) Class B. source follower vout vG2 1mA 0mA vG1 iD1 1mA Fig. pushpull.5% CMOS Analog Circuit Design Chapter 5 – Section 5 (2/25/03) © P.515 Illustration of Class B and Class AB PushPull. Source Follower Output current and voltage characteristics of the pushpull.E. VBias vIN VBias VDD M1 VSS iOUT vOUT VGG VSS VDD VDD M6 M5 M1 VSS iOUT vOUT VDD RL VDD RL M4 M2 Efficiency: VDD M2 Depends on how the vIN M3 transistors are biased.
06004 iOUT vOUT Comments: • The batteries VTR1 and VTR2 are necessary to control the bias current in M1 and M2. Av = 0. ID1 = ID2 = 500µA. Vout = 0V.2003 .Chapter 5 – Section 5 (2/25/03) Page 5. • The efficiency is the same as the pushpull. Common Source Amplifiers Similar to the class A but can operate as class B providing higher efficiency.787 (RL=∞) and Rout = 448Ω. CMOS Analog Circuit Design Chapter 5 – Section 5 (2/25/03) © P. source follower. z= C1 C1+C2 These roots will be highfrequency because the associated resistances are small. VDD M2 VTR2 vIN VTR1 M1CL VSS RL Fig. 06003 gmbs1vbs1 gm2vgs2 gmbs2vbs2 C1 gm1vin vout gm1 + gm2 vin = gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL 1 Rout = gds1+gds2+gm1+gmbs1+gm2+gmbs2 (does not include RL) If VDD = VSS = 2. Allen . CMOS Analog Circuit Design © P.5V. A zero and pole are located at (gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL) (gm1+gm2) p = .2003 Page 5.E. and W/L = 20µm/2µm.516 SmallSignal Performance of the PushPull Follower Model: + + vin + + vin vgs1 rds1 rds2 RL C2 + vout C1 gm1vgs1 vgs1 1 RL g gm1vout gmbs1vout rds1 gm2vin gm2vout m2 gmbs2vout rds2 C2 + vout Fig.517 PushPull.E. Allen .
06006 Comments: • Note that there is significant distortion at vIN =0V for the Class B inverter • Note that vOUT cannot reach the extreme values of VDD and VSS • IOUT+(max) and IOUT(max) is always less than VDD/RL or VSS/RL • For vOUT = 0V. inverting amplifier (RL = 1kΩ): 2V 1V 0V 1V 2V 2V 0V 1V 2V vIN Class B.Chapter 5 – Section 5 (2/25/03) Page 5. there is quiescent current flowing in M1 and M2 for Class AB CMOS Analog Circuit Design © P. pushpull. that the bias current in M6 and M8 is not dependent upon VDD or VSS (assuming VGG3 and VGG4 are not dependent on VDD and VSS). CMOS Analog Circuit Design Chapter 5 – Section 5 (2/25/03) © P.518 Practical Implementation of the PushPull.519 Illustration of Class B and Class AB PushPull.E. Common Source Amplifier VDD M5 M1 M3 vIN M2 M4 M7 VSS VGG4 M8 Fig.2003 . Fig. inverting amplifier. Note.2003 Page 5. pushpull. inverting amplifier. 1V iD2 vOUT iD1 vG2 iD1 iD2 vG1 2mA 1mA 0mA 1mA 2mA 2V 1V 0V 1V 2V 2V 1V iD2 iD1 vG2 vG1 iD1 iD2 vOUT 2mA 1mA 0mA 1mA 2mA 0V 1V 2V vIN Class AB.E. 06005 M6 VGG3 iOUT vOUT CL RL VGG3 and VGG4 can be used to bias this amplifier in class AB or class B operation. Allen . Inverting Amplifier Output current and voltage characteristics of the pushpull. Allen .
7. • If one considers the MOSFET driver. the base current.2003 .520 What about the use of BJTs? VDD M3 iB M2 CL VSS pwell CMOS VSS M3 VDD Q1 vout VDD M2 iB Q1 CL VSS nwell CMOS Fig. Providing large currents as the voltage gets to extreme values is difficult for MOSFET circuits to accomplish. the emitter can only pull to within vBE+VON of the power supply rails. We will consider the BJT as an output stage in more detail in Sec. 06007 iOUT vOUT Error Amplifier  VSS rds1rds2 Rout = 1+Loop Gain Comments: • Can achieve output resistances as low as 10Ω.1. iB. only PNP or NPN BJTs are available but not both on a standard CMOS technology. • Smallsignal output resistance is 1/gm which can easily be less than 100Ω. • If the error amplifiers are not balanced. must be large.2003 Page 5. CMOS Analog Circuit Design Chapter 5 – Section 5 (2/25/03) © P. it is difficult to control the quiescent current in M1 and M2 • Great linearity because of the strong feedback • Can be efficient if operated in class B or class AB CMOS Analog Circuit Design © P.58A vout Comments: • Can use either substrate or lateral BJTs.E.521 Use of Negative.Chapter 5 – Section 5 (2/25/03) Page 5. This value can be 1V or more. • In order for the BJT to sink (or source) large currents. Allen . • Unfortunately. 5. Shunt Feedback to Reduce the Output Resistance Concept: VDD Error Amplifier vIN M2 + + CL M1 RL Fig.E. Allen .
Shunt Feedback to Reduce the Output Resistance VDD M2 R1 vIN R2 iOUT vOUT CL M1 RL Fig. IBias = 500µA. rds1 = 50kΩ and rds2 = 40kΩ. gm1 = 3.522 Simple Implementation of Neg.ID S G D VSG M1 ID1 Q2 ID D D Fig.. gm2 = 3.511 + S S + VSG G ID NMOS Equivalent: PMOS Equivalent: K P ’W 1 K P ’W 1 2 2 I ( V V ) =(1+ β ) I =(1+ β ) ID=(1+β2)ID1=(1+β2) 2L (VSGVT) GS T D 2 D1 2 1 2L1 ∴ The composite has an enhanced KN’ ∴ The composite has an enhanced KP’ CMOS Analog Circuit Design © P.2003 Page 5. Thus. Allen .2003 .162mS.42kΩ if RL = 1kΩ) 3316+3162 = 1+0.5 25+20 CMOS Analog Circuit Design Chapter 5 – Section 5 (2/25/03) © P.22kΩ ∴ Rout = (Rout = 5.5(143.9) = 304Ω 1+0.316mS. 50kΩ40kΩ 22. 5. RL = ∞.523 QuasiComplementary Output Stages Quasicomplementary connections are used to improve the performance of the NMOS or PMOS transistor.E. Allen .E. Composite connections: D ID1 Q2 G + M1 VGS S ID G + VGS .Chapter 5 – Section 5 (2/25/03) Page 5. W1/L1 = 100µm/1µm and W2/L2 = 200µm/1µm. 06008 VSS R1 gm1+gm2 Loop gain ≈ R +R g +g +G 1 2 ds1 ds2 L rds1rds2 Rout = R1 gm1+gm2 1+ R +R g 2 ds1+gds2+GL 1 ∴ Let R1 = R2.
CMOS Analog Circuit Design © P.E.61 Closedloop gain: xo A Af = x = 1+AF s If AF >> 1.2003 .Chapter 5 – Section 5 (2/25/03) Page 5. negative feedback circuit: + xi x = either voltage or current xs A xo Σ . singleloop.524 Summary of Output Amplifiers • The objectives are to provide output power in form of voltage and/or current. • In addition. Af.E.61 SECTION 5. 5.HIGHGAIN AMPLIFIER ARCHITECTURES HighGain Amplifiers used in Negative Feedback Circuits Consider the general. Allen .6 . Allen .xf xo A = xi = highgain amplifier F = feedback network F Fig. • Low output resistance is required to provide power efficiently to a small load resistance. • Types of output amplifiers considered: Class A amplifier Source follower Class B and AB amplifier Use of BJTs Negative shunt feedback CMOS Analog Circuit Design Chapter 5 – Section 6 (2/25/03) © P. the output amplifier should be linear and be efficient. to precisely define the closedloop gain. we only need to make A large and Af becomes dependent on F which can be determined by passive elements. xo 1 Af = xs ≈ F Therefore. then. • High source/sink currents are required to provide sufficient output voltage rate due to large load capacitances.2003 Page 5.
CurrentSource (VCCS) Amplifier RS vs + vi R i Gmvi VCCS Ro io RL + vi Differential Amplifier VCCS Second Stage io Fig.E. xs. currentsource voltagesource currentsource voltagesource xi variable* Voltage Voltage Current Current xo variable Current Voltage Current Voltage Desired Ri Large Large Small Small Desired Ro Large Small Large Small * The xi .62 Types of Amplifiers The gain of an amplifier is given as xo A= x i Therefore. Allen .Chapter 5 – Section 6 (2/25/03) Page 5.62 io GmRoRi vs = GM = (Ri + RS)(Ro + RL) This amplifier is sometimes called an operational transconductance amplifier (OTA).E. controlled. controlled. Types of VoltageVoltageCurrentCurrentAmplifers controlled. Allen . and xf must all be the same type of variable. controlled. since x can be voltage or current.2003 . CMOS Analog Circuit Design Chapter 5 – Section 6 (2/25/03) © P.63 VoltageControlled. there are four types of amplifiers as summarized below. voltage or current. CMOS Analog Circuit Design © P.2003 Page 5. 5.
CMOS Analog Circuit Design Chapter 5 – Section 6 (2/25/03) © P.E.65 CurrentControlled.2003 Page 5. VoltageSource (VCVS) Amplifier RS vs + vi Ri Ro Avvi VCVS + vo RL + vi Differential Amplifier Second Stage VCVS Output Stage vo Fig. 5.6 vo AvRiRL = A = V vs (RS + Ri)(Ro + RL) This amplifier is normally called an operational amplifier.Chapter 5 – Section 6 (2/25/03) Page 5.2003 .64 VoltageControlled. Allen . 5.E. Allen . CurrentSource (CCCS) Amplifier ii is RS Ri Gmvi CCCS Ro io RL ii i1 i2 Current Differential Amplifier CCCS Fig.64 Second Stage io io AiRSRo = A = I is (RS + Ri)(Ro + RL) CMOS Analog Circuit Design © P.
6 HighGain Architectures Possible blocklevel implementations using the blocks of this chapter.E.65 Output Stage vo vo RmRSRL is = RM = (Ri + RS)(Ro + RL) CMOS Analog Circuit Design Chapter 5 – Section 7 (2/25/03) © P.Chapter 5 – Section 6 (2/25/03) Page 5. VoltageSource (CCVS) Amplifier ii is RS + vi Ri Ro Rmvi CCVS + vo RL ii i1 i2 Current Differential Amplifier Second Stage CCVS Fig.E.71 SECTION 5. 5. Allen .7 .4 Current Amplifiers Good for low power supplies 5.1 Inverting Amplifiers Class A (diode load and current sink/source load) Class AB of B (pushpull) 5.SUMMARY This chapter presented the following subjects: 5. CMOS Analog Circuit Design © P.3 Cascode Amplifiers Useful for controlling the poles of an amplifier 5.66 CurrentControlled.2 Differential Amplifiers Need good common mode rejection An excellent input stage for integrated circuit amplifiers 5.2003 .5 Output Amplifiers Minimize the output resistance Maximize the current sinking/sourcing capability 5.2003 Page 5. Allen .
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