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Chapter 6 – Introduction (2/25/03
)
Page 6.01
CHAPTER 6 – CMOS OPERATIONAL AMPLIFIERS
Chapter Outline 6.1 Design of CMOS Op Amps 6.2 Compensation of Op Amps 6.3 TwoStage Operational Amplifier Design 6.4 Power Supply Rejection Ratio of the TwoStage Op Amp 6.5 Cascode Op Amps 6.6 Simulation and Measurement of Op Amps 6.7 Macromodels for Op Amps 6.8 Summary Goal Understand the analysis, design, and measurement of simple CMOS op amps Design Hierarchy Functional blocks or circuits
Chapter 6 (Perform a complex function)
The op amps of this chapter are unbuffered and are OTAs but we will use the generic term “op amp”.
Blocks or circuits (Combination of primitives, independent)
Subblocks or subcircuits (A primitive, not independent)
Fig. 6.01
CMOS Analog Circuit Design Chapter 6 – Section 1 (2/25/03)
© P.E. Allen  2003 Page 6.11
SECTION 6.1  DESIGN OF CMOS OPERATIONAL AMPLIFIERS
HighLevel Viewpoint of an Op Amp Block diagram of a general, twostage op amp:
Compensation Circuitry
v1 v2
+ Differential Transconductance Stage
High Gain Stage
vOUT
Output vOUT' Buffer
Bias Circuitry
Fig. 11001
• Differential transconductance stage: Forms the input and sometimes provides the differentialtosingle ended conversion. • High gain stage: Provides the voltage gain required by the op amp together with the input stage. • Output buffer: Used if the op amp must drive a low resistance. • Compensation: Necessary to keep the op amp stable when resistive negative feedback is applied.
CMOS Analog Circuit Design © P.E. Allen  2003
Chapter 6 – Section 1 (2/25/03)
Page 6.12
Ideal Op Amp Symbol:
i1 + v1
+
VDD + VSS vOUT = Av(v1v2) Fig. 11002
+ v2  
+ i2 vi  
Null port: If the differential gain of the op amp is large enough then input terminal pair becomes a null port. A null port is a pair of terminals where the voltage is zero and the current is zero. I.e., v1  v2 = vi = 0 and i1 = 0 and i2 = 0 Therefore, ideal op amps can be analyzed by assuming the differential input voltage is zero and that no current flows into or out of the differential inputs.
CMOS Analog Circuit Design Chapter 6 – Section 1 (2/25/03) © P.E. Allen  2003 Page 6.13
General Configuration of the Op Amp as a Voltage Amplifier
R1 + vinn vinp + v2 v1   R2 +
+ vout Fig. 11003
Noniverting voltage amplifier: vinn = 0
⇒
R1+R2 vout = vinp R 1
Inverting voltage amplifier: vinp = 0
⇒
R2 vout =  R vinn
1
CMOS Analog Circuit Design
© P.E. Allen  2003
Chapter 6 – Section 1 (2/25/03)
Page 6.14
Example 6.11  Simplified Analysis of an Op Amp Circuit The circuit shown below is an inverting voltage amplifier using an op amp. Find the voltage transfer function, vout/vin.
R1 i1 + vin + ii vi i2 R2
+
+ vout Fig. 11004
Virtual Ground
Solution If Av → ∞, then vi → 0 because of the negative feedback path through R2. (The op amp with –fb. makes its input terminal voltages equal.) vi = 0 and ii = 0 Note that the null port becomes the familiar virtual ground if one of the op amp input terminals is on ground. If this is the case, then we can write that vin vout and i2 = R2 i1 = R1 vout R2 Since, ii = 0, then i1 + i2 = 0 giving the desired result as vin =  R1 .
CMOS Analog Circuit Design Chapter 6 – Section 1 (2/25/03) © P.E. Allen  2003 Page 6.15
Linear and Static Characterization of the Op Amp A model for a nonideal op amp that includes some of the linear, static nonidealities:
CMRR
v1
Ricm
IB2
v2 VOS v1
Ricm IB1 in2
en2
*
Cid Rid
+
Rout
vout
Ideal Op Amp
Fig. 11005
where Rid = differential input resistance Cid = differential input capacitance Ricm = common mode input resistance VOS = inputoffset voltage IB1 and IB2 = differential inputbias currents IOS = inputoffset current (IOS = IB1IB2) CMRR = commonmode rejection ratio e2 n = voltagenoise spectral density (meansquare volts/Hertz) 2 in = currentnoise spectral density (meansquare amps/Hertz)
CMOS Analog Circuit Design © P.E. Allen  2003
Allen . p2.17 Other Characteristics of the Op Amp Power supply rejection ratio (PSRR): Vo/Vin (Vdd = 0) ∆VDD PSRR = ∆VOUT Av(s) = Vo/Vdd (Vin = 0) Input common mode range (ICMR): ICMR = the voltage range over which the input commonmode signal can vary without influence the differential performance Slew rate (SR): SR = output voltage rate limit of the op amp Settling time (Ts): vOUT(t) Final Value + ε vIN Upper Tolerance ε ε Lower Tolerance + vOUT Final Value Final Value .2003 Page 6.E.ε Settling Time 0 0 Ts Fig.16 Linear and Dynamic Characteristics of the Op Amp Differential and commonmode frequency response: V (s)+V (s) 2 1 Vout(s) = Av(s)[V1(s) .Chapter 6 – Section 1 (2/25/03) Page 6. Av(jω) dB 20log10(Av0) Asymptotic Magnitude Actual Magnitude 6dB/oct.2003 . GB ω2 ω3 ω1 12dB/oct. Allen . 18dB/oct.··· are the poles of the differentialfrequency response (ignoring zeros). 0dB ω Fig. 11006 CMOS Analog Circuit Design Chapter 6 – Section 1 (2/25/03) © P. 11007 t CMOS Analog Circuit Design © P.E. p3.V2(s)] ± Ac(s) 2 Differentialfrequency response: Av0 Av0 p1p2p3··· = Av(s) = s s s (s p1)(s p2)(s p3)··· 1 1 1 ··· p p p 1 2 3 where p1.
2003 Page 6. Allen . 6.2003 .18 Classification of CMOS Op Amps Categorization of op amps: Conversion Voltage to Current Hierarchy Classic Differential Amplifier Modified Differential Amplifier Current to Voltage Differentialtosingle ended Load (Current Mirror) Source/Sink Current Loads MOS Diode Load First Voltage Stage Voltage to Current Transconductance Grounded Gate Transconductance Grounded Source Current Stage Second Voltage Stage Current to Voltage Class A (Source or Sink Load) Class B (PushPull) Table 11001 CMOS Analog Circuit Design Chapter 6 – Section 1 (2/25/03) © P.E. Allen .Chapter 6 – Section 1 (2/25/03) Page 6.E.19 TwoStage CMOS Op Amp Classical twostage CMOS op amp broken into voltagetocurrent and currenttovoltage stages: VDD M3 M4 M6 vin + vout vin + M1 M2 vout VBias M5 V→I I→ V V→I M7 VSS I→V Fig.18 CMOS Analog Circuit Design © P.
Layout of the transistors Floorplanning the connections.E. power supply buses and grounds Extraction of the physical parasitics and resimulation Verification that the layout is a physical representation of the circuit.2003 Page 6. The general performance of the circuit should be known a priori. Most of the effort of design is in this category.19 CMOS Analog Circuit Design Chapter 6 – Section 1 (2/25/03) © P. pinouts. 4. Allen . Simulators are used to aid the designer in this phase. VDD VBias M3 M10 M11 + vin M1 M2 M8 M6 VBias M7 M9 vin + vout vout VBias M4 V→ I I→ I M5 I→V VSS Fig.Chapter 6 – Section 1 (2/25/03) Page 6.) Physical implementation of the design.110 Folded Cascode CMOS Op Amp Folded cascode CMOS op amp broken into stages. 2.E. This step is results in a schematic showing the transistors and their interconnections.) Selection of the dc currents and transistor sizes.2003 .111 Design of CMOS Op Amps Steps: 1.) Choosing or creating the basic structure of the op amp.) Measurement Verification of the specifications Modification of the design as necessary CMOS Analog Circuit Design © P. then a new or modified structure must be developed. 6. This diagram does not change throughout the remainder of the design unless the specifications cannot be met. Allen .) Fabrication 5. 3.
5 V ≥ 60 dB ≥ 60 dB ≥ ±1.11 and 3. Offset 11.Chapter 6 – Section 1 (2/25/03) Page 6.12 ±2.5 V N/A. CMRR 7. Gain bandwidth 3.2003 .E. Noise 12. ICMR 6. Output resistance 10.112 Boundary Conditions and Requirements for CMOS Op Amps Boundary conditions: 1. Layout area CMOS Analog Circuit Design Chapter 6 – Section 1 (2/25/03) © P.5 V ±10% 100 µA 0 to 70°C Value ≥ 70 dB ≥ 5 MHz ≤ 1 µsec ≥ 5 V/µsec ≥ ±1.113 Specifications for a Typical Unbuffered CMOS Op Amp Boundary Conditions Process Specification Supply Voltage Supply Current Temperature Range Specifications Gain Gainbandwidth Settling Time Slew Rate Input CMR CMRR PSRR Output Swing Output Resistance Offset Noise Layout Area CMOS Analog Circuit Design Requirement See Tables 3. PSRR 8. channel length2 © P. capacitive load only ≤ ±10 mV ≤ 100nV/ Hz at 1KHz ≤ 10. Process specification (VT. etc. Operating temperature and range Requirements: 1. Cox. Supply current and range 4.000 min. Allen .E. Commonmode input range. Commonmode rejection ratio. K'. Powersupply rejection ratio.2003 Page 6. Gain 2. Allen . Settling time 4. Outputvoltage swing 9. Slew rate 5.) 2. Supply voltage and range 3.
CMOS Analog Circuit Design © P.31 SECTION 6.this step is to use hand calculations to propose a design that has potential of satisfying the specifications. inverting stage.114 Some Practical Thoughts on Op Amp Design 1. and transient performance.E.Use of a capacitor feeding back around a highgain.Chapter 6 – Section 1 (2/25/03) Page 6.2003 Page 6. Feedforward . • Miller capacitor only • Miller capacitor with an unitygain buffer to block the forward path through the compensation capacitor.this step uses the computer to refine and optimize the design. • This begins with hand calculations based upon approximate design equations.) Design dc currents and device sizes for proper dc.2 . Miller . 2. • Compensation components are also sized in this step of the procedure. Can eliminate the RHP zero. • Experience is a great help • The topology should be the one capable of meeting most of the specifications • Try to avoid “inventing” a new topology but start with an existing topology 2.) Optimization . ac.Bypassing a positive gain amplifier resulting in phase lead. • Miller with a nulling resistor.2003 .) Decide upon a suitable topology. CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P. Self compensating . Gain can be less than unity. 2. Similar to Miller but with an added series resistance to gain control over the RHP zero.COMPENSATION OF OP AMPS Compensation Objective Objective of compensation is to achieve stable operation when negative feedback is applied around the op amp. 3. a circuit simulator is used to fine tune the design Two basic steps of design: 1. Allen . • After each device is sized by hand.Load capacitor compensates the op amp (later). Design robustness is developed in this step.E. Types of Compensation 1. Allen . • Consider the load and stability requirements • Use some form of Miller compensation or a selfcompensated approach (shown later) 3.) Determine the type of compensation needed to meet the specifications.) “Firstcut” .
Fig. 12002 Frequency (rads/sec.) A measure of stability is given by the phase when A(jω)F(jω) = 1. 12001 © P. Allen .E.E.33 Illustration of the Stability Requirement using Bode Plots A(jω)F(jω) 20dB/decade 0dB ω 40dB/decade Arg[A(jω)F(jω)] 180° 135° 90° 45° 0° ΦM ω ω0dB Fig.2003 . Negative Feedback Systems F(s) Block diagram: A(s) = differentialmode voltage gain of the op amp Vin(s) A(s) + Σ F(s) = feedback transfer function from the output of op amp back to the input. negative feedback system is.2003 Page 6. This phase is called phase margin. Allen . Definitions: • Openloop gain = L(s) = A(s)F(s) Vout(s) A(s) • Closedloop gain = V (s) = 1+A(s)F(s) in Stability Requirements: The requirements for stability for a singleloop. A(jω0°)F(jω0°) = L(jω0°) < 1 where ω0° is defined as Arg[−A(jω0°)F(jω0°)] = Arg[L(jω0°)] = 0° Another convenient way to express this requirement is Arg[−A(jω0dB)F(jω0dB)] = Arg[L(jω0dB)] > 0° where ω0dB is defined as A(jω0dB)F(jω0dB) = L(jω0dB) = 1 CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) Vout(s) Fig.32 SingleLoop.Chapter 6 – Section 3 (2/25/03) Page 6. Phase margin = ΦM = Arg[A(jω0dB)F(jω0dB)] = Arg[L(jω0dB)] CMOS Analog Circuit Design © P.
C3) + g v gm1vin v1 m2 in R1 C1 2 2 D2. Allen .6 0. 12005 gm4v1 Note that this model neglects the basecollector and gatedrain capacitances for purposes of simplification. D7 (C6.4 1.2 1.E.) 15 Fig.gm6v2 D6. 12004 SmallSignal Model: D1.) Note that good stability is not necessarily the quickest risetime.E. we see that phase margin should be at least 45° and preferably 60° or larger.Chapter 6 – Section 3 (2/25/03) Page 6. D4 (C2.8 Av0 0. 1.34 Why Do We Want Good Stability? Consider the step response of secondorder system which closely models the closedloop gain of the op amp.2003 Page 6. CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P.2 0 0 5 10 ωot = ωnt (sec.0 vout(t) 0. CMOS Analog Circuit Design © P.2003 . Therefore. C4) R2 C2 + v2 . D3 (C1. Allen . C7) R3 C3 + vout Fig.4 0.35 Uncompensated Frequency Response of TwoStage Op Amps TwoStage Op Amps: VDD VCC M3 M4 M6 vout vin + Q3 Q4 Q6 vout vin + M1 M2 Q1 Q2 + VBias  M5 VSS M7 + VBias  Q5 VEE Q7 Fig. (A rule of thumb for satisfactory stability is that there should be less than three rings. 12003 60° 65° 70° + 45° 50° 55° A “good” step response is one that quickly reaches its final value.
2003 . Allen . Therefore.Chapter 6 – Section 3 (2/25/03) Page 6.gm6v2 R3 C3 + vout gm1Vin RI CI + VI .Continued For the MOS twostage op amp: 1 1 R2 = rds2 rds4 and R3 = rds6 rds7 R1 ≈ g rds3rds1 ≈ g m3 m3 C1 = Cgs3+Cgs4+Cbd1+Cbd3 C2 = Cgs6+Cbd2+Cbd4 and C3 = CL +Cbd6+Cbd7 For the BJT twostage op amp: 1 1 R1 = gm3 rπ3rπ4ro1ro3≈gm3 R2 = rπ6 ro2 ro4 ≈ rπ6 and R3 = ro6 ro7 C1 = Cπ3+Cπ4+Ccs1+Ccs3 C2 = Cπ6+Ccs2+Ccs4 and C3 = CL+Ccs6+Ccs7 Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives. the op amp must be compensated before using it in a closedloop configuration. 12007 If we assume that F(s) = 1 (this is the worst case for stability considerations).37 Uncompensated Frequency Response of an Op Amp Avd(0) dB 20dB/decade A(jω) GB 0dB Phase Shift 45°/decade 180° log10(ω) 40dB/decade Arg[A(jω)] 135° 90° 45° 0° p1' 45°/decade p2' ω0dB log10(ω) Fig. then the above plot is the same as the loop gain.2003 Page 6. 12006 The locations for the two poles are given by the following equations −1 −1 p’1 = RICI and p’2 = RIICII where RI (RII) is the resistance to ground seen from the output of the first (second) stage and CI (CII) is the capacitance to ground seen from the output of the first (second) stage. Note that the phase margin is much less than 45°.36 Uncompensated Frequency Response of TwoStage Op Amps . Allen . gm1vin R2 C2 + v2 .gmIIVI RII CII + Vout Fig.E. CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P.E. CMOS Analog Circuit Design © P.
2003 . CMOS Analog Circuit Design © P.38 Miller Compensation of the TwoStage Op Amp VDD M3 CM Cc vin + VCC M4 M6 vout CII vin + Q3 Q4 CM Cc Q6 vout CII M1 M2 CI Q1 Q2 CI + VBias  M5 VSS M7 + VBias  Q5 VEE Q7 Fig.Chapter 6 – Section 3 (2/25/03) Page 6.39 Compensated TwoStage. 12008 The various capacitors are: Cc = accomplishes the Miller compensation CM = capacitance associated with the firststage mirror (mirror pole) CI = output capacitance to ground of the firststage CII = output capacitance to ground of the secondstage CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P.E. Allen . v1 gm1vin 2 v2 gm2vin 2 Cc + vout  1 rds1rds3 CM gm3 gm4v1 C1 rds2rds4 gm6v2 rds6rds7 CL v2 + vin gm1vin CI rds2rds4 Cc CII + vout Fig.E. 12009 gm6v2 rds6rds7 Same circuit holds for the BJT op amp with different component relationships. Allen .) Assume that gm3 >> gds3 + gds1 gm 3 2. SmallSignal Frequency Response Model Simplified Use the CMOS op amp to illustrate: 1.) Assume that CM >> GB Therefore.2003 Page 6.
2. if p2>>p1 1 2 2 1 2 1 1 2 1 gmII 1 1 ∴ p1 = RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc ≈ gmIIR1RIICc . CII = C2 = CL Nodal Equations: gmIVin = [GI + s(CI + Cc)]V2 .E. Ao = gmIgmIIRIRII 1 s s 1 s2 s s2 In general. RII = rds6rds7.2003 Page 6.E. Root locus plot of the Miller compensation: Closedloop poles.) Dominant lefthalf plane pole (the Miller pole): (gds2+gds4)(gds6+gds7) 1 p1 ≈ gmIIRIRIICc = gm6Cc This root accomplishes the desired compensation.s (Cc/gmII)] = 1+s [R (C +C )+R (C +C )+g R R C ]+s2[R R (C C +C C +C C )] I I II II 2 c mII 1 II c I II I II c I c II where. Allen . CI = C1 Vin gmIVin Vout RI gmIIV2 RII CII and CI Fig.Chapter 6 – Section 3 (2/25/03) Page 6.311 CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) Summary of Results for Miller Compensation of the TwoStage Op Amp There are three roots of importance: 1.2003 . 3. D(s) = 1p 1p = 1s p + p +p p → D(s) ≈ 1p + p p .) Lefthalf plane output pole: gmII gm6 p2 ≈ CII ≈ CL This pole must be ≥ unitygainbandwidth or the phase margin will not be satisfied.sCc]V2 + [GII + sCII + sCc]Vout Solving using Cramer’s rule gives. RI = rds2rds4.) Righthalf plane zero: gmII gm6 z1= Cc = Cc This root is very undesirable. 12011 σ © P.it boosts the magnitude while decreasing the phase.sCc) = Vin(s) GIGII+s [GII(CI+CII)+GI(CII+Cc)+gmIICc]+s2[CICII+CcCI+CcCII] Ao[1 . CII > Cc > CI RIRII(CICII+CcCI+CcCII) © P. Vout(s) gmI(gmII .310 General TwoStage Frequency Response Analysis Cc where V2 + + gmI = gm1 = gm2. z = Cc p2 = [RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc] gmIICc gmII ≈ ≈ CICII+CcCI+CcCII CII . Allen . Cc≠0 jω Openloop poles Cc=0 p2 CMOS Analog Circuit Design p2' p1' p1 z1 Fig.[sCc]Vout and 0 = [gmII .12010 gmII = gm6.
12015 © P.) The lefthalf plane output pole: VDD Cc RII vout M6 CII VDD RII vout gm6 p2 ≈ CII 1 GB·Cc ≈ 0 M6 CII Fig. is GB = Avd(0)·p1 = (gmIgmIIRIRII)g CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) gmI gm1 gm2 1 = = C = C mIIRIRIICc Cc c c © P. 12013 2. where do these roots come from? 1.2003 .312 Compensated OpenLoop Frequency Response of the TwoStage Op Amp A(jω)F(jω) Avd(0) dB Uncompensated 20dB/decade Compensated GB 0dB Phase Shift Uncompensated Arg[A(jω)F(jω) log10(ω) 40dB/decade 45°/decade 45°/decade Compensated p1 No phase margin p2' p2 p1' Phase Margin log10(ω) Fig.313 Conceptually.E. GB. CMOS Analog Circuit Design VDD Cc RII vout v'' M6 v' Fig.2003 Page 6. Allen . 12014 3.) The Miller pole: 1 p1 ≈ R (g R C ) I m6 II c vI RI VDD Cc RII vout M6 ≈gm6RIICc Fig.E.Chapter 6 – Section 3 (2/25/03) Page 6. Allen .) Righthalf plane zero (One source of zeros is from multiple paths from the input to output): g m6 R 1 II sC gm6RII(1/sCc) R c II vout = RII + 1/sCc v’ + RII + 1/sCc v’’ = RII + 1/sCc v where v = v’ = v’’. 12012 180° 135° 90° 45° 0° Note that the unitygainbandwidth.
Allen . Generally. 12016 The transfer function from the input to the output voltage of the first stage.E. Allen . Avd(0) dB F=1 Cc = 0 6dB/octave Cc ≠ 0 GB 0dB Phase Shift 0° 45° 90° 135° 180° CMOS Analog Circuit Design log10(ω) Magnitude influence of C3 12dB/octave Cc ≠ 0 Cc = 0 45°/decade Cc ≠ 0 45°/decade Phase margi ignoring C3 p3z3p2 log10(ω) Fig.C 3 3 CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P. associated with the current mirror of the input stage. Vo1(s).315 Influence of the Mirror Pole – Continued Fortunately. p3. A smallsignal model for the input stage that includes C3 is shown below: gm1Vin 2 i3 1 rds1 rds3 gm3 gm2Vin 2 C3 i3 + Vo1 rds2 rds4  Fig.E. 12017 © P.2003 Page 6. In fact.2003 Cc = 0 Phase margin due to C3 p1 . the pole and zero due to C3 is greater than GB and will have very little influence on the stability of the twostage op amp. they actually increase the phase margin slightly because GB is decreased. The plot shown illustrates the case where these roots are less than GB and even then they have little effect on stability. the presence of the zero tends to negate the effect of the pole. we have neglected the influence of the pole.Chapter 6 – Section 3 (2/25/03) Page 6. can be written as sC3 + 2gm3 gm3+gds1+gds3 g m 1 g m 1 V o1(s) + 1 ≈ 2(gds2+gds4) sC + g Vin(s) = 2(gds2+gds4) 3 m3 gm3+ gds1+gds3+sC3 We see that there is a pole and a zero given as gm3 2gm3 p3 = .C and z3 = .314 Influence of the Mirror Pole Up to this point.
Allen .E.tan1p1 2 Let ω = GB and assume that z ≥ 10GB.316 Summary of the Conditions for Stability of the TwoStage Op Amp • Unitygainbandwith is given as: gmI gm1 1 1 GB = Av(0)·p1 = (gmIgmIIRIRII)· = = ( g g R R )· = g m1 m2 1 2 g Cc Cc mIIRIRIICc m2R1R2Cc • The requirement for 45° phase margin is: ω ω ω 1p  . GB GB GB . 43001 Solution of the problem: If a zero is caused by two paths to the output. Allen .818 ⇒ p2 ≥ 1.tan1 z = 45° tan ±180° . therefore we get.2gm1 > ⇒ g > 10 g and ⇒ Cc > 0. jω jω3 jω2 180° > θ1 > θ2 > θ3 θ3 θ2 θ1 jω1 z1 σ Fig.Chapter 6 – Section 3 (2/25/03) Page 6.2003 Page 6.tan1p1 p2 z GB GB 1(0.tan1 = 45° 1 tan ±180° .2003 .2GB if z ≥ 10GB • If 60° phase margin is required.the worst possible combination for stability.22C2 m 6 m 1 Cc Cc C2 > Cc CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P.E.1) = 90° + tan1p  + 5. CMOS Analog Circuit Design © P. then the following relationships apply: gm6 10gm1 gm6 2.317 Controlling the RightHalf Plane Zero Why is the RHP zero a problem? Because it boosts the magnitude but lags the phase . then eliminate one of the paths.Arg[AF] = ±180° .3° ≈ tan1 p2 = 0.7° + tan 135° ≈ tan1(Av(0)) + tan1p2 2 GB GB ⇒ 39.22GB p2 • The requirement for 60° phase margin: p2 ≥ 2.
is not neglected that another pole occurs at. Ro.E.2003 . CMOS Analog Circuit Design © P.73GB CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) VI Cc + Vout  CII Fig. is placed in series with Cc that the RHP zero can be eliminated or moved to the LHP. −1 p4 ≅ Ro[CICc/(CI + Cc)] and a LHP zero at −1 z2 ≅ RoCc Closer examination shows that if a resistor. For 45° phase margin. Model: Cc Ro +1 vOUT + Vin gmIvin CI VI RI Cc Ro Vout Ro gmIIVI RII + Vout Fig. V o(s) (gmI)(gmII)(RI)(RII) = Vin(s) 1 + s[RICI + RIICII + RICc + gmIIRIRIICc] + s2[RIRIICII(CI + Cc)] Using the technique as before to approximate p1 and p2 results in the following −1 −1 p1 ≅ RICI + RIICII + RICc + gmIIRIRIICc ≅ gmIIRIRIICc and −gmIICc p2 ≅ CII(CI + Cc) Comments: Poles are approximately what they were before with the zero removed. 43002 © P. 43003 Inverting HighGain Stage CII It can be shown that if the output resistance of the buffer amplifier. Allen .319 Use of Buffer with Finite Output Resistance to Eliminate the RHP Zero Assume that the unitygain buffer has an output resistance of Ro. p2 must be greater than 1. Allen .2003 Page 6.Chapter 6 – Section 3 (2/25/03) Page 6.E. called a nulling resistor. p2 must be greater than GB For 60° phase margin.318 Use of Buffer to Eliminate the Feedforward Path through the Miller Capacitor Model: Cc +1 The transfer + V function is given Vout CI v in gmIvin RI OUT Inverting RII HighGain gmIIVI by the following Stage equation.
then the roots of the above transfer function can be approximated as −1 −1 p1 ≅ (1 + gmIIRII)RICc ≅ gmIIRIIRICc −gmIICc −gmII p2 ≅ CICII + CcCI + CcCII ≅ CII −1 p4 = RzCI and 1 z1 = Cc(1/gmII − Rz) Note that the zero can be placed anywhere on the real axis.Continued If Rz is assumed to be less than RI or RII and the poles widely spaced. Univ.E.J. Ph. CMOS Analog Circuit Design © P. Allen .321 Use of Nulling Resistor to Eliminate the RHP . Dissertation. 1976. Santa Barbara.2003 Chapter 6 – Section 3 (2/25/03) Page 6.320 Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero)† Cc Rz VI Inverting HighGain Stage Cc Rz + Vout Fig. 43004 vOUT + Vin gmIvin  CI RI gmIIVI RII CII Nodal equations: VI sCc gmIVin + RI + sCIVI + 1 + sC R (VI − Vout) = 0 c z Vo sCc gmIIVI + RII + sCIIVout + 1 + sCcRz (Vout − VI) = 0 Solution: Vout(s) a{1 − s[(Cc/gmII) − RzCc]} Vin(s) = 1 + bs + cs2 + ds3 where a = gmIgmIIRIRII b = (CII + Cc)RII + (CI + Cc)RI + gmIIRIRIICc + RzCc c = [RIRII(CICII + CcCI + CcCII) + RzCc(RICI + RIICII)] d = RIRIIRzCICIICc † W.2003 .D..E. Allen . CMOS Analog Circuit Design © P. of CA. Parrish.Chapter 6 – Section 3 (2/25/03) Page 6. "An Ion Implanted CMOS Amplifier for High Performance Active Filters".
Setting the numerator equal to zero and assuming gm6 = gmII gives. For unitygain stability. Therefore.322 Conceptual Illustration of the Nulling Resistor Approach VDD Cc Rz RII Vout V'' M6 V' Fig. as CL changes. −gmII 1 jω = CII Cc(1/gmII − Rz) σ p z p p 1 Fig. can be written as gm6 1 gm6RII R + R g R + 1 z m6 z II sC sC R c c II V’ + V” = V Vout = 1 1 1 RII + Rz + sCc RII + Rz + sCc RII + Rz + sCc when V = V’ = V’’. 43006 1 4 2 The value of Rz can be found as Cc + CII (1/gmII) Rz = C c With p2 canceled. CMOS Analog Circuit Design © P.323 A Design Procedure that Allows the RHP Zero to Cancel the Output Pole. Unfortunately. Allen .E.E. the remaining roots are p1 and p4(the pole due to Rz) . 43005 The output voltage. Vout.Chapter 6 – Section 3 (2/25/03) Page 6. all that is required is that gmI Av(0) p4 > Av(0)p1 = gmIIRIIRICc = C c and (1/RzCI) > (gmI/Cc) = GB Substituting Rz into the above inequality and assuming CII >> Cc results in gmI Cc > gmII CICII This procedure gives excellent stability for a fixed value of CII (≈ CL). p2 We desire that z1 = p2 in terms of the previous notation. Fig. p2 changes and the zero must be readjusted to cancel p2.2003 .2003 Page 6. 1 z1 = Cc(1/gmII − Rz) CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P. Allen .
“An Improved Frequency Compensation Technique for CMOS Operational Amplifiers. p2. 6 (Dec.2003 Chapter 6 – Section 3 (2/25/03) Page 6. 1983) pp. 629633.2003 .gm6V1 Cgd6 M6 Cc + gm8 1 Vs8 . Ahuja.324 Increasing the Magnitude of the Output Pole† The magnitude of the output pole . No. VDD M11 M12 Cc M8 VBias M7 vOUT Cgd6 + Iin R1 rds8 Cc R2 C2 + Vout  + V1 Vs8 . CMOS Analog Circuit Design © P. Vol.gm8Vs8 .Chapter 6 – Section 3 (2/25/03) Page 6.gm8Vs8 The resistors R1 and R2 are defined as 1 1 R1 = g + g + g and R = 2 + g ds2 ds4 ds9 ds6 gds7 where transistors M2 and M4 are the output transistors of the first stage. sCc 1 + gm 8 g m 6 Vout Cc CcC2 C C g Iin = C c 2 m 6 c G1G2 1 + s gm8 + G2 + G2 + G1G2 + s2 gm8G2 Using the approximate method of solving for the roots of the denominator gives 1 6 p1 = Cc Cc C2 gm6Cc ≈ g r 2C m6 ds c gm8 + G2 + G2 + G1G2 and gm6rds2Cc g g r gm8rds2G2 6 m8 ds m 6 p2 ≈ = = p2’ C CcC2 6 3 2 gm8G2 where all the various channel resistance have been assumed to equal rds and p2’ is the output pole for normal Miller compensation.gm6V1 R2 C2 + Vout M10 Fig. Result: Dominant pole is approximately the same and the output pole is increased by ≈ gmrds. Allen . can be increased by introducing gain in the Miller capacitor feedback path. CMOS Analog Circuit Design © P. For example.325 Increasing the Magnitude of the Output Pole .” IEEE J.E. 6. of SolidState Circuits.Continued Solving for the transfer function Vout/Iin gives. Nodal equations: gm8sCc gm8sCc Iin = G1V1gm8Vs8 = G1V1gm8 + sCc Vout and 0 = gm6V1+ G2+sC2+ gm8+sCcVout † B. Allen .E.K. SC18.215B M9 VSS + Iin R1 V1 .
Chapter 6 – Section 3 (2/25/03) Page 6.2003 Page 6. 43008 3 3 Rout = rds7 g ≈ g g r g m6 m8rds8 m6 m8 ds8 Therefore.220) at gm6/Cgd6.326 Increasing the Magnitude of the Output Pole .327 Concept Behind the Increasing of the Magnitude of the Output Pole VDD Cc M8 M6 CII rds7 vout VDD gm8rds8 3 rds7 vout 1 GB·Cc ≈ 0 M6 CII Fig.E.216A CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P.2003 . Fig. the output pole is approximately. Allen .E. Allen .Continued In addition there is a LHP zero at gm8/sCc and a RHP zero due to Cgd6 (shown dashed in the model on Page 6. gm6gm8rds8 p2 ≈ 3CII CMOS Analog Circuit Design © P. 6. Roots are: jω σ gm6gm8rds gm8 Cc 3C2 1 gm6rdsCc gm6 Cgd6 Fig.
) Most poles are equal to the reciprocal product of the resistance from a node to ground and the capacitance connected to that node. 2.2003 . Allen .) Negative feedback: C3 C2 A R1 C1 R1 C1 C3(1+A) C2 A RootID01 b.Chapter 6 – Section 3 (2/25/03) Page 6.) Zeros arise from poles in the feedback path.) Zeros are also created by two paths VDD from the input to the output and one of more of the paths is frequency dependent.328 Identification of Poles from a Schematic 1.E. vin + − F(s) vout A(s) RootID03 s A(s) +1 p 1 Σ Vout A(s) A(s) 1 . Cc v'' RII vout M6 v' Fig.) Positive feedback (A<1): C3 C2 +A R1 C1 R1 C1 C3(1A) C2 +A RootID02 CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P. 12015 CMOS Analog Circuit Design © P. then Vin = 1+A(s)F(s) = If F(s) = s 1 =s 1+A(s) s p1 +1+ A(s) p1 +1 +1 p1 2.2003 Page 6.) Exceptions (generally due to feedback): a.E.329 Identification of Zeros from a Schematic 1. Allen .
Chapter 6 – Section 3 (2/25/03) Page 6. CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P.331 SelfCompensated Op Amps Self compensation occurs when the load capacitor is the compensation capacitor (can never be unstable for resistive feedback) dB + Gm  Rout(must be large) vout Rout CL Av(0) dB 20dB/dec.E.2003 . vin + Increasing CL 0dB ω Fig. CMOS Analog Circuit Design © P.2003 Page 6. • Placing the zero below GB will lead to boosting of the loop gain that could deteriorate the phase margin. Allen .E. RHP Zero A Vi Inverting High Gain Amplifier CII RII Vout Vi Inverting High Gain Amplifier Cc + Vi A gmIIVi CII RII + Vout Fig. 43010 Voltage gain: vout vin = Av(0) = GmRout Dominant pole: 1 p1 = RoutCL Unitygainbandwidth: Gm GB = Av(0)·p1 = C L Stability: Large load capacitors simply reduce GB but the phase is still 90° at GB. a compromise must be observed.43009 Cc LHP Zero A Cc LHP Zero using Follower Cc Vout Vi Vout +1 CII RII ACc Vout(s) s + gmII/ACc = Vin(s) Cc + CII s + 1/[RII(Cc + CII)] To use the LHP zero for compensation. Note that a source follower is a good candidate for the use of feedforward compensation. • Placing the zero above GB will have less influence on the leading phase caused by the zero.330 Feedforward Compensation Use two parallel paths to achieve a LHP zero for lead compensation purposes. Allen .
if CL is not too large and if I7 is significantly greater than I5. 6.3 . c Cc CL Therefore.333 SECTION 6. Allen .31 Notation: Wi Si = Li = W/L of the ith transistor CMOS Analog Circuit Design © P. = C if I7>>I5. 14005 SR+ = min I5 I 5 I6 I5 I7 .332 Slew Rate of a TwoStage CMOS Op Amp Remember that slew rate occurs when currents flowing in a capacitor become limited and is given as dvC Ilim = C dt where vC is the voltage across the capacitor C. then the slew rate of the twostage op amp should be.E.2003 .2003 Page 6.= min I5 I5 I7I5 .Chapter 6 – Section 3 (2/25/03) Page 6. Allen .TWOSTAGE OP AMP DESIGN Unbuffered. TwoStage CMOS Op Amp VDD M6 M3 M4 Cc vout vin + M1 M2 CL + VBias  M5 VSS M7 Fig. VDD M6 I6 ICL vout vin>>0 + VDD M6 I6=0 ICL M3 M4 C c I5 Assume a virtural ground M3 M4 C c I5 Assume a virtural ground vout M1 M2 CL I7 M7 vin<<0 + M1 M2 CL I7 M7 I5 + VBias  I5 + VBias  M5 VSS Positive Slew Rate M5 VSS Negative Slew Rate Fig. I5 SR = C c CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P. CL = Cc because I6>>I5 Cc SR.E.
vin I7 1. then I6 = S4I4 S7 S7 3. CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P. 6.E. vout Therefore.335 Design Relationships for the TwoStage Op Amp I5 Slew rate SR = Cc (Assuming I7 >>I5 and CL > Cc) gm1 2gm1 Firststage gain Av1 = gds2 + gds4 = I5(λ2 + λ4) gm6 gm6 Secondstage gain Av2 = gds6 + gds7 = I6(λ6 + λ7) gm1 Gainbandwidth GB = Cc −gm6 Output pole p2 = CL gm6 RHP zero z1 = Cc 60° phase margin requires that gm6 = 2. I6 must equal I7 ⇒ S4 = S5 5.2003 . keep all transistors in VDD saturation. This will + I5 cause “proper mirroring” in the M3M4 mirror. Allen . I5 Positive ICMR Vin(max) = VDD − β3 − VT03(max) + VT1(min)) I5 Negative ICMR Vin(min) = VSS + β1 + VT1(max) + VDS5(sat) Saturation voltageVDS(sat) = CMOS Analog Circuit Design 2IDS β (all transistors are saturated) © P. M7 + M5 VBias Also. we develop conditions to force M4 to CL M1 M2 be in saturation.) So if the balance conditions are satisfied.E. + VSG6 + VSG4 M4 is the only transistor that cannot be forced M6 into saturation by internal connections or I6 M3 M4 I4 Cc external voltages.) For balance.334 DC Balance Conditions for the TwoStage Op Amp For best performance. the gate and drain of M4 are at the same potential so that M4 is “guaranteed” to be in VSS Fig.) First assume that VSG4 = VSG6.) If VSG4 = VSG6. S6 2.2003 Page 6. I7 = S5I5 = S5 (2I4) S6 2S7 called the “balance conditions” 4.) However. then VDG4 = 0 and M4 is saturated.Chapter 6 – Section 3 (2/25/03) Page 6.2gm2(CL/Cc) if all other roots are ≥ 10GB.31A saturation. Allen .
Power dissipation. CMOS Analog Circuit Design © P. ICMR and/or p3 2. Allen . settling time (Ts). 16002 CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P. unity gain bandwidth (GB). GB VDD Vout(max) + + V 3. choose the minimum value for Cc.2003 .2CL vin M1 M2 7. Verify that the pole of M3 due to Cgs3 and Cgs4 (= 0. Output voltage swing (PM = 60°) + 8.22CL 2. Slewrate.E.e. This assumes that z ≥ 10GB. slew rate (SR). Allen . Gainbandwidth.67W3L3Cox) will not be dominant by assuming it to be greater than 10 GB gm3 2Cgs3 > 10GB. From the desired phase margin. SR CL Cc ≈ 0. Choose the smallest device length which will keep the channel modulation parameter constant and give good matching for current mirrors.Cc or I5 ≅ 10 2 . Cc > 0. for a 60° phase margin we use the following relationship. ICMR I5 = SR·Cc Vout(min) + VBias  M5 VSS M7 Fig.Chapter 6 – Section 3 (2/25/03) Page 6.E. Determine the minimum value for the “tail current” (I5) from the largest of the two values. output voltage swing (Vout(max) and Vout(min)). 1.337 Unbuffered Op Amp Design Procedure This design procedure assumes that the gain at dc (Av).Ts 3.336 Op Amp Specifications The following design procedure assumes that specifications for the following parameters are given. Gain at dc. input common mode range (Vin(min) and Vin(max)). 1. Design for S3 from the maximum input voltage specification.2003 Page 6. Av(0) Max. Load Capacitance. VDD + VSS I5 = SR . and power dissipation (Pdiss) are given. ICMR M3 M4 Proper Mirroring Cc I6 5. I5 S3 = K'3[VDD − Vin(max) − VT03(max) + VT1(min)]2 4. Pdiss I5 Min. load capacitance (CL). CL VSG4=VSG6 g GB = m1 vout Cc 6. Input commonmode range. Phase margin (or settling time) SG6 VSG4 M6 gm6 or 4. i.
Reduction of currents will probably necessitate increase of some of the W/L ratios in order to satisfy input and output swings. I5 2 I5 VDS5(sat) = Vin(min) − VSS− β1 −VT1(max) ≥ 100 mV → S5 = K'5[VDS5(sat)]2 7. gm1 = GB Cc → S2 = K'2I5 6. The previous calculations must be rechecked to insure that they are satisfied. Find S6 by letting the second pole (p2) be equal to 2. Design S7 to achieve the desired current ratios between I5 and I6.2003 . Check gain and power dissipation specifications. First calculate VDS5(sat) then find S5. then one can only reduce the currents I5 and I6. Simulate the circuit to check to see that all specifications are met. 2KP'S6I6 S6I6 S6 gm6 gm6 = = → S = gm6 = 2.2003 Page 6.Continued 5.2gm2(CL/Cc) and gm4 = 6 gm4S4 S4I4 S4 2KP'S4I4 8. S7 = (I6/I5)S5 (Check the minimum output voltage requirements) CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P. can be decreased or the W/L ratios of M2 and/or M6 increased.339 Unbuffered Op Amp Design Procedure . Design for S1 (S2) to achieve the desired GB. Allen . CMOS Analog Circuit Design © P.E. 2gm 2gm 6 Av = I5(λ2 + λ3)I6(λ6 + λ7) Pdiss = (I5 + I6)(VDD + VSS) 11. If the power dissipation is too high.338 Unbuffered Op Amp Design Procedure . Design for S5 from the minimum input voltage.Chapter 6 – Section 3 (2/25/03) Page 6. 9.2 times GB and assuming that VSG4 = VSG6. Allen . I5 and I6.E. then the currents. 12. Calculate I6 from gm 62 I6 = 2 K ' 6 S 6 Check to make sure that S6 satisfies the Vout(max) requirement and adjust as necessary. If the gain specification is not met.Continued 10. gm 22 .
35)2 = 4.79 ≈ 3. p3. VSS = 2.0 ⇒ (W/L)1 = (W/L)2 = 3 6.. I5 = (3x1012)(10x106) = 30 µA 3. 5. Cc > (2. Assume the Cox = 0. Thus. The mirror pole can be found as g m 3 . (W/L)1 is gm 12 (94. is not of concern in this design because p3 >> 10GB. 6.2 pF 2.5 CMOS Analog Circuit Design © P.25µS Therefore.E.5V Av > 3000V/V VDD = 2.5) − 110x106·3 .Design of a TwoStage Op Amp Using the material and device parameters given in Tables 3.5V GB = 5MHz SR > 10V/µs 60° phase margin Vout range = ±2V ICMR = 1 to 2V Pdiss ≤ 2mW Solution 1.Chapter 6 – Section 3 (2/25/03) Page 6.) The first step is to calculate the minimum value of the compensation capacitor Cc.) Next calculate VDS5.49 ≈ 4.4fF/µm2.2/10)(10 pF) = 2.340 Example 6.85 + 0.) The next step in the design is to calculate gm1 to get gm1 = (5x106)(2π)(3x1012) = 94.2003 .31 that meets the following specifications.85 = 0.12. 30x106 VDS5 = (−1) − (−2. to make sure that it is in fact greater than 10GB.81x109(rads/sec) or 448 MHz.2003 Page 6.E.) Now we can check the value of the mirror pole.2 K ’pS 3I3 p3 ≈ 2Cgs3 = 2(0.31 .Continued 4. p3. 30x106 → (W/L)3 = (W/L)4 = 15 (W/L)3 = (50x106)[2.25)2 (W/L)1 = (W/L)2 = 2K’NI1 = 2·110·15 = 2.667)W3L3Cox = 2.11 and 3. Allen .5 (W/L)5 = (110x106)(0.31 .) Next calculate (W/L)3 using ICMR requirements.35V Using VDS5 calculate (W/L)5 from the saturation relationship.) Choose Cc as 3pF.341 Example 6. Assume the channel length is to be 1µm and the load capacitor is CL = 10pF. Using the slewrate specification and Cc calculate I5.55]2 = 15 CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P. design an amplifier similar to that shown in Fig. 2(30x106) → (W/L)5 = 4.5 − 2 − . Allen .
At this point.5µS and knowing that gm4 = 150µS.25 ≈ 94 8.625mW. CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P.04 + . 11.342 Example 6.05) = 7.04 + . Allen .5µS Assuming that gm6 = 942. we will stay with (W/L)6 = 94 and I6 = 95µA. Therefore. ∆ W will not be taken into account.05)95x106(.5 → (W/L)7 = 14 30x106 Let us check the Vout(min) specification although the W/L of M7 is so large that this is probably not necessary. In this example ∆L will be due to lateral diffusion only. 10.E. Allen .) Finally.31 .5x106 (W/L)6 = 15 (150x106) = 94.) The final step in the hand design is to establish true electrical widths and lengths based upon ∆L and ∆W variations.343 Example 6.Chapter 6 – Section 3 (2/25/03) Page 6.2003 .25 ≈ 14 (W/L)7 = 4.) For 60° phase margin.2µm. Unless otherwise noted.) Now check to see that the gain specification has been met (92.5x106) Av = 15x106(. we have Vout(min) = VDS7(sat) = CMOS Analog Circuit Design © P.Continued 9. .697V/V which exceeds the specifications by a factor of two. With I6 = 95µA the power dissipation is Pdiss = 5V·(30µA+95µA) = 0. calculate (W/L)7 95x106 = 14.31 . The value of Vout(min) is 2·95 110·14 = 0.5x106)2 I6 = (2)(50x106)(94. the value is approximately 15.45x106)(942.) Calculate I6 using the smallsignal gm expression: (942.Continued 7. All dimensions will be rounded to integer values.An easy way to achieve more gain would be to increase the W and L values by a factor of two which because of the decreased value of λ would multiply the above gain by a factor of 20.351V which is less than required.5µA ≈ 95µA If we calculate (W/L)6 based on Vout(max). we calculate (W/L)6 as 942.E. the firstcut design is complete. Since 94 exceeds the specification and maintains better phase margin. Assume that ∆L = 0. we know that gm6 ≥ 10gm1 ≥ 942.2003 Page 6.25) = 94.
2003 .Chapter 6 – Section 3 (2/25/03) Page 6.E.0.33 CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P. 6.0.344 Example 6.4) = 8.0.4) = 2.8 µm ≈ 2µm W3 = W4 = 15(1 − 0.5µm 1µm 30µA M8 4.345 Incorporating the Nulling Resistor into the Miller Compensated TwoStage Op Amp Circuit: VDD M11 VA M10 VC IBias M3 CM vin M4 V B M8 vin+ M1 M2 Cc M6 vout CL M12 M9 M5 VSS M7 Fig.4µm ≈ 56µm W7 = 14(1 .E. The next phase requires simulation.2003 Page 6.4 ≈ 8µm The figure below shows the results of the firstcut design. 15µm 1µ m 30µA M1 vin + M3 VDD = 2.4) = 9µm W5 = 4.) CMOS Analog Circuit Design © P.4) = 1.5V M7 14µm 1µm Fig.7µm ≈ 3µm W6 = 94(1 .5V M4 15µm 1µm M6 Cc = 3pF 3µm 1µm 3µm 1µm M2 94µm 1µm vout 95µA CL = 10pF 4.31 . Allen .4) = 56. 16003 We saw earlier that the roots were: gm2 gm1 gm6 p2 = − CL p1 = − AvCc = − AvCc 1 −1 p4 = − RzCI z1 = RzCc − Cc/gm6 where Av = gm1gm6RIRII. Allen .5µm M5 1µm VSS = 2. The W/L ratios shown do not account for the lateral diffusion discussed above.Continued W1 = W2 = 3(1 − 0.5(1 . (Note that p4 is the pole resulting from the nulling resistor compensation technique.
thenVSG11 must equal VSG6. and will be set equal to 1.8 ≈ 15.5) = 2.Chapter 6 – Section 3 (2/25/03) Page 6. can be written as ∂vDS8 1 Rz = ∂iD8 = K’PS8(VSG8VTP) VDS8=0 The bias circuit is designed so that voltage VA is equal to VB. This ratio is (W/L)9 = (I10/I5)(W/L)5 = (15/30)(4. VSG10. W 11 I10 W 6 ∴ VGS10 − VT = VGS8 − VT ⇒ VSG11 = VSG6 ⇒ L =I L 11 6 6 In the saturation region 2(I10) VGS10 − VT = K'P(W10/L10) = VGS8 − VT K’PS10 1 S10 1 = ∴ Rz = K’ S S8 2I10 2K’PI10 P 8 W 8 S10S6I6 Cc Equating the two expressions for Rz gives L8 = CL + Cc I10 CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P.2003 Page 6.RHP Zero Compensation Use results of Ex. S11 = (I11/I6)S6 Choose I11 = I10 = I9 = 15µA which gives S11 = (15µA/95µA)94 = 14.2003 .347 Example 6. Therefore. and VDS9. Solution The task at hand is the design of transistors M8.25 ≈ 2 Now (W/L)8 is determined to be 3pF (W /L )8 = 3pF+10pF 1·94·95µA = 5. Rz.E. Allen . is realized by the transistor M8 which is operating in the active region because the dc current through it is zero.31.63 ≈ 6 15µA CMOS Analog Circuit Design © P.346 Design of the Nulling Resistor (M8) In order to place the zero on top of the second pole (p2). The first step in this design is to establish the bias components. and bias current I10. Allen . Therefore.32 . The aspect ratio of M10 is essentially a free parameter. In order to set VA equal to VB. 6. the following relationship must hold Cc+CL 1 CL + Cc 1 Rz = gm6 = Cc Cc 2K’PS6I6 The resistor. Rz. Use device data given in Ex. M9. M11. 6.31 and design compensation circuitry so that the RHP zero is moved from the RHP to the LHP and placed on top of the output pole p2. The ratio of I10/I5 determines the (W/L) of M9. M10.E. There must be sufficient supply voltage to support the sum of VSG11.
2003 Page 6. The results of this design are summarized below. is 942. It is equal to VSG10.5µS.5x106 The output pole. Allen .E.7 = 1. Allen . Choose I6B = 10µA to get 2KPW6BI6B Cc 2KPW6AID6 gm6ACc = gm6B = Cc + CL → L6B L6A Cc+CL or W6B 3 2 I6A W6A 3 2 95 (94) = 47.474V An Alternate Form of Nulling Resistor To cancel p2. 6. Cc = 3pF and CL = 10pF.348 Example 6.349 2I10 K’PS10 + VTP = 2·15 50·1 + 0. first calculate the value of Rz.590kΩ The location of z1 is calculated as −1 6 z1 = 3x1012 = 94.Continued It is worthwhile to check that the RHP zero has been moved on top of p2. Cc+CL 1 z1 = p2 → Rz = gm6ACC = gm6B Which gives C c gm6B = gm6ACc+CL M3 M4 M6 vout vin + VDD M11 M10 M1 M2 M6B Cc M8 M9 CL M7 Fig.34A In the previous example.E.25x106 rads/sec Thus. + M5 VBias gm6A = 942.32 . VSG8 must first be determined. which is VSG10 = Next determine Rz.590 x 103)(3x1012) − 942.63(1.Chapter 6 – Section 3 (2/25/03) Page 6. p2. To do this.5x106 p2 = 10x1012 = 94. we see that for all practical purposes. 1 106 Rz = K’PS8(VSG10VTP) = 50·5. the output pole is canceled by the zero that has been moved from the RHP to the LHP. W9 = 2 µm W10 = 1 µm W11 = 15 µm W8 = 6 µm CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P.46x10 rads/sec (4.7) = 4.474.2003 .6 → W = 6B = 48µm L6B = 13 I6B L6A 13 10 VSS CMOS Analog Circuit Design © P.
6. Allen .350 Programmability of the TwoStage Op Amp The following relationships depend on the bias current.2003 Page 6. Allen . Ibias.E.2003 .304D 100 Fig. 6. M3 1 Av(0) = gmIgmIIRIRII ∝ IBias gmI M1 GB = C ∝ IBias vin c + Pdiss = (VDD+VSS)(1+K1+K2)IBias ∝ Ibias IBias K1IBias SR = Cc ∝ IBias 1 1 Rout = 2λK2IBias ∝ IBias 103 p1 Pdiss and SR IBias2 1 102 1.5 p1 = gmIIRIRIICc ∝ I ∝ IBias Bias 101 GB and z gmII 100 z = C ∝ IBias c 101 Ao and Rout Illustration of the Ibias dependence → 102 103 1 10 IBias IBias(ref) CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) VDD M6 M4 vout M2 K2IBias K1IBias M5 VSS M7 Fig. in the following manner and allow for programmability after fabrication.351 Simulation of the Electrical Design Area of source or drain = AS = AD = W[L1 + L2 + L3] where L1 = Minimum allowable distance between the contact in the S/D and the polysilicon (5µm) L2 = Width of a minimum size contact (5µm) L3 = Minimum allowable distance from contact in S/D to edge of S/D (5µm) ∴ AS = AD = Wx15µm Perimeter of the source or drain = PD = PS = 2W + 2(L1+L2+L3) ∴ PD = PS = 2W + 30µm Illustration: L3 L2 L1 L1 L2 L3 Poly Diffusion Diffusion W L CMOS Analog Circuit Design Fig.Chapter 6 – Section 3 (2/25/03) Page 6. 16005 © P.35 © P.E.
...5 Transistor Matching . . . .... ... . . 2 1 Metal 2 Metal 1 Poly Diffusion Contacts Figure 6. .37 The layout of two transistors with a 1. . Allen . .2003 . . . .. . ..... .353 1to1. .. . . .E. . . .E. . (a) Layout which minimizes area at the sacrifice of matching. . .. . . . .36 The layout of a 5to1 current mirror. . . . .Chapter 6 – Section 3 (2/25/03) Page 6... . . . .. 2 1 .... . . . . ... . . 2 Drain 2 Gate 2 Source 2 Drain 1 Gate 1 Source 1 CMOS Analog Circuit Design © P. . Allen . .. . (b) Layout which optimizes matching.352 5to1 Current Mirror with Different Physical Performances Input Output Ground (b) Figure 6.... . . .. . . .5 to 1 matching using centroid geometry to improve matching.... . . . .. (a) Metal 1 Poly Diffusion Contacts Ground Input Output CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P. . . .. . . .2003 Page 6.
At 1 mA this amounts to a 1 mV drop which could easily be greater than the least significant bit of an analogdigital converter. For example: At 2mΩ/square.Chapter 6 – Section 3 (2/25/03) Page 6. . (For example. Resistance parasitics are minimized by using wide busses and keeping the bus length short. .2003 . .. Allen .E..354 Reduction of Parasitics The major objective of good layout is to minimize the parasitics that influence the design. Note: Can get more W/L in less area with the above geometry. a metal run of 1000µm and 2µm wide will have 1Ω of resistance. a 10 bit ADC with VREF = 1V has an LSB of 1mV) CMOS Analog Circuit Design Chapter 6 – Section 3 (2/25/03) © P. Allen .E.. . Typical parasitics include: Capacitors to ac ground Series resistance Capacitive parasitics is minimized by minimizing area and maximizing the distance between the conductor and ac ground.355 Technique for Reducing the Overlap Capacitance Square Donut Transistor: Source Gate Source Figure 6.2003 Page 6.38 Reduction of Cgd by a donut shaped transistor. . Source Drain Source Metal 1 Poly Diffusion Contacts CMOS Analog Circuit Design © P.
PSRR OF THE TWOSTAGE OP AMP What is PSRR? Av(Vdd=0) PSRR = A (V =0) dd in Vin V2 V1 + Vdd VDD Vout Vss VSS Fig. however Vdd V2 V2 V1 + VDD Vout Vss VSS V1 Av(V1V2) Vout ±AddVdd Fig.BG + M6A M5A VDD VPBias1 VPBias2 R4 R3 M11 M12 M13 M14 M15 M16 R1A Slave Bias Circuit R2A M3 M1 M4 M2 IPTAT R1 Q2 xn R2 Q3 Master Voltage Reference Circuit IREF Rext M3A M1A VNBias2 VNBias1 Q1 M2A M4A Location of reference voltage Remote portion of chip Figure 6. Allen .2003 .Chapter 6 – Section 3 (2/25/03) Page 6. CMOS Analog Circuit Design Chapter 6 – Section 4 (2/25/03) © P. 18002 Vout = AddVdd + Av(V1V2) = AddVdd .2003 Page 6.39 Generation of a reference voltage which is distributed on the chip as a current to slave bias circuits. Allen .356 Chip Voltage Bias Distribution Scheme VDD M7 M5 M8 M6 M9 M10 Bandgap Voltage.E. V .E.4 .18001 How do you calculate PSRR? You could calculate Av and Add and divide.AvVout → Vout(1+Av) = AddVdd Vout Add Add 1 ∴ V = ≈ = (Good for frequencies up to GB) dd 1+Av Av PSRR+ CMOS Analog Circuit Design © P.41 SECTION 6.
Continued Using Cramers rule to solve for the transfer function.I3 gm1Vout gm3 rds7 Vout  M7 VSS VBias gm6(V1Vdd) rds4 Vdd gds1Vdd rds2 gm1Vout + V1  Cc CI CII + Vout  rds6 rds7 Fig. Allen .2003 Page 6.E.Vout/Vdd.42 Positive PSRR of the TwoStage Op Amp Vdd M3 M4 Cc M6 Vout VDD Vdd 1 gm3 I3 rds1 gm1V5 gm6(V1Vdd) rds4 rds2 gm2V5 rds5 + V5 I3 + V1 V5 ≈ 0 Cc + CI CII rds6 M1 M2 M5 CI CII Vdd . GII = gds6 + gds7. and inverting the transfer function gives the following result. 18003 The nodal equations are: (gds1 + gds4)Vdd = (gds2 + gds4 + sCc + sCI)V1 − (gm1 + sCc)Vout (gm6 + gds6)Vdd = (gm6 − sCc)V1 + (gds6 + gds7 + sCc + sCII)Vout Using the generic notation the nodal equations are: GIVdd = (GI + sCc + sCI)V1 − (gmI + sCc)Vout (gmII + gds6)Vdd = (gmII − sCc)V1 + (GII + sCc + sCII)Vout whereGI = gds1 + gds4 = gds2 + gds4.43 Positive PSRR of the TwoStage Op Amp . Allen .2003 .Chapter 6 – Section 4 (2/25/03) Page 6. Vdd s2[CcCI+CICII + CIICc]+ s[GI(Cc+CII) + GII(Cc+CI) + Cc(gmII − gmI)] + GIGII+gmIgmII Vout = s[Cc(gmII+GI+gds6) + CI(gmII + gds6)] + GIgds6 We may solve for the approximate roots of numerator as sCc s(CcCI+CICII+CcCII) + 1 + 1 g C g g g Vdd mI mII c mI mII + PSRR = Vout ≅ GIgds6 sg C mII c + 1 G g I ds 6 where gmII > gmI and that all transconductances are larger than the channel conductances.E. s s sCc sCII + 1 + 1 + 1 + 1 g p2 g GIIAvo GB g g Vdd mI mII mI mII + ∴ PSRR = V =Gg = gds6 sGIIAvo sgmIICc out I ds6 GIgds6 + 1 + 1 g GB ds6 CMOS Analog Circuit Design © P. gmI = gm1 = gm2 and gmII = gm6 CMOS Analog Circuit Design Chapter 6 – Section 4 (2/25/03) © P.
Allen .Continued GIIAv0 gds6 PSRR+(jω) dB 0 gds6GB GIIAv0 GB p2 ω Fig.Chapter 6 – Section 4 (2/25/03) Page 6.E. 18004 At approximately the dominant pole. 18005 1.) The M7 current sink causes VSG6 to act like a battery. Conclusion: The Miller capacitor Cc couples the positive power supply ripple directly to the output. 2. Vdd couples from the source to gate of M6. Allen . 3.8dB.31 we get: PSRR+(0) = 68. z2 = 15MHz and p1 = 906Hz CMOS Analog Circuit Design Chapter 6 – Section 4 (2/25/03) © P.E. Using the values of Example 6. the PSRR falls off with a 20dB/decade slope and degrades the higher frequency PSRR + of the twostage op amp.2003 Page 6.) The path to the output is through any capacitance from gate to drain of M6. CMOS Analog Circuit Design © P.44 Positive PSRR of the TwoStage Op Amp .45 Concept of the PSRR+ for the TwoStage Op Amp Vdd Vout Vdd M3 M4 Cc M6 Vout VDD Cc Vdd Vout 0dB 1 RoutCc ω M1 M2 M5 CI CII Rout M7 VSS Other sources of PSRR+ besides Cc VBias Fig. z1 = 5MHz. Must reduce or eliminate Cc.) Therefore.2003 .
however.E.= Vout ≅ G g s ( C + C ) I m7 c I GI + 1 This equation can be rewritten approximately as sCc sCII s s + 1 +1 + 1 + 1 GB  p  g g G A Vss gmIgmII mI mII 2 II v0 PSRR.46 Negative PSRR of the TwoStage Op Amp withVBias Grounded M3 M4 Cc M6 Vout VDD Cc M1 M2 M5 VBias VBias grounded CI CII gmIVout RI CI M7 V ss gmIIV1 CII RII gm7Vss + Vout  VSS Fig. Allen . 18006 Nodal equations for VBias grounded: 0 = (GI + sCc+sCI)V1 .31 gives a gain of 23.zeros = PSRR + zeros DC gain ≈ Secondstage gain.E.pole ≈ (Secondstage gain) x (PSRR+ pole) Assuming the values of Ex.is very poor for this case. 6.2003 Page 6.7 dB and a pole 147 kHz.(gmI+sCc)Vo gm7Vss = (gMIIsCc)V1 + (GII+sCc+sCII)Vo Solving for Vout/Vss and inverting gives Vss s2[CcCI+CICII+CIICc]+s[GI(Cc+CII)+GII(Cc+CI)+Cc(gmII −gmI)]+GIGII+gmIgmII Vout = [s(Cc+CI)+GI]gm7 CMOS Analog Circuit Design Chapter 6 – Section 4 (2/25/03) © P.= Vout ≅ GIgm7 = g g sC s c m 7 mI +1 G + 1 G GB I I Comments: PSRR. The dc value of PSRR. this case can be avoided by correctly implementing VBias which we consider next. PSRR. Allen .Continued Again using techniques described previously. we may solve for the approximate roots as sCc s(CcCI+CICII+CcCII) + 1 + 1 g C g g g Vss mI mII c mI mII PSRR.47 Negative PSRR of the TwoStage Op Amp withVBias Grounded .Chapter 6 – Section 4 (2/25/03) Page 6. CMOS Analog Circuit Design © P.2003 .
= Vout ≅ G g sC s ( C + C ) I ds7 gd 7 I c +1 + 1 g GI ds7 This equation can be rewritten as s s + 1 +1 p  GB G A Vss 2 II v0 PSRR = V ≈ g sC out ds7 sCgd7 c gds7 +1 GI + 1 Comments: • DC gain has been increased by the ratio of GII to gds7 • Two poles instead of one. Allen .Chapter 6 – Section 4 (2/25/03) Page 6.48 Negative PSRR of the TwoStage Op Amp withVBias Connected to VSS M3 M4 Cc M6 Vout VDD M1 M2 M5 CI CII Vss Cc rds5 gmIVout VSS Cgd7 rds7 + Vout  VBias VBias connected to VSS M7 V ss CI RI + V1 gmIIV1  CII rds6 Fig. The nodal equations for this model are 0 = (GI + sCc + sCI)V1 . then the model shown results.7dB CMOS Analog Circuit Design and Poles at 71. however the pole at gds7/Cgd7 is large and can be ignored.49 Negative PSRR of the TwoStage Op Amp withVBias Connected to VSS .Continued Assuming that gmII > gmI and solving for the approximate roots of both the numerator and denominator gives sCc s(CcCI+CICII+CcCII) + 1 + 1 g C g g g Vss mI mII c mI mII PSRR.2003 . 18007 If the value of VBias is independent of Vss.E.31 and assume that Cds7 = 10fF. PSRR(0) = 76.2003 Page 6.(gmI + sCc)Vout and (gds7 + sCgd7)Vss = (gmII .2kHz and 149MHz © P. Allen .sCc)V1 + (GII + sCc + sCII + sCgd7)Vout Again. Using the values of Ex.E. gives. solving for Vout/Vss and inverting gives Vss s2[CcCI+CICII+CIICc+CICgd7+CcCgd7]+s[GI(Cc+CII+Cgd7)+GII(Cc+CI)+Cc(gmII−gmI)]+GIGII+gmIgmII Vout = (sCgd7+gds7)(s(CI+Cc)+GI) CMOS Analog Circuit Design Chapter 6 – Section 4 (2/25/03) © P. 6.
Invalid region of analysis GB p2 PSRR(jω) dB ω Fig..18010 © P..E. 18008 CMOS Analog Circuit Design Chapter 6 – Section 4 (2/25/03) © P.410 Frequency Response of the Negative PSRR of the TwoStage Op Amp with VBias Connected to VSS GIIAv0 gds7 0 GI Cc .Chapter 6 – Section 4 (2/25/03) Page 6.. .. .2003 Page 6.E.. Allen . 18009 Path through the input stage is not important as long as the CMRR is high. Path through the output stage: vout ≈ issZout = gm7ZoutVss Vout 1 ∴ V = gm7Zout = gm7Rout sR C +1 ss out out Vout Vss 20 to 40dB 0dB CMOS Analog Circuit Design 1 RoutCout ω Fig.411 Approximate Model for Negative PSRR with VBias Connected to Ground M3 M4 Cc M6 Vout VDD M5 or M7 VBias iss M1 M2 M5 CI CII Vss VSS VBias VBias grounded M7 V ss VSS Fig. . . Allen .2003 .
CASCODE OP AMPS Why Cascode Op Amps? • Control of the frequency behavior • Can get more gain by increasing the output resistance of a stage • In the past section. PSRR of the twostage op amp was insufficient for many applications • A twostage op amp can become unstable for large load capacitors (if nulling resistor is not used) • We will see in future sections that the cascode op amp leads to wider ICMR and/or smaller power supply requirements Where Should the Cascode Technique be Used? • First stage Good noise performance Requires level translation to second stage Degrades the Miller compensation • Second stage Self compensating Increases the efficiency of the Miller compensation Increases PSRR CMOS Analog Circuit Design © P. CMOS Analog Circuit Design Chapter 6 – Section 5 (2/25/03) © P. Allen .412 Approximate Model for Negative PSRR with VBias Connected to VSS M3 M4 Cc M6 Vout VDD rds7 CI rds7 Vss VSS vout Zout M1 M2 M5 CII Vss What is Zout? Vt Zout = I ⇒ t VBias M7 VBias connected to VSS Path through Cgd7 is negligible Fig.E. Allen .E.2003 . 18011 gmIVt It = gmIIV1 = g GI+sCI+sCc GI+s(CI+Cc) Thus.2003 Page 6. Zout = gmIgMII mII Cc CII+Cgd7 CI RI It gmIVout + V1 gmIIV1  rds6rds7 + Vout Vt Fig.Chapter 6 – Section 4 (2/25/03) Page 6.5 .51 SECTION 6.18012 rds7 1+ Vss Zout s(Cc+CI) + GI+gmIgmIIrds7 GI ∴ V = 1 = ⇒ Pole at C +C s(Cc+CI) + GI out c I The twostage op amp will never have good PSRR because of the Miller compensation.
Use the model parameters of Table 3.E.52 Use of Cascoding in the First Stage of the TwoStage Op Amp M3 VDD M4 Implementation of the floating voltage VBias.E. Cascode Op Amp Performance Assume that all W/L ratios are 10 µm/1 µm. VDD M3 MB3 MB4 M4 MC3 MC3 R MC1 M1 +v in MC4 vo1 MB5 MC4 vo1 R MC1 M1 +v in MC2 M2 VBias vin + 2 MB1 + VBias  MC2 M2 MB2 2+ VBias  2+ VBias  vin + 2  M5 VSS M5 VSS Fig.51 Rout of the first stage is RI ≈ (gmC2rdsC2rds2)(gmC4rdsC4rds4) vo1 Voltage gain = v = gm1RI [The gain is increased by approximately 0.6 µS.7µS gmC4 = 223.53MHz.2003 Page 6.2003 . respectively.53 Example 6. Find the voltage gain of this op amp and the value of CI if GB = 10 MHz. What happens if a 100pF capacitor is attached to this op amp? GB goes from 10MHz to 0. 6.4 MΩ. the value of CI is 5.28 pF. Allen . CMOS Analog Circuit Design © P. The output resistance of the NMOS and PMOS devices is 0.5 MΩ and 0.5(gMCrdsC)] in As a single stage op amp.Chapter 6 – Section 5 (2/25/03) Page 6.12. the compensation capacitor becomes the load capacitor. Allen . ∴ RI = 25 MΩ Av(0) = 8290 V/V. and that IDS1 = IDS2 = 50 µA of single stage op amp. CMOS Analog Circuit Design Chapter 6 – Section 5 (2/25/03) © P. Solution The device transconductances are gm1 = gm2 = gmI = 331.7 µS gmC2 = 331. For a unitygain bandwidth of 10 MHz.51 SingleStage.
Allen .54 TwoStage Op Amp with a Cascoded FirstStage VDD M3 MB3 MB4 M4 MT2 MC3 R MB5 MC4 vo1 M6 MT1 Cc vout MC1 M1 +v in MB1 + VBias  MC2 M2 MB2 2+ VBias  vin + 2  M5 VSS M7 Fig. is approximately the same if Cc is constant • The RHP is the same if Cc is constant CMOS Analog Circuit Design © P.E. p2. Allen . 6.Chapter 6 – Section 5 (2/25/03) Page 6.55 TwoStage Op Amp with a Cascode SecondStage VDD M6 M3 M4 VBP Cc VBN MC6 vout Rz vin + M1 M2 MC7 CL + VBias  M5 VSS M7 Fig.2003 . • The voltage gain of this op amp could easily be 100. 6. 6.E. 1 2 RI = gds2 + gds4 = (λ2 + λ4)ID5 and RII = (gmC6rdsC6rds6)(gmC7rdsC7rds7) Comments: • The secondstage gain has greatly increased improving the Miller compensation • The overall gain is approximately (gmrds)3 or very large • Output pole. • The PSRR+ is improved by the presence of MT1 p3 p2 • Internal loop pole at the gate of M6 may cause the Miller compensation to fail.000V/V CMOS Analog Circuit Design Chapter 6 – Section 5 (2/25/03) jω p1 z1 σ Fig.53 Av = gmIgmIIRIRII where gmI = gm1 = gm2. gmII = gm6.2003 Page 6.52 • MT1 and MT2 are required for level shifting from the firststage to the second.52 © P.
1. and S10 = S11 CMOS Analog Circuit Design © P. This is found from the slew rate.2003 .57 Example 6.5 V Output swing = ±1. thus we can write Max. Iout(source) = (S6/S4)I5 and Max. Iout(sink) = (S8/S3)I5 The maximum output sinking current is equal to the maximum output sourcing current if S3 = S4. The pertinent design equations for the op amp were given above. The specifications of the design are as follows: Slew rate = 5 V/µs with a 50 pF load VDD = −VSS = 2. g m 1g m 8 1 gm1gm8 gm2gm6 Iout GB = gm3CL Av = 2 + gm4 Slew rate = CL g RII m3 I5 1/2 I5 1/2 − V (max) +V (min) Vin(max) = VDD − V (min) = V + V + + VT1(min) TO3 T1 in SS DS5 β3 β1 CMOS Analog Circuit Design Chapter 6 – Section 5 (2/25/03) © P. we shall follow one based on the above specifications.Chapter 6 – Section 5 (2/25/03) Page 6. cascoded output stage op amp is a useful alternative to the twostage op amp. The steps will be numbered to help illustrate the procedure. 6. all of I5 will flow in M4.E. TABLE 1 .5 V Use the parameters of Table 3.) The first step will be to find the maximum source/sink current. Cascoded Output Stage Op Amp The balanced.) Next some W/L constraints based on the maximum output source/sink current are developed. TwoStage Op Amp using a Cascode Output Stage gm1gm8 vin VDD gm2gm6 vin vout = g + g RII m3 2 m4 2 M4 M6 M15 M3 M8 R1 M9 M10 M14 R2 M7 vout vin + M1 M2 M12 M5 + VBias  CL M11 M13 VSS Fig.56 A Balanced.2003 Page 6.E. Solution While numerous approaches can be taken. Under dynamic conditions.12 and let all device lengths be 1 µm. S6 = S8.Design Relationships for Balanced.54 g m1 gm2 = + kvin RII = gm1·k·RII vin 2 2 where RII = (gm7rds7rds6)(gm12rds12rds11) and gm8 gm6 k = gm3 = gm4 This op amp is balanced because the draintoground loads for M1 and M2 are identical. Cascode Output Stage Op Amp. Its design will be illustrated by this example. Allen . Allen .52 Design of Balanced.5 V GB = 10 MHz with a 25 pF load Av ≥ 5000 Input CMR = −1V to +1. Isource/Isink = CL × slew rate = 50 pF(5 V/µs) = 250 µA 2.
Chapter 6 – Section 5 (2/25/03) Page 6.Continued 3. This would minimize the power dissipation. First consider the negative output peak.2003 .52 . A larger value of S3 will give a higher value of Vin(max) so that we continue to use S3 = 16 which gives Vin(max) = 1. Assuming a Cox of 0. For the resistor of the selfbiased cascode we can write R1 = VDS12(sat)/250µA = 2kΩ and R2 = VSD7(sat)/250µA = 2kΩ 0.) Next the values of R1 and R2 are designed.) The first is from the Av specification.5) = 16. Since there is 1 V difference between VSS and the minimum output.) Next we find gm1 (gm2).5 V (we continue to ignore the bulk effects).E. One could redesign R1 to avoid this but the minimum output voltage under maximum sinking current would not be realized.Continued Using this value of R1 (R2) will cause M11 to slightly be in the active region under quiescent conditions. 2KP’·S6·I6 gm6 gm11 = = gm4 gm3 2KP’·S4·I4 = k CMOS Analog Circuit Design © P. Allen .15x109 rads/sec or 5.) Choose I5 as 100 µA. check to see if the larger W/L causes a pole below the gainbandwidth. 6. This current (which can be changed later) gives S6 = 2. S3 has already been designed as 16. Allen .2 and S9 = S10 = 18.5 = 2 I6 2 I7 500 µA = = K'PS6 K'PS7 (50 µA/V2)S6 which gives S6 = S7 = S8 = 40 and S3 = S4 = (40/2.275GHz which is much greater than 10GB. Using ICMR relationship.) Now we must consider the possibility of conflict among the specifications. The gain is Av = (gm1/2gm4)(gm6 + gm8) RII Note. There are two ways of calculating gm1.) Next design for ±1.2K’PS3I3 p3 = Cgs3+Cgs8 = (0. 5. Next. 7. we find that S3 should be at least 4.58 Example 6.E. We shall assume that the output must source or sink the 250µA at the peak values of output.5S3 Note that S8 could equal S3 if S11 = 2.5 = CMOS Analog Circuit Design Chapter 6 – Section 5 (2/25/03) © P.59 Example 6. First consider the input CMR.5S4 and S8 = 2.2003 Page 6.95V.2.1. 4.5 V output capability. let VDS11(sat) = VDS12(sat) = 0. a current gain of k could be introduced by making S6/S4 (S8/S3 = S11/S3) equal to k. For the positive peak. Therefore 2I11 2I12 500 µA = = (110 µA/V2)S11 K'NS11 K'NS12 which gives S11 = S12 = 18.5S10. (a. we get 0. Under the maximum negative peak assume that I11 = I12 = 250 µA.4fF/µm2 gives the firststage pole of g m 3 .667)(W3L3+W8L8)Cox = 33.52 .
52 . Assuming that the gain Av must be greater than 5000 and k = 2.) The next step is to check that S1 and S2 are large enough to meet the −1V input CMR specification. Table 2 .) The second method of finding gm1 is from the GB specifications.511 Example 6.2003 Page 6. Knowing I5 gives S1 = S2 = 5. The gain becomes Av = 6.E.Summary of W/L Ratios for Example 6. Use the saturation formula we find that VDS5 is 0.925V/V and GB = 10 MHz for a 25 pF load.510 Example 6. which can be done with the values of S5 and I5 known.7 ≈ 27. However. we choose gm1 = gm2 = 251µS.16 MΩ.Chapter 6 – Section 5 (2/25/03) Page 6. Allen .2 S13 = 34 CMOS Analog Circuit Design © P.261 V.E.) With S5 = 7 then we can design S13 from the relationship I13 125µA S13 = I S5 = 100µA 27 = 33. M5 is usually biased from a current source flowing into a MOS diode in parallel with the gatesource of M5.2003 .75 ≈ 34 5 CMOS Analog Circuit Design Chapter 6 – Section 5 (2/25/03) © P.52 S1 = S2 = 6 S3 = S4 = 16 S5 = 27 S6 = S7 = S8 = S14 = S15 = 40 S9 = S10 = S11 = S12 = 18.Continued 10. Table 2 summarizes the values of W /L that resulted from this design procedure.7 ≈ 6.52 . The value of the current source compared with I5 would define the W/L ratio of the MOS diode.4 µS. 8. Allen .43µS. and rds11 = rds12 = 0. This gives S5 = 26.5 gives gm1 > 72. (b.Continued Calculating the various transconductances we get gm4 = 282. rds6 = rd7 = 0.2 MΩ. gm11 = gm12 = 707 µS. gm6 = gm7 = gm8 = 707 µS. We shall assume that exceeding the specifications in this area is not detrimental to the performance of the op amp. The next step would be begin simulation. 9. The power dissipation for this design is seen to be 2 mW. Since this is greater than 72.) Finally we need to design the value of VBias. Multiplying the gain by the dominant pole (1/CIIRII) gives gm1(gm6 + gm8) GB = 2gm4CL Assuming that CL= 25 pF and using the specified GB gives gm1 = 251 µS.43 µS.
Poly I Poly I n+ nchannel n+ nchannel p substrate/well CMOS Analog Circuit Design Chapter 6 – Section 5 (2/25/03) . Poly I Poly II n+ If a double poly CMOS process is available.56 current source loads. + VBias  M5 vicm In order to improve the ICMR. VSS Differential amplifier with Fig.M3 Mode Range M1 VSS+VDS5+VGS1 + VSD4 M4 VBP M2 M5 vicm VSS Differential amplifier with a current mirror load. internode parasitics can be minimized.. 6. D nchannel n+ p substrate/well Fig... A A B Thin oxide B Minimum Poly separation C D .. 6.. Allen .M3 Common Mode M1 Range VSS+VDS5+VGS1 + VBias VDD VDDVSD3+VTN VDD + VSD4 M4 M2 + V Input SD3 Common . . .. it is desirable to use current source (sink) loads without losing half the gain. Allen .. CMOS Analog Circuit Design © P.2003 . .513 Input Common Mode Range for Two Types of Differential Amplifier Loads VDDVSG3+VTN + VSG3 Input .2003 Page 6. As an alternative. 6.E.55A © P. .55 C D n+ Fig. . . The resulting solution is the folded cascode op amp.Chapter 6 – Section 5 (2/25/03) Page 6... .E.512 Technological Implications of the Cascode Configuration A B Thin oxide A B C C D . one should keep the drain/source between the transistors to a minimum area..
vout.E.Chapter 6 – Section 5 (2/25/03) Page 6. Allen . 14007 rds6+R2+(1/gm10) 1 rds7 + RII RII ≈ and R = ≈ B 1 + gm7rds7 gm7rds7 where RII ≈gm9rds9rds11 gm6 1 + gm6rds6 The smallsignal voltage transfer function can be found as follows.5I3) • This amplifier is nearly balanced (would be exactly if RA was equal to RB) • Self compensating • Poor noise performance. vout g gm2 2+k m1 g R = + R = vin 2 2(1+k) out 2+2k mI out CMOS Analog Circuit Design © P. Allen . RA = gm7vgs7 RB i7 + vout  rds2 rds5 vgs7 rds7 i 10 + RII Fig.2003 Page 6.514 The Folded Cascode Op Amp VDD M14 M4 I4 M5 I5 A B RB RA I1 + vin  I2 M13 M6 I6 M7 I7 M1 M2 R1 R2 vout CL M9 M11 I3 + VBias  M8 M3 M12 M10 VSS Fig. Thus. The current i10 is written as gm1(rds1rds4)vin gm1vin i10 = 2[RA + (rds1rds4)] ≈ 2 and the current i7 can be expressed as gm2(rds2rds5)vin gm2vin gm2vin RII(gds2+gds5) i7 = RII = = where k = RII(gds2+gds5) gm7rds7 2(1+k) 2g r + (rds2rds5) 21 + g r m7 ds7 m7 ds7 The output voltage.E.e.57 Comments: • I4 and I5. the gain occurs at the output so all intermediate transistors contribute to the noise along with the input transistors. I4=I5=1.2003 . should be designed so that I6 and I7 never become zero (i. 6.515 SmallSignal Analysis of the Folded Cascode Op Amp Model: gm6vgs6 R A Recalling what we learned about the i10 g v g m 1 in m2vin resistance looking into r rds1 rds4 vgs6 ds6 1 2 2 R2+g the source of the m10 + cascode transistor. CMOS Analog Circuit Design Chapter 6 – Section 5 (2/25/03) © P. is equal to the sum of i7 and i10 flowing through Rout. (Some first stage gain can be achieved if RA and RB are greater than gm1 or gm2.
Cout. ⇒ 278Hz ⇒ GB = 1.E.gm6/CA 2. CMOS Analog Circuit Design Chapter 6 – Section 5 (2/25/03) © P.143MΩ 1 1 pout = RoutCout = 57.gm7/CB 1 3. The approximate expressions for each pole is 1. rdsP = 1MΩ.) Pole at drain of M6: p6 ≈ (R2+1/gm10)C6 4. and CL = 10pF.Chapter 6 – Section 5 (2/25/03) Page 6.) Pole at node B: pB ≈ . rdsN = 2MΩ.2003 Page 6.2 100 vout 2+1.E.2003 . However. RA = 10kΩ.750 rads/sec.156V/V Rout = RII [gm7rds7(rds5rds2)] = 400MΩ[(100)(0.516 Frequency Response of the Folded Cascode Op Amp The frequency response of the folded cascode op amp is determined primarily by the output pole which is given as 1 pout = R C out out where Cout is all the capacitance connected from the output of the op amp to ground.) Pole at gate of M10: p10 ≈ gm10/C10 where the approximate expressions are found by the reciprocal product of the resistance and parasitic capacitance seen to ground from a given node.517 Example 6.667MΩ)] = 57.53 . One might feel that because RB is approximately rds that this pole might be too small. Allen .Folded Cascode.) Pole at node A: pA ≈ . Allen .4 (100)(57.143) = 4. All other poles must be greater than GB = gm1/Cout.4x109(0. causes Rout to be much smaller making pB also nondominant.3x106) RII = 0.143MΩ·10pF = 1.) Pole at source of M8: p8 ≈ gm8/C8 5.) Pole at source of M9: p9 ≈ gm9/C9 6. and RB = 4MΩ ∴ k = = 1.2 vin = 2+2. 0. at frequencies where this pole has influence.21MHz CMOS Analog Circuit Design © P.4GΩ. Find all of the smallsignal performance values for the foldedcascode op amp. CMOS Op Amp Assume that all gmN = gmP = 100µS.
E. Allen .510A We see that the PSRR of the cascode op amp is much better than the twostage op amp.59A This model assumes that gate. We shall examine Vout/Vss rather than PSRR. 6.of the Folded Cascode Op Amp dB PSRR Avd(ω) 1 Cgd9Rout Dominant pole frequency 0dB Cgd9 Cout GB Vout Vss Other sources of Vss injection.e.Chapter 6 – Section 5 (2/25/03) Page 6. CMOS Analog Circuit Design © P.E. source and drain of M11 and the gate and source of M9 all vary with VSS. CMOS Analog Circuit Design Chapter 6 – Section 5 (2/25/03) © P.2003 . rds9 log10(ω) Fig. (Small Vout/Vss will lead to large PSRR. 6.2003 Page 6.519 Frequency Response of the PSRR.518 PSRR of the Folded Cascode Op Amp Consider the following circuit used to model the PSRR: VDD R Vss Cgd9 Cgd11 VGSG9 Vout rds9 Cgd9 M9 Vss Vss rds11 Vss VGS11 Cout Rout M11 + Vout  Vss Fig. i. Allen .is sketched on the next page.) The transfer function of Vout/Vss can be found as sCgd9Rout Vout ≈ Vss sCoutRout+1 for Cgd9 < Cout The approximate PSRR.
(I3/KN’S1) VT1 in 2I4 2 8 Maximum input S4 = S5 =K ’V V (max)+V P DD in T1 CM 9 10 Differential Voltage Gain Power dissipation gm 2 vout gm1 2+k g R = + 2(1+k)Rout = vin 2 2+2k mI out Pdiss = (VDDVSS)(I3+I12+I10+I11) © P.5V/2 or 0.53 Design of a FoldedCascode Op Amp Follow the procedure given to design the foldedcascode op amp when the slew rate is 10V/µs.5I3 output cascodes 2I7 2I5 3 Maximum output S = . the maximum and minimum output voltages are ±2V for ±2. we see that the value of 0.521 Comments Avoid zero current in cascodes VSD5(sat)=VSD7(sat) = 0. Thus. Allen . I3 = SR·CL = 10x106·1011 = 100µA Select I4 = I5 = 125µA.Chapter 6 – Section 5 (2/25/03) Page 6. vout(max) 5 KP’VSD52 7 KP’VSD72 . S9= . S10 and S11 2·I8 2·125 as S8 = S9 = S10 = S11 = K ’V 2 = 110·(0.520 Design Approach for the FoldedCascode Op Amp Step Relationship Design Equation/Constraint I = SR·C 1 Slew Rate 3 L Bias currents in I = I = 2 4 5 1. Use channel lengths of 1µm. 2·125µA 2·125·16 S4 = S5 = S14 = 50µA/V2·(0.36 N DS8 CMOS Analog Circuit Design © P.25V.2I3 to 1.25)2 = 36.2003 Page 6.5V and the maximum input common mode voltage is 2. S9.5(Vout(max)VSS) S4 and S5 must meet or exceed value in step 3 k= RII(gds2+gds4) gm7rds7 CMOS Analog Circuit Design Chapter 6 – Section 5 (2/25/03) Example 6.2003 .E.5(Vout(min)VSS) is also 0.25V)2 = 50 = 80 and assuming worst case currents in M6 and M7 gives.5V. 2·125µA 2·125·16 S6 = S7 = S13 = 50µA/V2(0. vout(min) 2 KN’VDS92 N DS11 5 Selfbias cascode R1 = VSD14(sat)/I14 and R2 = VDS8(sat)/I6 gm 1 gm12 GB2CL2 6 GB = C S = S = 1 2 K N ’I3 = K N ’I3 L 2I3 7 Minimum input S3 = 2 CM K N ’ V (min)VSS. (S4=S14=S5 & S13=S6=S7) 2I9 2I11 4 Minimum output S = . (S10=S11&S8=S9) 11 K ’V voltage.000V/V and the power dissipation should be less than 5mW. Solution Following the approach outlined above we obtain the following results. Next. the minimum input common mode voltage is 1.25V)2 = 50 = 80 The value of 0. The differential voltage gain should be greater than 5.25V which gives the value of S8.E. the load capacitor is 10pF. the GB is 10MHz.5V power supplies. Allen . S = voltage.5[VDDVout(max)] VDS9(sat)=VDS11(sat) = 0.5(VDDVout(max)) is 0.
05 = 6.25µS RII(gds2+gds4) 86. S7: S1. S9. Allen .5+2.Continued The value of R1 and R2 is equal to 0. S14: S6.9 N 3 The minimum input common mode voltage defines S3 as 2 I3 200x106 S3 = = = 91.25µS and gds = 75x106·0.6µS and gds = 75x106·0. The maximum input common mode voltage of 2.07MΩ RII ≈ gm9rds9rds11 = (774. In step 6.E.VT1 110·35.40x106 = 7.Continued The smallsignal voltage gain requires the following values to evaluate: S4.4375 774. the value of GB gives S1 and S2 as GB2·CL2 (20πx106)2(1011)2 S1 = S2 = K ’I = 110x106·100x106 = 35.25V/125µA or 2kΩ.7 KN’Vin(min)VSS. Allen .04 = 3µS gm = 2·75·50·80 = 774.04) = 2µS 1 1 = 86. differentialinput. S13.53 The power dissipation is found to be Pdiss = 5V(125µA+125µA+125µA) = 1.75µS 2µS+6.2003 .07MΩ(774. voltage gain is 2+k 2+3.6 I3 100 2 2 110x106 1. In fact.Chapter 6 – Section 5 (2/25/03) Page 6.7V]2 = 10.464 V/V = Avd = 2+2k mI out 2+6. Finally. S12.36 = 774.05 = 3. is given as 125 S12 = 100 S3 = 114.53 .75µS gm = 2·75·110·36. S2: Thus.K ’S .6µS gm7rds7 The smallsignal.6µS)3.25µS)(3.E.2003 Page 6.523 Example 6. S11: gm = 2·125·50·80 = 1000µS and gds = 125x106·0.5 0.875mW CMOS Analog Circuit Design Chapter 6 – Section 5 (2/25/03) © P.53 .4375 g R 0. with S4 = S5 = 80.5 requires 2 I4 2·125µA S4 = S5 ≥ K ’[V V (max)+V ]2 = 6 50x10 µA/V2[0.75µS) = = 3.2 P DD in T1 which is much less than 80.6µS gmI = 2·50·110·35.6µS)3µS 3µS 1 1 = 19. S5.40MΩ Rout ≈ 86. k= CMOS Analog Circuit Design © P.522 Example 6.07MΩ(2µS+6.875 The gain is larger than required by the specifications which should be okay.9 = 628µS and gds = 50x106(0.9 N 1 We need to check that the values of S4 and S5 are large enough to satisfy the maximum input common mode voltage. S8. S10. the maximum input common mode voltage is 3V.628x103·19.
• The objective of measurement is to experimentally confirm the specifications.6 .Chapter 6 – Section 5 (2/25/03) Page 6.SIMULATION AND MEASUREMENT OF OP AMPS Simulation and Measurement Considerations Objectives: • The objective of simulation is to verify and optimize the design.2003 Page 6.61 SECTION 6. Allen . Allen .E. Similarity Between Simulation and Measurement: • Same goals • Same approach or technique Differences Between Simulation and Measurement: • Simulation can idealize a circuit • Measurement must consider all nonidealities CMOS Analog Circuit Design © P.524 Comments on Folded Cascode Op Amps • Good PSRR • Good ICMR • Self compensated • Can cascade an output stage to get extremely high gain with lower output resistance (use Miller compensation in this case) • Need first stage gain for good noise performance • Widely used in telecommunication circuits where large dynamic range is required CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03) © P.2003 .E.
power dissipation 6.62 Simulating or Measuring the OpenLoop Transfer Function of the Op Amp Circuit (Darkened op amp identifies the op amp under test): VOS vIN + VDD vOUT Simulation: RL This circuit will give the voltage transfer CL VSS function curve.) The gain in the linear range 3.) From the openloop frequency response. This curve should identify: Fig. Allen .) DC operating conditions. CMOS Analog Circuit Design © P.Chapter 6 – Section 6 (2/25/03) Page 6. the phase margin can be obtained (F = 1) Measurement: This circuit probably will not work unless the op amp gain is very low.) The output limits 4. 24003 Make the RC product as large as possible.E.) When biased in the linear range. 24002 Resulting ClosedLoop Frequency Response: dB Av(0) Op Amp Open Loop Frequency Response 0dB 1 RC Av(0) RC log10(w) Fig. the smallsignal frequency response can be obtained 7. Allen .2003 .) The systematic input offset voltage 5. 24001 1. CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03) © P.E.2003 Page 6.63 A More Robust Method of Measuring the OpenLoop Frequency Response Circuit: VDD vIN CL C R RL vOUT VSS Fig.) The linear range of operation 2.
dB © P. the GB = 1MHz.61 – Measurement of the Op Amp OpenLoop Gain Develop the closedloop frequency response for op amp circuit used to measure the openloop frequency response.72) CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03) Magnitude.01) vOUT = = = vIN (s+0. R = 10MΩ.2003 Page 6.Chapter 6 – Section 6 (2/25/03) Page 6. 1/sC 80 v + v vOUT = Av(s) OUT IN R+(1/sC) Av(jω) 60 1/RC v +vIN = Av(s) 40 s+(1/RC) OUT Vout(jω) vOUT [s +(1/RC)]Av(s) Vin(jω) 20 ∴ vIN = s +(1/RC)+Av(s)/RC 0 (s+0.E.01) [s +(1/RC)] = s +0.E. Allen .07)(s+1529.001 0. 24004 vOUT CL RL VDD VSS Make R as large and measure vout and vi to get the open loop gain. Allen .01 Av(s) +1/RC S01E2S2 Radian Frequency (radians/sec) Substituting.01)(s+500π)+2πx104 s2+500πs +2πx104 (s+41. and C = 10µF. 2πx106 GB Av(s) = s +(GB/Av(0)) = s +500π The closedloop transfer function of the op amp can be expressed as.01 = s +(1/RC) 20 0. CMOS Analog Circuit Design © P. Sketch the closedloop frequency response of the magnitude of Vout/Vin if the low frequency gain is 4000 V/V.1 10 1000 105 107 Av(s) +0. 2πx106s 2πx104 2πx106s 2πx104 2πx106(s +0.65 Simulation and Measurement of OpenLoop Frequency Response with Moderate Gain Op Amps R vIN R + vi Fig.2003 .64 Example 6. Solution The openloop transfer function of the op amp is. Av(s) gives.
due to mismatches in current mirrors.) Mismatch offset .E.E.Chapter 6 – Section 6 (2/25/03) Page 6.2003 . Allen . exists even with ideally matched transistors.due to mismatches in transistors (normally not available in simulation except through Monte Carlo methods).64 Types of offset voltages: 1. 6.66 Simulation or Measurement of the Input Offset Voltage of an Op Amp vOUT=VOS + VDD VOS  CL RL VSS Fig. CMOS Analog Circuit Design © P. CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03) © P.65 Make sure that the output voltage of the op amp is in the linear region. 2. Allen . 6.2003 Page 6.) Systematic offset .67 Simulation of the CommonMode Voltage Gain V + OS + vout VDD vcm  CL RL VSS Fig.
24008 .can be measured similar to PSRR+ by changing only VSS.) Set VDD’ = VDD .= vos 1000·vcm and CMRR = v os © P.Chapter 6 – Section 6 (2/25/03) Page 6. in the above circuit the value of vout is the same so that we get vicm CMRR = v id +  Measurement of CMRR and PSRR Configuration: vOS Note that vI ≈ 1000 or vOS ≈ 1000vI How Does this Circuit Work? CMRR: PSRR: 1.) Set VDD’ = VDD + 1V VDD’ = VDD + 1V VSS’ = VSS + 1V VSS’ = VSS vOUT’ = 0V vOUT’ = vOUT + 1V 2.) Set 1.) The ±1V perturbation can be replaced by a sinusoid to measure CMRR or PSRR as follows: 1000·vdd 1000·vss PSRR+ = vos .2003 Substituting in the previous expression gives. Allen .) Measure vOS called vOS2 called vOS4 5.68 vOS 10kΩ + 10Ω vI  Note: 1.) Measure vOS 2. Allen . Prove that the CMRR can be given as 1000 vicm CMRR = vos Solution The definition of the commonmode rejection ratio is Avd (vout/vid) = CMRR = A (vout/vicm) cm However.) Set 3.E. CMOS Analog Circuit Design +  How Does the Previous Idea Work? A circuit is shown which is used to measure the CMRR and PSRR of an op amp.) 5.1V VDD’ = VDD .1V VSS’ = VSS . 24007 100kΩ 100kΩ vicm vOUT VDD vicm CL RL VSS Fig. 2.2003 Page 6.) Measure vOS called vOS1 called vOS3 3.69 CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03) vos 10kΩ + 10Ω vi  vos But vid = vi and vos ≈ 1000vi = 1000vid ⇒ vid = 1000 vicm 1000 vicm CMRR = v = vos os 1000 © P. PSRR.) Measure vOS 4.1V vOUT’ = 0V 4.) PSRR.) 2000 2000 CMRR=vOS2vOS1 PSRR+=vOS4vOS3 100kΩ 100kΩ vSET vOUT VDD CL RL VSS Fig.E.1V VSS’ = VSS vOUT’ = vOUT .
Allen .2003 Page 6.611 CMRR of Ex.31 using the Above Method of Simulation 85 80 75 200 150 Arg[CMRR] Degrees 104 105 106 Frequency (Hz) 107 108 100 50 0 50 100 150 200 CMRR dB 70 65 60 55 50 45 10 100 1000 10 100 1000 104 105 106 Frequency (Hz) 107 108 Fig.2003 . PSRR+ must equal PSRR) CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03) © P.67 Av(V1V2) Vout V 1+ V Vout = Av(V1V2) ±A 2 = AvVout ± AcmVcm ±Acm ±Acm Vout = 1+A Vcm ≈ A Vcm v v Av Vcm ∴ CMRR = Acm = Vout cm 2 (However. Consider the following: Vcm V2 Vcm V2 V1 + Vcm VSS VDD Vout V1 Vcm ±AcVcm Fig. Allen . 6.Chapter 6 – Section 6 (2/25/03) Page 6.E. 6.E.610 Simulation of CMRR of an Op Amp None of the above methods are really suitable for simulation of CMRR. 24010 CMOS Analog Circuit Design © P.
2003 Page 6. Allen . 6. Should also plot the current in the input stage (or the power supply current).613 Simulation or Measurement of ICMR vOUT IDD vOUT + VDD 1 1 vIN ICMR Also. Allen .24011 vIN  ISS CL RL VSS Initial jump in sweep is due to the turnon of M5. CMOS Analog Circuit Design © P.= A = V dd out ss out Works well as long as CMRR is much greater than 1.E. monitor IDD or ISS. Fig.2003 .E. CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03) © P.Chapter 6 – Section 6 (2/25/03) Page 6.612 Direct Simulation of PSRR Circuit: Vdd V2 V2 V1 + VDD V1 Vss VSS Vss = 0 Av(V1V2) Vout ±AddVdd Fig.69 Vout = Av(V1V2) ±AddVdd = AvVout ± AddVdd ±Add ±Add Vout = 1+A Vdd ≈ A Vdd v v Av Vdd Av V ss ∴ PSRR+ = A = V and PSRR.
less than 0.E.Chapter 6 – Section 6 (2/25/03) Page 6.5V for MOS).614 Measurement or Simulation of the OpenLoop Output Resistance Method 1: vOUT + vI +  vOUT RL VDD VO1 VO2 VOS Without RL With RL vI(mV) VSS Fig. Allen .VDD Method 2: vIN Rout Ro Fig.615 Measurement or Simulation of Slew Rate and Settling Time Volts Peak Overshoot vin IDD vout + VDD +SR SR 1 1 Settling Time Feedthrough Settling Error Tolerance vout t Fig. Allen .2003 . CMOS Analog Circuit Design © P.E. 24013 + VSS 1 Av 100Ro 1 1 Rout = Ro + 100R + 100Ro ≅ Av CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03) © P.5VO1 ⇒ Rout = RL R 100R .e. then make the input step size small enough to avoid slew rate (i. 24014 vin  CL RL VSS If the slew rate influences the small signal response.2003 Page 6. 24012 V 01 Rout = RL V02 − 1 or vary RL until VO2 = 0.
2003 Page 6.3M3 M4 M6 1 and shown in Fig.5V The op amp designed in Example 6.Chapter 6 – Section 6 (2/25/03) Page 6. 24015 CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03) © P.61).61).31. Phase Margin Overshoot 1.33 is to be analyzed 15µm 15µm 94µm 1µm 1µm by SPICE to determine if the specifications 1µm Cc = 3pF are met.31.2003 . 4. we will make an educated estimate of these values by using the following approximations.0 0.5 µm 1µm Solution/Simulation M5 1µm M8 M7 Fig.6 0. L2 is the length of a minimumsize square contact to moat (Rule 5A of Table 2. VDD = 2. The table on the next page gives the SPICE subcircuit description of Fig.616 Phase Margin and Peak Overshoot Relationship It can be shown (Appendix C) that: Phase Margin (Degrees) = 57.2958cos1[ 4ζ4+1 . and L3 is the minimum allowable distance between a contact to moat and the edge of the moat (Rule 5D of Table 2.4 ζ= 1 2Q 0.62 Simulation of the CMOS Op Amp of Ex. While the values of AD.617 Example 6. The device parameters to be used vout M1 M2 are those of Tables 3.2 0. In 30µA 3 µ m 3 µ m C L= 1µm 1µm addition to verifying the specifications of 10pF 95 µ A vin Example 6. Allen .2ζ2] πζ 80 Overshoot (%) = 100 exp 1ζ2 70 60 50 40 30 20 10 0 0 0.1 Fig. Allen . 6. a 5% overshoot corresponds to a phase margin of approximately 64°.5V The op amp will be treated as a subcircuit in order to simplify the repeated analyses. 6. CMOS Analog Circuit Design © P. and PS could be calculated if the physical layout was complete.61). AS = AD ≅ W[L1 + L2 + L3] PS = PD ≅ 2W + 2[L1 + L2 + L3] where L1 is the minimum allowable distance between the polysilicon and a contact in the moat (Rule 5C of Table 2.12 and 3.33. PD.21.8 1 Overshoot (%) 100 Phase Margin (Degrees) 10 For example. AS. 24016 VSS = 2. we will simulate PSRR+ + 30µA and PSRR. 6.E.E.5µm 14µm 1 µ m 4.
005 100U .618 Example 6.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P +LD=0.016U TOX=14N .7 KP=50U GAMMA=0.005 0.2003 Page 6.70 KP=110U GAMMA=0.E.AC DEC 10 1 10MEG .7 +MJ=0.ENDS CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03) © P.E.MODEL PMOS1 PMOS VTO=0.OP ..5 VIN .PROBE (This entry is unique to PSPICE) .Continued Op Amp Subcircuit: .5U L=1U AD=27P AS=27P PD=21U PS=21U CC 5 6 3.OPTION LIMPTS=1000 VIN+ 1 0 DC 0 AC 1.04 PHI=0. Allen . .2 0 DC 0 CL 3 0 10P X1 1 2 3 4 5 OPAMP .5 MJSW=.0P .35 CGBO=700P CGSO=220P CGDO=220P CJ=560U CJSW=350P +LD=0. Allen . .2003 .Continued PSPICE Input File for the OpenLoop Configuration: EXAMPLE 1 OPEN LOOP CONFIGURATION .MODEL NMOS1 NMOS VTO=0.DC VIN+ 0. (Subcircuit of previous slide) .5U L=1U AD=27P AS=27P PD=21U PS=21U M6 6 5 8 8 PMOS1 W=94U L=1U AD=564P AS=564P PD=200U PS=200U M7 6 7 9 9 NMOS1 W=14U L=1U AD=84P AS=84P PD=40U PS=40U M8 7 7 9 9 NMOS1 W=4.PRINT DC V(3) . .62 .8 +MJ=0.5 MJSW=0.TF V(3) VIN+ .05 PHI=0. .PRINT AC VDB(3) VP(3) . .619 Example 6.SUBCKT OPAMP 1 2 6 8 9 M1 4 2 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U M2 5 1 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U M3 4 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U M4 5 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U M5 3 7 9 9 NMOS1 W=4.57 LAMBDA=0.62 .Chapter 6 – Section 6 (2/25/03) Page 6.4 LAMBDA=0. 24017 .5 VSS 0 5 DC 2.2 vin + 1 + 9 VSS 8 VDD 6 vout Fig.0 VDD 4 0 DC 2.014U TOX=14N IBIAS 8 7 30U .END CMOS Analog Circuit Design © P.
24018 CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03) © P.31: 80 200 150 Phase Shift (Degrees) 60 Magnitude (dB) 100 50 0 50 40 20 0 100 150 200 20 GB 40 10 100 1000 105 106 104 Frequency (Hz) 107 108 Phase Margin 10 100 1000 104 105 106 Frequency (Hz) GB 107 108 Fig.Continued Openloop transfer frequency response of Example 6.621 Example 6.5 2 Fig. 6.5 1.620 Example 6.5 2 1.5 vIN(mV) 1 1. Allen .Chapter 6 – Section 6 (2/25/03) Page 6.31: 2.62 .5 2 VOS 1 vOUT(V) 0 1 2 2.616 CMOS Analog Circuit Design © P.Continued Openloop transfer characteristic of Example 6. Allen .E.62 .E.5 0 0.2003 Page 6.2003 .0 0.
Chapter 6 – Section 6 (2/25/03)
Page 6.622
Example 6.62  Continued Input common mode range of Example 6.31:
EXAMPLE 6.61 UNITY GAIN CONFIGURATION. .OPTION LIMPTS=501 VIN+ 1 0 PWL(0 2 10N 2 20N 2 2U 2 2.01U 2 4U 2 4.01U + .1 6U .1 6.0 1U .1 8U .1 8.01U .1 10U .1) VDD 4 0 DC 2.5 AC 1.0 VSS 0 5 DC 2.5 CL 3 0 20P X1 1 3 3 4 5 OPAMP . 4 . . (Subcircuit of Table 6.61) 3 . . . 2 .DC VIN+ 2.5 2.5 0.1 .PRINT DC V(3) 1 .TRAN 0.05U 10U 0 10N .PRINT TRAN V(3) V(1) 0 .AC DEC 10 1 10MEG .PRINT AC VDB(3) VP(3) 1 .PROBE (This entry is unique to PSPICE) .END 2
vOUT (V)
3 3 2 1
3 1 vin

4
VDD
3 vout
Subckt. + 5
VSS
Fig. 6.616A
ID(M5)
40 30 20 Input CMR 10 0
0 vIN(V)
1
2
3
Fig. 24021
CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03)
© P.E. Allen  2003 Page 6.623
Example 6.62  Continued Positive PSRR of Example 6.31:
100
Arg[PSRR+(jω)] (Degrees)
100
80
PSRR+(jω) dB
50
60 40 20 0 20 10
0
50
100
1000
10 10 10 Frequency (Hz)
4
5
6
10
7
10
8
100 10
100
1000
104 105 106 Frequency (Hz)
107
ID(M5) µA
108
Fig. 24022
CMOS Analog Circuit Design
© P.E. Allen  2003
Chapter 6 – Section 6 (2/25/03)
Page 6.624
Example 6.62  Continued Negative PSRR of Example 6.31:
120 100
PSRR(jω) dB Arg[PSRR(jω)] (Degrees)
4
200 150 100 50 0 50 100 150 200 100 1000 10 10 10 Frequency (Hz)
5 6
80 60
PSRR+
40 20 10
10
7
10
8
10
100
1000
104 105 106 Frequency (Hz)
107
108
Fig. 24023
CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03)
© P.E. Allen  2003 Page 6.625
Example 6.62  Continued Largesignal and smallsignal transient response of Example 6.31:
1.5 1 0.5 Volts 0 Volts 0.15 0.1 0.05
vin(t) vout(t)
vout(t)
0
0.5 1 1.5 0 1 2 3 Time (Microseconds) 4 5
0.05
vin(t)
0.1 0.15
2.5
3.0
3.5 4.0 Time (Microseconds)
4.5
Fig. 24024
Why the negative overshoot on the slew rate? If M7 cannot sink sufficient current then the output stage slews and only responds to changes at the output via the feedback path which involves a delay. Note that dvout/dt ≈ 2V/0.3µs = 6.67V/µs. For a 10pF capacitor this requires 66.7µA and only 95µA66.7µA = 28µA is available for Cc. For the positive slew rate, M6 can provide whatever current is required by the capacitors and can immediately respond to changes at the output.
CMOS Analog Circuit Design
VDD M6
Cc iCc
iCL
vout
dvout dt
CL
95µA + VBias 
M7 VSS
Fig. 24025
© P.E. Allen  2003
Chapter 6 – Section 6 (2/25/03)
Page 6.626
Example 6.62  Continued Comparison of the Simulation Results with the Specifications of Example 6.31: Specification (Power supply = ±2.5V) Open Loop Gain GB (MHz) Input CMR (Volts) Slew Rate (V/µsec) Pdiss (mW) Vout range (V) PSRR+ (0) (dB) PSRR (0) (dB) Phase margin (degrees) Output Resistance (kΩ) Design (Ex. 6.31) >5000 5 MHz 1V to 2V >10 (V/µsec) < 2mW ±2V 60° Simulation (Ex. 1) 10,000 5 MHz 1.2 V to 2.4 V, +10, 7(V/µsec) 0.625mW +2.3V, 2.2V 87 106 65° 122.5kΩ
CMOS Analog Circuit Design Chapter 6 – Section 6 (2/25/03)
© P.E. Allen  2003 Page 6.627
Example 6.63 Why is the negativegoing overshoot larger than the positivegoing overshoot on the smallsignal transient response of the last slide? Consider the following circuit and waveform:
VDD = 2.5V
94/1 M6 i6 iCc iCL 0.1V
Cc 95µA VBias
M7
vout
t
CL
0.1V 0.1µs 0.1µs
Fig. 24026 VSS = 2.5V During the rise time, iCL = CL(dvout/dt )= 10pF(0.2V/0.1µs) = 20µA and iCc = 3pf(2V/µs) = 6µA ∴ i6 = 95µA + 20µA + 6µA = 121µA ⇒ gm6 = 1066µS (nominal was 942.5µS) During the fall time, iCL = CL(dvout/dt) = 10pF(0.2V/0.1µs) = 20µA and iCc = 3pf(2V/µs) = 6µA ∴ i6 = 95µA  20µA  6µA = 69µA ⇒ gm6 = 805µS The dominant pole is p1 ≈ (RIgm6RIICc)1 but the GB is gmI/Cc = 94.25µS/3pF = 31.42x106 rads/sec and stays constant. Thus we must look elsewhere for the reason. Recall that p2 ≈ gm6/CL which explains the difference. ∴ p2(95µA) = 94.25x106 rads/sec, p2(121µA) = 106.6 x106 rads/sec, and p2(69µA) = 80.05 x106 rads/sec. Thus, the phase margin is less during the fall time than the rise time.
CMOS Analog Circuit Design
© P.E. Allen  2003
) v2 Fig. FREQUENCY INDEPENDENT.SUBCKT SIMPLEOPAMP 1 2 3 RID 1 2 {Rid} RO 3 0 {Ro} GAVD 0 3 1 2 {Avd/Ro} .72 SMALL SIGNAL.) vo Ro v2 (b. OP AMP MODELS Simple Model v1 v1 A v2 (a.Chapter 6 – Section 7 (2/25/03) Page 6. 1c RID 1 2 {Rid} RO 3 0 {Ro} GAVD 0 3 1 2 {Avd/Ro} Subcircuit SPICE Description for Fig. inductors. frequency dependent • Large signal Time independent Time dependent CMOS Analog Circuit Design Chapter 6 – Section 7 (2/25/03) © P.) Op amp symbol. controlled sources. A macromodel uses resistors. 01001 Figure 1 . (b.) vo 1 4 3 v1 1 3 R id 2 Ro v o Avd (v 1 v 2 ) R id 2 Avd (v v ) Ro 1 2 (c. SPICE Description of Fig.2003 Page 6.E.E.) Norton form of simple model. Op Amp Characterization • Small signal.71 SECTION 6. 1c . frequency independent • Small signal. (c.) Thevenin form of simple model.MACROMODELS FOR OP AMPS Macromodel A macromodel is a model that captures some or all of the performance of a circuit using different components (generally simpler). and some active devices (mostly diodes) to capture the essence of the performance of a complex circuit like an op amp without modeling every internal component of the op amp.(a. Allen . capacitors.7 . Allen .ENDS SIMPLEOPAMP CMOS Analog Circuit Design © P.2003 .
2003 . Example 1 VIN 1 0 DC 0 AC 1 XOPAMP1 1 3 2 SIMPLEOPAMP R1 3 0 1KOHM R2 2 3 100KOHM . Solution Rin Rout The circuit with the SPICE node 2 1 v out A1 numbers identified is shown in Fig.Use of the Simple Op Amp Model Use SPICE to find the voltage gain. 01002 The input file for this example is given as follows. GAVD/RO 0 3 1 2 {Avd/Ro} GAVC1/RO 0 3 1 0 {Avc/2Ro} GAVC2/RO 0 3 2 0 {Avc/2Ro} RO 3 0 {Ro} .Simple op amp model including differential and common mode behavior.71 .END CMOS Analog Circuit Design Chapter 6 – Section 7 (2/25/03) The command . 01003 Linear Op Amp Macromodel SPICE File: . + 3 Figure 2 – Noninverting voltage amplifier for Ex. Av. The results extracted from the output file are: **** SMALLSIGNAL CHARACTERISTICS V(2)/VIN = 1. vin R1 = 1kΩ R2 = 100kΩ Fig.ENDS SIMPLEOPAMP .SUBCKT LINOPAMP 1 2 3 RIC1 1 0 {Ric} RID 1 2 {Rid} RIC2 2 0 {Ric} CMOS Analog Circuit Design Figure 3 . and Ro = 100Ω.ENDS LINOPAMP © P. vout/vin. 1. 2.E. Find the input resistance.TF V(2) VIN .74 Common Mode Model Electrical Model: Acmv1+v2 vo = Avd(v1v2) + R o 2 Macromodel: 1 Ric1 Rid 2 3 Avd(v1 v2 ) Ro Ric2 Avc v1 2Ro Avc v2 2Ro + Ro vo Fig. the input resistance. Allen . Rout. Rin.2003 Page 6. and the voltage gain. of the noninverting voltage amplifier configuration when R1 = 1kΩ and R2 = 100kΩ. © P.E. Rout of Fig.73 Example 6. Allen . The op amp parameters are Avd = 100.901E+08 OUTPUT RESISTANCE AT V(2) = 1.010E01.000.009E+02 INPUT RESISTANCE AT VIN = 9. the output resistance.Chapter 6 – Section 7 (2/25/03) Page 6. Rin. and the output resistance.SUBCKT SIMPLEOPAMP 1 2 3 RID 1 2 1MEGOHM RO 3 0 100OHM GAVD/RO 0 3 1 2 1000 . output resistance. and voltage or current gain of an amplifier.TF finds the small signal input resistance. 2. Rid = 1MΩ.
2003 Page 6. We will use the circuit of Fig. 01005 Figure 5 . 2 if the gain is +1.Chapter 6 – Section 7 (2/25/03) Page 6. Allen .ENDS .72 . Example 2 R12 32 0 1KOHM VIN 1 0 DC 0 AC 1 R22 22 32 9KOHM *Unity Gain Configuration XOPAMP1 1 31 21 *Gain of 100 Configuration XOPAMP3 1 33 23 LINFREQOPAMP LINFREQOPAMP R11 31 0 15GOHM R13 33 0 1KOHM R21 21 31 1OHM R23 23 33 99KOHM *Gain of 10 Configuration XOPAMP2 1 32 22 . Solution The parameters of the model are R2/R1 = 0. Allen . The input file for this example is shown below. CMOS Analog Circuit Design Chapter 6 – Section 7 (2/25/03) © P.2003 .Frequency dependent model with constant output resistance. Let us additionally select Rid = 1MΩ and Ro = 100Ω.Macromodel for the op amp including the frequency response of Avd.END CMOS Analog Circuit Design © P.76 Example 6. and 99. +10.75 Small Signal. Model Using Passive Components with Constant Output Resistance: v1 1 3 4 vo Rid v2 2 Avd(0) (v1 v2 ) R1 R1 C1 v3 Ro Ro Fig. 2 and insert the model as a subcircuit. 4 to find the frequency response of Fig. 01004 Figure 4 . 9. Frequency Dependent Op Amp Models Dominant Pole Model: Avd(0) 1 Avd(s) = (s/ω ) + 1) where ω1= R C (dominant pole) 1 1 1 Model Using Passive Components: v1 1 3 vo Rid Avd(0) (v1 v2 ) R1 R1 C1 v2 2 Fig.Frequency Response of the Noninverting Voltage Amplifier Use the model of Fig. and +100 V/V assuming that Avd(0) = 105 and ω1= 100 rads/sec.PROBE .E.PRINT AC V(21) V(22) V(23) .AC DEC 10 100 10MEG .E.SUBCKT LINFREQOPAMP 1 2 3 LINFREQOPAMP RID 1 2 1MEGOHM GAVD/RO 0 3 1 2 1000 R1 3 0 100 C1 3 0 100UF .
59MHz 1MHz 10MHz Fig.Chapter 6 – Section 7 (2/25/03) Page 6. GAVD/RO 0 3 LAPLACE {V(1. Avd(0) Ro Avd(s) GAvd/Ro = Ro = s ω1 + 1 where Avd(0) = 100.000. CMOS Analog Circuit Design Chapter 6 – Section 7 (2/25/03) © P. Implements.2)} = {1000/(0.01s+1)}.9kHz 20dB 100Hz 1kHz 159kHz 1.Frequency response of the 3 noninverting voltage amplifiers of Ex. Allen . 01006 Gain of 100 Gain of 10 Gain of 1 10kHz 100kHz Figure 6 .E.E. Ro = 100Ω.72 . Allen .77 Example 6. 2.2003 .2003 Page 6.Continued 40dB 30dB 20dB 10dB 0dB 10dB 15.78 Behavioral Frequency Model Use of Laplace behavioral modeling capability in PSPICE. and ω1 = 100 rps CMOS Analog Circuit Design © P.
79 Differential and Common Mode Frequency Dependent Models Op Amp Macromodel 1 4 Avc v1 2Ro Ric1 Rid Avc v2 2Ro C2 R2 3 2 5 + Ric2 Avd(v1 v2 ) Ro C1 R1 v3 Ro v4 Ro Ro vo Fig.) Method of modeling zeros without introducing new nodes.710 Zeros in the Transfer Function Models: 3 + Ro Avd(v1 v2 ) Ro 4 3 4 + C1 R1 kAvd (v1 v2 ) Ro v3 Ro Ro vo (b.) Figure 8 .) Independent zero model. 01008 L1 vo Avd(v1 v2 ) R1  (a.Chapter 6 – Section 7 (2/25/03) Page 6.(a. Allen . 01007 Figure 7 . Inductor: Avd(0) s Vo(s) = Ro (sL1 + Ro) [V1(s)V2(s)] = Avd(0)Ro/L1 + 1 [V1(s)V2(s)] . (b.Op amp macromodel for separate differential and common voltage gain frequency responses. CMOS Analog Circuit Design Chapter 6 – Section 7 (2/25/03) © P. Allen . 1 The zero can be expressed as z1 = ω1 1 + k where k can be + or .2003 .) Fig.by reversing the direction of the current source.E.2003 Page 6. CMOS Analog Circuit Design © P. Feedforward: Avd(0) Vo(s) = (s/ω1) +1 1+k(s/ω1)+k [V1(s)V2(s)] .E.
CMOS Analog Circuit Design © P.73 .000.9Hz or 100rps 20dB 1. a pole at 100rps. it is not possible to determine whether the zero is in the RHP or LHP of the complex frequency axis. Next.2003 Page 6.SUBCKT LINFREQOPAMP 1 2 4 RID 1 2 1MEGOHM GAVD/R1 0 3 1 2 1 R1 3 0 100KOHM C1 3 0 0.712 Example 6. Unless we examined the phase shift.ENDS .PRINT AC V(2) VDB(2) VP(2) .59MHz or 10Mrps 0dB 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz Fig. (6) gives k as 105. 9.59MHz (10Mrps). The following input file verifies this model.1UF GV3/RO 0 4 3 0 0. there is a pole at 100rps (15. To get the pole at 100rps. and a zero in the righthalf.9Hz) and a zero at 1.01 RO 4 0 100 .1µF.73. Allen . 8b to model an op amp with a differential voltage gain of 100.2003 . an output resistance of 100Ω. Since ω1 = 100rps. C1 = 1/(100R1) = 0.01 GAVD/RO 4 0 1 2 0.1) Vo(s) = (s/100 + 1) .Modeling Zeros in the Op Amp Frequency Response Use the technique of Fig. Solution The transfer function we want to model is given as 105(s/107 . complex frequency plane at 107 rps.PROBE . 100dB 80dB VDB(2) 60dB 40dB 15.Continued The asymptotic magnitude frequency response of this simulation is shown in Fig.AC DEC 10 1 100MEG .73 .711 Example 6. 6. we want z1 to be 107 rps.END CMOS Analog Circuit Design Chapter 6 – Section 7 (2/25/03) © P.Asymptotic magnitude frequency response of the op amp model of Ex.E. Allen .Chapter 6 – Section 7 (2/25/03) Page 6. then Eq.E. 01009 Frequency Figure 9 . We note that although the frequency response is plotted in Hertz. Let us arbitrarily select R1 as 100kΩ which will make the GAVD/R1 gain unity. Example 3 VIN 1 0 DC 0 AC 1 XOPAMP1 1 0 2 LINFREQOPAMP .
PROBE . Rid = 1MΩ. unity gain. The op amp parameters are Avd(0) = 100. voltage amplifier when vIN is varied from 15V to +15V. Example 4 VIN 1 0 DC 0 XOPAMP 1 2 2 NONLINOPAMP .SUBCKT NONLINOPAMP 1 2 3 RIC1 1 0 100MEG RLIM1 1 4 0. VIH1 =VIH2 = VIL1 = VIL2 = 5V.714 Example 6.000. Subcircuit Description . Ro = 100Ω.PRINT V(2) .0001 .1 D1 4 6 IDEALMOD VIH1 6 0 {VIH1} D2 7 4 IDEALMOD VIL1 7 0 {VIL1} RID 4 5 {Rid} RIC2 2 0 {Ricm} RLIM2 2 5 0.001 . VOH = VOL = 10V.2003 .Illustration of the Voltage Limits of the Op Amp Use the macromodel of Fig.Op amp macromodel that limits the input and output voltages. Ricm = 100MΩ.Chapter 6 – Section 7 (2/25/03) Page 6. 01010 2 D3 +  D4 VIL2 +  9 Avd(v v ) 4 5 Ro Figure 10 .DC VIN 15 15 0.SUBCKT NONLINOPAMP 1 2 3 RIC1 1 0 {Ricm} RLIM1 1 4 0.1 .E.MODEL IDEALMOD D N=0. Avc(0) = 10. 10 to plot vOUT as a function of vIN for the noninverting.1 D1 4 6 IDEALMOD VIH1 6 0 5V D2 7 4 IDEALMOD VIL1 7 0 5V RID 4 5 1MEG RIC2 2 0 100MEG RLIM2 2 5 0.2003 Page 6.END CMOS Analog Circuit Design © P.1 D3 5 8 IDEALMOD VIH2 8 0 5V D4 9 5 IDEALMOD VIL2 9 0 5v GAVD/RO 0 3 4 5 1000 GAVC1/2RO 0 3 4 0 0.ENDS © P. Solution The input file for this example is given below.E. Allen .MODEL IDEALMOD D N=0.05 RO 3 0 100 D5 3 10 IDEALMOD VOH 10 0 10V D6 11 3 IDEALMOD VOL 11 0 10V .ENDS . Allen .05 GAVC2/2RO 0 3 5 0 0.1 D3 5 8 IDEALMOD VIH2 8 0 {VIH1} CMOS Analog Circuit Design Chapter 6 – Section 7 (2/25/03) D4 9 5 IDEALMOD VIL2 9 0 {VIL2} GAVD/RO 0 3 4 5 {Avd/Ro} GAVC1/RO 0 3 4 0 {Avc/Ro} GAVC2/RO 0 3 5 0 {Avc/Ro} RO 3 0 {Ro} D5 3 10 IDEALMOD VOH 10 0 {VOH} D6 11 3 IDEALMOD VOL 11 0 {VOL} .74 .713 Large Signal Macromodels for the Op Amp Output and Input Voltage Limitations 1 RLIM Ric1 D1 VIH1 RLIM Ric2 VIH2 + 6 4 D2 VIL1 + 5 8 7 Nonlinear Op Amp Macromodel Avc v4 2Ro Avc v5 2Ro D5 Ro VOH D6 3 Rid + + 10 + 11 vo VOL Fig.
01013 Ro D4 ILimit VOH D5 +  D6 7 vo VOL +  8 CMOS Analog Circuit Design © P. Allen .5V 5V 7.74 .2003 Page 6.Continued 7.5V 5V 2. Allen .5V V(2) 0V 2.5V 10V 5V 0V VIN 5V 10V Fig. 01011 Figure 11 .715 Example 6. 01012 Macromodel for Output Voltage and Current Limiting: v1 1 4 D3 5 D1 D2 6 3 Rid 2 v2 Avd (v v ) Ro 1 2 Fig.Simulation results for Ex.E.Chapter 6 – Section 7 (2/25/03) Page 6. 4.716 Output Current Limiting Technique: Io 2 Io ILimit 2 D1 D2 Io 2 D3 ILimit D4 Io 2 Io ILimit 2 Io 2 Fig. CMOS Analog Circuit Design Chapter 6 – Section 7 (2/25/03) © P.2003 .E.Illustration of the Voltage Limits of the Op Amp .
Influence of Current Limiting on the Amplifier Voltage Transfer Curve VIN 1 0 DC 0 D4 6 4 IDEALMOD R1 1 2 500 ILIMIT 5 6 20MA R2 2 3 500 D5 3 7 IDEALMOD RL 3 0 500 VOH 7 0 10V XOPAMP 0 2 3 NONLINOPAMP D6 8 3 IDEALMOD . The input file for this simulation is given below.00001 GAVD 0 4 1 2 1000 .PROBE D3 4 5 IDEALMOD .2003 . v3.000.DC VIN 15 15 0. Solution For the ideal op amp we will choose Avd = 100. as a function of the input voltage. VIH = VIL = 10V.718 Example 6. Allen .Chapter 6 – Section 7 (2/25/03) Page 6.75 .END CMOS Analog Circuit Design Chapter 6 – Section 7 (2/25/03) © P. the op amp is ideal. 10V 5V V(3) 0V 5V 10V 15V 10V 5V 0V VIN 5V 10V 15V Fig.PRINT DC V(3) D2 6 3 IDEALMOD . and R1 = R2 = RL = 500Ω where RL is a resistor connected from the output to ground.2003 Page 6. Assume the VOH = VOL = 10V.Continued The resulting plot of the output voltage.1 D1 3 5 IDEALMOD . and Ro = 100Ω and assume one cannot tell the difference between these parameters and the ideal parameters.ENDS RO 4 0 100 . vIN is shown in Fig.SUBCKT NONLINOPAMP 1 2 3 VOL 8 0 10V RID 1 2 1MEGOHM . 01014 Figure 14 .75 . The remaining model parameters are VOH = VOL = 10V and ILimit = ±20mA. the maximum output current is ±20mA. CMOS Analog Circuit Design © P.717 Example 6. Rid = 1MΩ.Results of Example 5.E. Allen .Influence of Current Limiting on the Amplifier Voltage Transfer Curve Use the model above to illustrate the influence of current limiting on the voltage transfer curve of an inverting gain of one amplifier. Example 5 .E.MODEL IDEALMOD D N=0. Otherwise. 14.
000. and Ro = 100Ω.E.Chapter 6 – Section 7 (2/25/03) Page 6.01 RO 3 0 100 .720 Example 6. Let us assume the op amp parameters of Avd = 100.0001 . ω1 = 100rps.2003 Page 6. Example 6 . The simulation input file based on the macromodel of Fig.1UF D1 0 6 IDEALMOD D2 7 0 IDEALMOD D3 5 6 IDEALMOD D4 7 5 IDEALMOD ISR 6 7 1A GVO/R0 0 3 4 5 0.76 .ENDS CMOS Analog Circuit Design © P.Simulation of the Slew Rate of A Noninverting Voltage Amplifier Let the gain of a noninverting voltage amplifier be 1.2003 . 01015 R1 C1 D4 ISR v4 v5 Ro Ro CMOS Analog Circuit Design Chapter 6 – Section 7 (2/25/03) © P. Solution We can calculate that the op amp should slew when the frequency is 159kHz. Allen . 15 is given below.SUBCKT NONLINOPAMP 1 2 3 RID 1 2 1MEGOHM GAVD/R1 0 4 1 2 1 R1 4 0 100KOHM C1 4 5 0. If the input signal is given as vin(t) = 10 sin(4x105πt) use the computer to find the output voltage if the slew rate of the op amp is 10V/µs.E. Allen .Simulation of slew rate limitation VIN 1 0 SIN(0 10 200K) XOPAMP 1 2 2 NONLINOPAMP .MODEL IDEALMOD D N=0.719 Slew Rate Limiting (Time Dependency) Slew Rate: dvo ±ISR dt = C1 = Slew Rate Macromodel: v1 1 4 6 D3 5 D1 D2 7 3 Rid v2 2 vo Avd(0) (v1 v2 ) R1 Fig. Rid = 1MΩ.
• Be sure to verify the correctness of the macromodels before using.Results of Ex. Key Aspects of Op Amp Macromodels • Use the simplest op amp macromodel for a given simulation.2003 .E. • All things being equal.722 SPICE Op Amp Library Models Macromodels developed from the data sheet for various components. no. Allen . use the macromodel with the min. • Macromodels are a good means of trading simulation completeness for decreased simulation time. of nodes. 6 on modeling the slew rate of an op amp. The influence of the slew rate causes the output waveform not to be equal to the input waveform. 10V 5V Output Voltage 0V 5V Input Voltage 2µ s 4µ s Time 6µs 8µs 10µs Fig.E. 16. • Use the SUBCKT feature for repeated use of the macromodel. CMOS Analog Circuit Design Chapter 6 – Section 7 (2/25/03) © P.721 Example 6. 01016 10V 0µs Figure 16 .76 .Chapter 6 – Section 7 (2/25/03) Page 6. Allen . CMOS Analog Circuit Design © P.Continued The simulation results are shown in Fig.2003 Page 6. The input waveform is shown along with the output waveform.
Feedforward Twostage op amp design Power supply rejection ratio of the twostage op amp Cascode op amps Simulation and measurement of op amps Macromodels of op amps • Purpose of this chapter is to introduce the simple twostage op amp to illustrate the concepts of op amp design and to form the starting point for the improvement of performance of the next chapter. • The design procedures given in this chapter are for the purposes of understanding and applying the design relationships and should not be followed rigorously as the designer gains experience.Selfcompensating .Chapter 6 – Section 8 (2/25/03) Page 6. CMOS Analog Circuit Design © P.81 SECTION 6.8 .SUMMARY • Topics Design of CMOS op amps Compensation of op amps .Miller .E. Allen .2003 .