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2/25/03
CHAPTER 9 – SWITCHED CAPACITOR CIRCUITS
Objective The objective of this presentation is: 1.) Introduce the principles of switched capacitor circuits 2.) Illustrate the application of switched capacitor circuits to filter design Outline Section 9.0  Introduction Section 9.1  Switched Capacitor Circuits Section 9.2  Switched Capacitor Amplifiers Section 9.3  Switched Capacitor Integrators Section 9.4  zdomain Models of TwoPhase, Switched Capacitor Circuits, Simulation Section 9.5  Firstorder, Switched Capacitor Circuits Section 9.6  Secondorder, Switched Capacitor Circuits Section 9.7  Switched Capacitor Filters Section 9.8  Summary
CMOS Analog Circuit Design Chapter 9 – Section 1 (2/25/03)
© P.E. Allen  2003 Page 9.11
Organization
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Chapter 9 Switched Capacitor Circuits Chapter 10 D/A and A/D Converters Systems Chapter 6 Simple CMOS & BiCMOS OTA's Chapter 7 High Performance OTA's Chapter 8 CMOS/BiCMOS Comparators Complex Simple Chapter 4 CMOS/BiCMOS Subcircuits Chapter 5 CMOS/BiCMOS Amplifiers
9.0  INTRODUCTION
CMOS Analog Circuit Design
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Circuits Chapter10 1 Chapter Introduction D/ to Analog CMOS Design Devices Chapter Chapter11 2 Analog CMOS Technology Systems Chapter 3 CMOS Modeling
© P.E. Allen  2003
Chapter 9 – Section 1 (2/25/03)
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Advantages of Switched Capacitor Circuits 1.) Compatibility with CMOS technology 2.) Good accuracy of time constants 3.) Good voltage linearity 4.) Good temperature characteristics Disadvantages of Switched Capacitor Circuits 1.) Experience clock feedthrough 2.) Require a nonoverlapping clock 3.) Bandwidth of the signal must be less than the clock frequency Philosophical Viewpoint The implementation of switched capacitors in CMOS technology occurred in the early 1970’s and represented a major step in implementing practical analog circuits and systems in an integrated circuit technology. Switched capacitor circuits are not new. James Clerk Maxwell used switches and a capacitor to measure the equivalent resistance of a galvanometer in the 1860’s.
CMOS Analog Circuit Design Chapter 9 – Section 1 (2/25/03) © P.E. Allen  2003 Page 9.11
SECTION 9.1 – SWITCHED CAPACITOR CIRCUITS
RESISTOR EMULATION Parallel Switched Capacitor Equivalent Resistor
i1(t) v1(t)
1 2
i2 (t) v2 (t) v1(t)
i1(t)
R
i2 (t) v2 (t)
Fig 9.101
vC (t)
C
TwoPhase, Nonoverlapping Clock:
1
1 0
2
t
1 0 0
CMOS Analog Circuit Design
T/2
T
3T/2 2T
t
Fig. 9.102
© P.E. Allen  2003
Chapter 9 – Section 1 (2/25/03)
Page 9.12
Equivalent Resistance of a Switched Capacitor Circuit Assume that v1(t) and v2(t) are changing slowly with respect to the clock period. The average current is, 1T 1 T/2 i1(t) i2 (t) ⌠ 1 i1(average) = T ⌡i1(t)dt = T ⌠ 2 ⌡i1(t)dt 0 0 Charge and current are related as, v (t) v1(t) vC (t) C 2 dq1(t) i1(t) = dt Fig. 9.103 Substituting this in the above gives, 1 T/2 q1(T/2)q1(0) CvC(T/2)CvC(0) i1(average) = T ⌠ = ⌡dq1(t) = T T
0
However, vC(T/2) = v1(T/2) and vC(0) = v2(0). Therefore, C [v1(T/2)v2(0)] C [V1V2] i1(t) i2 (t) R ≈ T T For the continuous time circuit: v1(t) v2 (t) V 1V 2 T i1(average) = R ∴ R≈C Fig. 9.104 For v1(t) ≈ V1 and v2(t) ≈ V2, the signal frequency must be much less than fc. i1(average) =
CMOS Analog Circuit Design Chapter 9 – Section 1 (2/25/03) © P.E. Allen  2003 Page 9.13
Example 9.11  Design of a Parallel Switched Capacitor Resistor Emulation If the clock frequency of parallel switched capacitor equivalent resistor is 100kHz, find the value of the capacitor C that will emulate a 1MΩ resistor. Solution The period of a 100kHz clock waveform is 10µsec. Therefore, using the previous relationship, we get that T 105 C = R = 106 = 10pF We know from previous considerations that the area required for 10pF capacitor is much less than for a 1MΩ resistor when implemented in CMOS technology.
CMOS Analog Circuit Design
© P.E. Allen  2003
how is the power v (t) v1(t) vC (t) dissipated? C 2 Continuous Time Resistor: (V 1 .)(V1V2) where i1 (aver.15 Other SC Equivalent Resistance Circuits i1(t) v1(t) 1 2 i2 (t) v1(t) i1(t) 1 2 i2 (t) 1 2 i1(t) S1 S2 v2 (t) C vC (t) C1 S1 S2 v2 (t) vC2(t) v1(t) S1 C S2 i2 (t) vC (t) 2 S1 1 vC1 (t) S2 v2 (t) Fig.V 2 )2 Power = R i1(t) v1(t) R i2 (t) v2 (t) Fig 9. vC1(T/2)=0. and vC1(T)= V1V2.0] (C1+C2)(V1V2) + = i1(average) = T T T T Equating the average current to the continuous time circuit gives: R = C1 + C2 CMOS Analog Circuit Design © P.2003 .14 Power Dissipation in the Resistance Emulation If the switched capacitor i1(t) i2 (t) 1 2 circuit is an equivalent resistance. C2 [vC2(T/2)vC2(0)] C1 [vC1(T)vC1(T/2)] + i1(average) = T T The sequence of switches cause. CMOS Analog Circuit Design Chapter 9 – Section 1 (2/25/03) © P. 9. if R = T/C.E. that flows during both the φ1 and φ2 clocks is: T q1(T/2)q1(0) q1(T)q1(T/2) 1T 1 T/2 ⌠i (t)dt = ⌠ ⌠ = i ( t ) dt + i ( t ) dt + i1(average) = T ⌡ ⌡ 1 ⌡ 1 1 T T T 0 0 T/2 Therefore.Chapter 9 – Section 1 (2/25/03) Page 9.101 Discrete Time Resistor Emulation: If the switches have an ON resistance of Ron. Allen .vC2(0)=V2. i1(t). Applying these results gives C2[V1V2] C1[V1V2. Allen . vC2(T/2)=V1.2003 Page 9. then the power dissipation is identical in the continuous time and discrete time realizations.E.) = RonT ⌠ ⌡et/(RonC)dt 0 ∴ Power = TRon (V 1 V 2 )2 T ⌠ ⌡ e t/(RonC)dt 0 = (T/C) (V1V2)2 e T /(RonC) + 1 (V 1 V 2 )2 ≈ (T/C) if T >> RonC Thus.105 Series C2 SeriesParallel Bilinear SeriesParallel: The current. (V 1 V 2 ) T Power = i1(aver. then power dissipated/clock cycle is. i1(average) can be written as.
Allen .Chapter 9 – Section 1 (2/25/03) Page 9. T 4x106 2C = R = 106 = 4pF Therefore.Design of a SeriesParallel Switched Capacitor Resistor Emulation If C1 = C2 = C. Allen .E.E.12 . C1 = C2 = C = 2pF.2003 . Solution The period of the clock waveform is 4µsec. Using above relationship we find that C is given as.16 Example 9. find the value of C that will emulate a 1MΩ resistor if the clock frequency is 250kHz.2003 Page 9. CMOS Analog Circuit Design Chapter 9 – Section 1 (2/25/03) © P.17 Summary of the Four Switched Capacitor Resistance Circuits Switched Capacitor Schematic Equivalent Resistor Emulation Resistance Circuit 1 2 Parallel v1(t) C v2 (t) T C T C 1 2 Series v1(t) C 1 2 v2 (t) SeriesParallel v1(t) C1 1 C2 2 v2 (t) T C1 + C2 Bilinear v1(t) C 2 1 v2 (t) T 4C CMOS Analog Circuit Design © P.
9. e v(t) 2 2 2 2 2 Fig. 1 2 v(t) 1 2 1 2 1 2 1 2 0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5 vO(t) t/T A sampleddata voltage waveform for the oddphase clock. 1 v(t) 1 1 1 1 0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5 t/T A sampleddata v (t) voltage waveform for the evenphase clock. The accuracy of τC can be expressed as. lowpass circuit: R1 v2 v1 C2 The transfer function of this simple circuit is. 9. firstorder. CMOS Analog Circuit Design Chapter 9 – Section 1 (2/25/03) © P. The accuracy of τ can be expressed as.1065 0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5 t/T © P.2003 Page 9.Chapter 9 – Section 1 (2/25/03) Page 9. Allen .E.1% to 1% depending on the size of components The above is the primary reason for the success of switched capacitor circuits in CMOS technology.19 ANALYSIS OF SWITCHED CAPACITOR CIRCUITS Analysis Methods for TwoPhase. Nonoverlapping Clocks Sampled Data Voltage Waveforms for a Twophase Clock: v*(t) A sampleddata voltage waveform for a twophase clock.106 H(jω) = V (jω) = jωR C + 1 = jωτ + 1 1 1 2 1 where τ1 = R1C2 is the time constant of the circuit and determines the accuracy.18 Accuracy of Switched Capacitor Circuits Consider the following continuous time. Continuous Time Accuracy Let τ1 = τC. Let τ1 = τD = 2 2 D C1 fcC1 dτD dC2 dC1 dfc τD = C2 .C1 .E. V2(jω) 1 1 Fig. dτC dR1 dC2 τC = R1 + C2 ⇒ 5% to 20% depending on the size of the components Discrete Time Accuracy T 1 C = C . Allen .2003 CMOS Analog Circuit Design .fc ⇒ 0.
The zdomain format for switched capacitor circuits will allow the analysis of transfer functions. o Vi (z) e Vi (z) = + Vi (z) Switched Capacitor Circuit 1 2 Vo (z) = V o (z) o (z) + V o e Fig.2 + ··· n=0 for all z for which the series V(z) converges.2003 Page 9. v(nT).6. o V i (z) + V i (z) e o e o j CMOS Analog Circuit Design © P. Now.3. a transfer function. CMOS Analog Circuit Design Chapter 9 – Section 1 (2/25/03) © P. Allen .··· zdomain Relationships: Consider the onesided ztransform of a sequence.4.Cont’d Timedomain Relationships: The previous figure showed that. v*(t) = vo(t) + ve(t) where the superscript o denotes the odd phase (φ1) and the superscript e denotes the even phase (φ2). t = nT/2. Nonoverlapping Clocks . Hoe(z) represents Vo (z)/ V i (z) . For any given sample point.5.E.n = v(0) + v(T)z.Chapter 9 – Section 1 (2/25/03) Page 9.E.111 Transfer Function Viewpoint of Switched Capacitor Circuits Inputoutput voltages of a general switched capacitor circuit in the zdomain. Also. defined as ∞ V(z) = Σ v(nT)z.2003 . the above may be expressed as nT o nT e nT + = v v v* 2 2 2 n=1.··· n=2. 9. Allen .··· n=1.2. this equation can be expressed in the zdomain as V*(z) = V o(z) + V e(z) . H(z) can be defined as Vo(z) Vo(z) + Vo (z) H(z) = Vi(z) = e .5.5.110 Analysis Methods for TwoPhase.4. For example.107 zdomain transfer functions: V o (z ) H ij (z) = i V i( z ) where i and j can be either e or o.1 + v(2T)z.3.
E. 5. low pass filter.113 Example 9. 2. Fig. 1 2 v1 C1 C2 v2 Switched capacitor. R1. 6. 1 1 2 2 2 t 3 n1 n. Allen . 3. CMOS Analog Circuit Design Chapter 9 – Section 1 (2/25/03) © P. 4.1 n n+ 1 n+1 T n. Firstorder. The timing of the clocks is also shown.) Identify the timedomain equation that relates the desired voltage variables.) The resulting equations are based on q = Cv.2 2 Equivalent circuit. This timing is arbitrary and is used to assist the analysis and does not change the result. This circuit was developed by replacing the resistor.) Analyze the circuit in the timedomain during a selected phase period. Allen .) Solve for the desired zdomain transfer function.Analysis of a Switched Capacitor.E.2 2 2 Clock phasing for this example.) Analyze the following phase period carrying over the initial conditions from the previous analysis.112 Approach for Analyzing Switched Capacitor Circuits 1. 7. Simplified equivalent circuit.) Replace z by ejωT and examine the frequency response. Low pass Filter Use the above approach to find the zdomain transfer function of the firstorder.109 e The voltage at the output (across C2) is vo 2(n1)T = v2 (n3/2)T CMOS Analog Circuit Design (1) © P.13 .2003 .2003 Page 9. 9. low pass switched capacitor circuit shown below. 9.2 2 v1o(n1)T C1 e 3 )T vo(n1)T v2 (n. of the previous circuit with the parallel switched capacitor resistor circuit.108 Solution φ1: (n1)T< t < (n0.) Convert this equation to the zdomain.Chapter 9 – Section 1 (2/25/03) Page 9.5)T Equivalent circuit: C2 v1o(n1)T C1 C2 e 3 )T vo(n1)T v2 (n. Fig.
vo 1 (n1)T and v2 (n1)T given as C1 C2 vo (n1)T + vo (n1)T.E. (n1/2 )T = ve 2 C1+C2 1 C1+C2 2 (2) (3) If we advance Eq. (4).13 .2003 Page 9.2 )T v2o(n1)T Fig. (2) yields the desired result given as C1 C2 vo (n1)T + vo (n1)T. (3) into Eq. Substituting.2003 . where α = H (z) = o = = (7) C2 1 + α .114 Example 9.13 .5)T< t < nT Equivalent circuit: e v1(n1/2)T C1 C2 C1 vo(n1)T 1 e 1 v 2 (n. Allen .110 The output of this circuit can be expressed as the superposition of two voltage o sources. (1) by one full period. solving for V2 1 switched capacitor circuit of this example as C1 1 o z V2(z) z1 C2 C1+C2 oo 1 .E. V 1(z) 1 1 .αz C1 . it can be rewritten as e vo 2(n)T = v2 (n1/2)T.Chapter 9 – Section 1 (2/25/03) Page 9.115 Example 9. vo (nT) = 2 C1+C2 1 C1+C2 2 CMOS Analog Circuit Design Chapter 9 – Section 1 (2/25/03) (4) © P. Vo ( z ) = (6) 2 1 2 C1+C2 C1+C2 o(z)/Vo(z) gives the desired zdomain transfer function for the Finally. Eq. Allen . 9. T.z C1+C2 CMOS Analog Circuit Design © P. The result is C1 1 C2 1 z V o(z) + z V o(z).Continued φ2: (n0. This can be done term by term using the sequence shifting property given as (5) v(nn1)T ↔ zn1V(z) .Continued zdomain Analysis: The next step is to write the zdomain equivalent expression for Eq.
Frequency Response of Example 9.2003 Page 9. Solution The first step is to replace z in Hoo(z) of Ex.2003 .13 Use the results of the previous example to find the magnitude and phase of the discrete time frequency response for the switched capacitor circuit of Example 3.tan1 (3) Arg (1+α)cos(ωT)α = .E. The phase shift of Eq.1+α CMOS Analog Circuit Design © P. The magnitude of Eq.116 DiscreteFrequency Domain Analysis Relationship between the continuous and discrete frequency domains: z = e jω T Illustration: j Continuous time frequency response =∞ =0 1 Discrete time frequency response Imaginary Axis +j1 r=1 =∞ = ∞ = ∞ Continuous Frequency Domain j1 Discrete Frequency Domain Fig. (1) is expressed as (1+α)sin(ωT) sin(ωT) 1 oo = .α (1+α)cos(ωT).tan H α cos(ωT) . Allen . (1) is found by taking the square root of the square of the real and imaginary components of the denominator to give 1 oo 2 2 H = (1+α) cos (ωT) .111 =0 +1 Real Axis CMOS Analog Circuit Design Chapter 9 – Section 1 (2/25/03) © P. The result is given below as ejωT 1 1 jωΤ = Hoo = = (1) j ω T e 1+αα ejωT (1+α)e .E. 3 by e jωT.2α(1+α)cos(ωT) + α2 + (1+α)2sin2(ωT) 1 = (1+α)2[cos2(ωT)+sin2(ωT)]+α22α(1+α)cos(ωT) 1 1 (2) = 1+2α+α2 2α(1+α)cos(ωT) = 1+2α(1+α)(1cos(ωT)) .14 .α +j(1+α)sin(ωT) where we have used Eulers formula to replace e jωT by cos(ωT)+jsin(ωT). Allen . 9.117 Example 9.Chapter 9 – Section 1 (2/25/03) Page 9.
E. Allen .1 = ω3dB .1 = 2πω3dB . firstorder.2003 Page 9. low pass continuous time circuit results in the following relationship which permits the design of the circuit parameter α. CMOS Analog Circuit Design Chapter 9 – Section 1 (2/25/03) © P.1 = fcτ1 . ωτ1 = (1+α)ωT (2) Solving for α gives τ1 ωc fc α = T . Substituting these approximations into the magnitude response of Eq. (2) of Ex.118 The Oversampling Assumption The oversampling assumption is simply to assume that fsignal << fclock = fc. continuous time filter. then cos(ωT) approaches 1 and sin(ωT) approaches ωT.2003 . switched capacitor circuit of Ex.1 . Therefore. 3 to have a 3dB frequency at 1kHz.1831. 2π 1 fsignal = f << T ⇒ 2πf = ω << T ⇒ ωT << 2π. The importance of the oversampling assumption is that is permits the design of switched capacitor circuits that approximates the continuous time circuit until the signal frequency begins to approach the clock frequency. CMOS Analog Circuit Design © P.Chapter 9 – Section 1 (2/25/03) Page 9.E. This means that.Design of Switched Capacitor Circuit and Resulting Frequency Response Design the firstorder. Assume that the clock frequency is 20kHz Plot the frequency response for the resulting discrete time circuit and compare with a firstorder. Solution If we assume that ωT is less than unity. Allen .15 . (3) Using the values given. 4 results in 1 1 (1) Hoo(ejωT) ≈ (1+α) α + j(1+α)ωΤ = 1 + j(1+α)ωT . low pass. low pass.28)1 =2. Comparing this equation to the simple. we see that α = (20/6.1831C1. C2 = 2.119 Example 9.
Continued Frequency Response of the Firstorder.) Analyze the circuit in the timedomain during a selected phase period. CMOS Analog Circuit Design © P.15 .E.2 0.Parallel switched capacitor resistor emulation . Low Pass Circuit: 1 Phase Shift (Degrees) 100 50 0 50 ω = 1/τ1 oo jωT Magnitude 0. 6.Seriesparallel switched capacitor resistor emulation .2 0. 3. 4. Allen .8 1 100 ω/ωc Fig.6 0.121 SUMMARY • Resistance emulation is the replacement of continuous time resistors with switched capacitor approximations . Switched Capacitor.) Identify the timedomain equation that relates the desired voltage variables.8 0.2 0 0 ω = 1/τ1 0.707 0.) Analyze the following phase period carrying over the initial conditions from the previous analysis. CMOS Analog Circuit Design Chapter 9 – Section 1 (2/25/03) © P. 5.2003 Page 9.Chapter 9 – Section 1 (2/25/03) Page 9.8 1 oo jωT Arg[H (e )] ) Arg[H(jω)] 0 0. 9. 2.4 ω/ωc 0.2003 .6 H(jω) 0.) Convert this equation to the zdomain. Allen . 7.4 0.112 Better results would be obtained if fc > 20kHz.E.6 H (e 0.Series switched capacitor resistor emulation .4 0.) Replace z by ejωT and examine the frequency response.) Solve for the desired zdomain transfer function.) The resulting equations are based on q = Cv.120 Example 9.Bilinear switched capacitor resistor emulation • Time constant accuracy of switched capacitor circuits is proportional to the capacitance ratio and the clock frequency • Analysis of switched capacitor circuits includes the following steps: 1.
9. Allen .E.22 Example 9.201 Gain and GB = ∞: Vout R1+R2 Vin = R1 Gain ≠ ∞.2 – SWITCHED CAPACITOR AMPLIFIERS CONTINUOUS TIME AMPLIFIERS Inverting and Noninverting Amplifiers R1  R2 + vOUT vIN R1 + R2 vOUT vIN Fig.2003 . the ratio of R2/R1 is 10.E.909 Vout 90. ∴ Vin = 10 101 For the inverting amplifier.2003 Page 9. Solution For the noninverting amplifier.21.Chapter 9 – Section 2 (2/25/03) Page 9. find the actual voltage gains for each amplifier.909 = .909 CMOS Analog Circuit Design © P. If Avd(0) is 1000.901 rather than 10.R1 = = s+ω GB·R1 Vin(s) R1 H s + R1+R2 © P.21 SECTION 9. 1000 Avd(0)R1/(R1+R2) = 1+9 = 100. ∴ Vin = (10) 1+90. GB ≠ ∞: GB·R1 R1+R2 ωH R +R2 R1+R2 Vout(s) 1 = s+ω R R GB · R Vin(s) = 1 1 1 H s + R1+R2 CMOS Analog Circuit Design Chapter 9 – Section 2 (2/25/03) Vout R2 = Vin R1 R1Avd(0) R2 Vout(s) R1+R2 = Vin(s) Avd(0)R1 R1 1 + R1+R2 GB·R1 R2 ωH R2 R1+R2 Vout(s) . GB = ∞: Avd(0)R1 R +R2 R1+R2 Vout(s) 1 = Avd(0)R1 Vin(s) R1 1 + R1+R2 Gain ≠ ∞. Avd(0)R1 1000 R1+R2 = 1+10 = 90.Accuracy Limitation of Voltage Amplifiers due to a Finite Voltage Gain Assume that the noninverting and inverting voltage amplifiers have been designed for a voltage gain of +10 and 10.9. Vout 100 = 9. the ratio of R2/R1 is 9.891 rather than 10. Allen .
GB. the upper 3dB frequency is given by GB·R1 ωH = R1+R2 For the noninverting amplifier with an ideal gain of +1. GB ≠ ∞: GB·C2 Vout C1+C2 C1+C2 Vin = GB·C2 C2 s + C1+C2 CMOS Analog Circuit Design Vout C1 = Vin C2 Avd(0)C2 Vout C1 C1+C2 Vin = C2 Avd(0)C2 1 + C1+C2 GB·C2 Vout C1 C1+C2 . Allen .Chapter 9 – Section 2 (2/25/03) Page 9. Solution In both cases.22 .23 Example 9.24 CHARGE AMPLIFIERS Noninverting and Inverting Charge Amplifiers C1 vIN + C2 vOUT vIN C1 + Inverting Charge Amplifier C2 vOUT Noninverting Charge Amplifier Gain and GB = ∞: Vout C1+C2 Vin = C2 Gain ≠ ∞. If the unitygainbandwidth. Allen . of the op amps are 2πMrads/sec. find the upper 3dB frequency for each amplifier. Vin = GB·C2 C2 s + C1+C2 © P. ∴ ωH = GB = 2π Mrads/sec (1MHz) For the inverting amplifier with an ideal gain of 1.2003 Page 9. GB = ∞: Avd(0)C2 Vout C1+C2 C1+C2 Vin = C2 Avd(0)C2 1 + C1+C2 Gain ≠ ∞. the value of R2/R1 is one.E.3dB Frequency of Voltage Amplifiers due to Finite UnityGainbandwidth Assume that the noninverting and inverting voltage amplifiers have been designed for a voltage gain of +1 and 1.2003 . the value of R2/R1 is zero.E. GB·1 GB ∴ ωH = 1+1 = 2 = π Mrads/sec (500kHz) CMOS Analog Circuit Design Chapter 9 – Section 2 (2/25/03) © P.
2 2 n 1 n+1 T n+ 2 Clock phasing for this example.2003 . Hoe (z) = CMOS Analog Circuit Design e V out (z) Vin (z) o C1 z 1/ 2 =  C2 © P.E. C1 e z 1 V o ( z ) z 1/2 Vout (z) =  in C2 Multiplying by z1/2 gives. C2 in Converting to the zdomain gives.+ + C1  vC2 = 0 e .+ vout (n1/2)T C2 C1 From the simplified equivalent circuit we write.25 SWITCHED CAPACITOR AMPLIFIERS Parallel Switched Capacitor Amplifier 1 2 1 vin 1 2 C2 + + vC2  vout vin 1 2 + vC2 + C1  vC1 C1 +  + C2 vout vC1 Inverting Switched Capacitor Amplifier Modification to prevent openloop operation Analysis: Find the evenodd and the eveneven zdomain transfer function for the above switched capacitor inverting amplifier. Equivalent circuit at the moment φ2 closes. C1 e o v (n1)T vout (n1/2)T = . + o vin (n1)T  + o vin (n1)T  + Simplified equivalent circuit. φ1: (n 1)T < t < (n 0.5)T o o vC 1(n 1)T = vin (n 1)T 2 1 2 1 2 t 3 n1 n. and vC2(n 1)T = 0 CMOS Analog Circuit Design Chapter 9 – Section 2 (2/25/03) © P. Allen . gives.5)T < t < nT vC2 = 0 v e t=0 .Chapter 9 – Section 2 (2/25/03) Page 9.Continued φ2: (n 0.1 n. Allen .+ out (n1/2)T Equivalent circuit: 2 vC1 = 0 .2003 Page 9. C1 e z 1/ 2 V o ( z ) V out (z) =  C in 2 Solving for the evenodd transfer function.26 o Parallel Switched Capacitor Amplifier.E. Hoe (z).
this delay is 90°. the phase shift of Hoe(e jωT) is Arg[Hoe(e jωT)] = ±180° .27 Parallel Switched Capacitor Amplifier. Substituting this relationship into Hoe(z) gives C1 e e V out(z) = C z 1 Vin(z) 2 or Hee (z) = V out(z) Vin(z) e e C1 1 =  z C 2 o o e o e CMOS Analog Circuit Design Chapter 9 – Section 2 (2/25/03) © P. • One must be careful when using switched capacitor circuits in a feedback loop because of the excess phase delay. • When the frequency is equal to 0. Allen . Hoe (e jωT) and Hee (e jωT) = V out(e jωT) o Vout( e jωT) e C1 e jωT =  C2 = V out( e jωT) Vout( e jωT) e e C1 jωT/2 = .5fc. then vin (n1)T = vin (n3/2)T which gives V in(z) = z 1/2 Vin(z) .2003 . CMOS Analog Circuit Design © P. Comments: • The phase shift of the SC inverting amplifier has an excess linear phase delay.28 Frequency Response of Switched Capacitor Amplifiers Replace z by e jωT. Allen .ωT/2 and the phase shift of Hee(e jωT) is Arg[Hee(e jωT)] = ±180° .Chapter 9 – Section 2 (2/25/03) Page 9. Hee (z). was uncharged during the previous φ2 phase period(from t = (n3/2)T to t = (n1)T). vin (n1)T.E.E. However. then the magnitude response is identical to inverting unity gain amp.C2 e If C1/C2 = R2/R1.ωT. Assume that the applied input signal.Continued Solving for the eveneven transfer function.2003 Page 9.
5)T 1 3 1 n.2003 . was unchanged during the previous φ2 phase. C1 e e z1 Vin(z) V out(z) = C 2 o → C1 H˚ee(z) = C z1 2 Comments: • Excess phase of H oe(e jωT) is ωT/2 and for H ee(e jωT) is ωT CMOS Analog Circuit Design © P.E. then we can write q2(T) . Analysis (Negative transresistance realization): v1(t) v1 RT = i (t) = i (average) 2 2 If we assume v1(t) is ≈ constant over one period of the clock. vin(n 1)T.+ vC2(n 1)T = vout(n 1)T = 0 . then.2 n1 n. Circuits: i1(t) 1 i1(t) vC(t) vC(t) i2(t) i2(t) 2 2 2 v1(t) C 1 1 v1(t) CP C 2 1 CP CP CP Positive Transresistance Realization. C2 C1 φ2: (n 0. Allen .E.29 Positive and Negative Transresistance Equivalent Circuits Transresistance circuits are twoport networks where the voltage across one port controls the current flowing between the ports.5)T < t < nT 2 1 The voltage across C2 is + C o e 1 vin(n 1)T vout(n 1/2)T = Noninverting Switched Capacitor Voltage Amplifier.Chapter 9 – Section 2 (2/25/03) Page 9. one of the ports is at zero potential (virtual ground).CvC(T/2) Cv1 1 T ⌠ = = T i2(average) = T ⌡i2(t)dt = T T T/2 Substituting this expression into the one above shows that RT = T/C Similarly. These circuits are insensitive to the parasitic capacitances shown as dotted capacitors. Typically.q2(T/2) CvC(T) . it can be shown that the positive transresistance is T/C. C2 C1 C1 o e 1/2 ˚oe(z) = z 1/2 Vin(z) → H V out(z) = C z C2 2 If the applied input signal.2 n n+ 2 n+1 The voltages across each capacitor can be written as Clock phasing for this example. CMOS Analog Circuit Design Chapter 9 – Section 2 (2/25/03) © P.210 Noninverting Stray Insensitive Switched Capacitor Amplifier Analysis: 1 1 2 2 2 t T φ1: (n 1)T < t < (n 0. o o vC1(n 1)T = vin(n 1)T 1 and vC2 vC1(t) vin 1 vout 2 o o . Negative Transresistance Realization.2003 Page 9. Allen .
(1) can be rewritten as 1 C + vo (1) (2) (3) (4) (5) © P. 5C 2 v2 2 Solution A possible solution is shown. we can write that voe1(n1/2)T = 10vo 1(n1)T and voe2(n1/2)T = 5ve 2(n1/2)T .2003 voe1(n1/2)T = 10ve 1(n3/2)T . Allen .212 Example 9.E.E.211 Inverting Stray Insensitive Switched Capacitor Amplifier Analysis: φ1: (n 1)T < t < (n 0. C2 C1 o e V in(z) → V out(z) = .5)T vC1(t) The voltages across each capacitor can vin 2 be written as vC1(n 1)T = 0 and v (n 1)T = vout(n 1)T = 0 . CMOS Analog Circuit Design e e e .5v2(n1/2)T . (2) and (3) gives e e e e ve o(n1/2)T = vo1(n1/2)T + vo2(n1/2)T = 10v1(n3/2)T . Combining Eqs. Considering 1 1 each of the inputs separately. C 2 Comments: • The inverting switched capacitor amplifier has no excess phase delay.Chapter 9 – Section 2 (2/25/03) Page 9. C1 H˚oe(z) = . or V o(z) = 10z1V1(z) .5)T < t < nT The voltage across C2 is C1 e e vin(n 1/2)T vout(n 1/2)T = . Eq. • There is no transfer of charge during φ1.Design of a Switched Capacitor Summing Amplifier Design a switched capacitor summing 10C 2 1 amplifier using the stray insensitive transresistv1 ance circuits to gives the output voltage during the φ2 phase period that is equal to 10v1 . φ2: (n 0. CMOS Analog Circuit Design Chapter 9 – Section 2 (2/25/03) © P.23 . 2 1 where v1 and v2 are held constant during a φ2φ1 period and then resampled for the next period. e Because vo 1(n1)T = v1(n3/2)T.5V2(z) . C2 o C2 o 1 2 + vC2 C1 1 1 + C2 vout vC1(t) o Inverting Switched Capacitor Voltage Amplifier.5v2.2003 Page 9. Allen .
The first will be when φ1 turns off (φ1off).+ switches have a W = 1µm M4 M1 C2 and L = 1µm and the C COL COL 1 nonoverlapping clock of 0 to M3 M2 2 1 + 5V amplitude has a rate of C COL OL rise and fall of ±0. and the third when φ2 turns off (φ2off). Allen . 9.E.E. CMOS Analog Circuit Design Chapter 9 – Section 2 (2/25/03) © P. the second when φ2 turns on (φ2on).5x109 volts/second. Allen .2003 . Solution We will break this example into three time sequences.24 – Influence of Clock Feedthrough on a Noninverting Switched Capacitor Amplifier A noninverting. The switch overlap capacitors.2003 Page 9. COL are 2 1 COL C C C OL OL OL assumed to be 100fF each M5 vC(t) vC2 and C1 = C2 = 1pF. CMOS Analog Circuit Design © P.Chapter 9 – Section 2 (2/25/03) Page 9.214 Example 9.213 NONIDEALITIES OF SWITCHED CAPACITOR CIRCUITS Switches Covered in Chapter 4. find the actual Fig. Capacitors Covered in Chapter 2. If the vin vout .29 value of the output voltage when a 1V signal is applied to the input. switched capacitor voltage amplifier 1 COL C OL is shown.
we will Fig.0 .19mV.00022V 1 COL COL We see that the influence of vin ≠ 0V is to cause the 2 1 M5 feedthrough from M1 and M2 not to cancel COL COL vC(t) COL COL v vin vout . the net error on the C1 capacitor at the end of the φ1 phase is vC1(φ1off) = 1. The error voltage is found as π109·1012 220x1018 220x1018+(0.29 = (0.498mV0.1012 (0+1.4+0) 1012 = (0.7)(1016) π109·1012 220x1018 Verror = 1012 2·110x106 .00497 + 0.4+0) M4 COL M5 vC2 + C2 + vout Fig. 9.001455)(3.215 Example 9.19mV Therefore.2003 . Allen .220x106(2.3)2 = 0.3V C1 M3 M2 2 1 Therefore. the value of βVHT2/2CL is found as COL COL βVHT2 110x106(3.00519V.7V = 3.779) . Based on this assumption.4) = 5.1012 (1+1. This voltage error will left on C2 at the end of the φ1 and is vC2(φ1off) = 0. 9. Using the previous model gives 220x1018+(0.5)(24.29 assume that feedthrough of M5 via a virtual ground is valid for the previous model given for feedthrough.017x109V/sec.220x106(1.7V = 4.498mV0. M5 will have the same feedthrough as M2 which is 5.3)2 = 1.599x109V/sec.001455)(3. M4 M1 C 2 C1 COL COL M5: M3 M2 2 1 + COL COL We must also consider the influence of M5 turning off. In order to use the previous model for M5.5)(24.C2 + completely.E.Chapter 9 – Section 2 (2/25/03) Page 9.779) .24 – Continued φ1 turning off M1: The value of VHT is given as COL COL vin M1 COL 1 1 COL COL vC(t) COL 2 COL  VHT = 5V1V0.7)(1016) Verror = 2·110x106 .24 – Continued Therefore. 2CL = 2x1012 CMOS Analog Circuit Design Chapter 9 – Section 2 (2/25/03) © P.216 Example 9.0. 2CL = 2x1012 This corresponds to the slow transition mode.528mV = 4.00519 = 1. M2 is also in the slow transition mode.E.97mV M2: The value of VHT for M2 is given as VHT = 5V0V0. CMOS Analog Circuit Design © P.2003 Page 9.4) = 5.308mV = 5.3V 2 The value of βVHT /2CL is found as βVHT2 110x106(4. Allen .
FINITE GAIN Finite Amplifier Gain Consider the noninverting switched capacitor amplifier during φ2: C1 o vin (n1)T e vout (n1/2)T Avd(0) + C2 + e vout (n1/2)T + Op amp with finite value of Avd(0) Fig.00022V φ2 turning off Finally. 9. as switch M4 turns off.00519V + C2 vc1(φ1off) = 1.00022V + 0.00519V = 1. the feedthrough of M4 onto C2 is exactly equal and opposite to the previous feedthrough by M5.998 rather than 1.24 – Continued 1 COL COL φ2 turning on 2 1 During the turnon part of φ2. The final voltage across C2. M3 and M4 will COL COL COL COL M5 vC(t) v feedthrough onto C1 and C2.E.Avd(0)C2 Comments: • The phase response is unaffected by the finite gain • A gain of 1000 gives a magnitude of 0. As a result.218 NONIDEAL OP AMPS .217 Example 9. M4 has one of its terminals at 0V.211 The output during φ2 can be written as. the value of voltage on C2 after φ2 has stabilized is C1 vC2(φ2on) = 0.2003 Page 9.2003 e . there will be feedthrough onto C2. we need only consider M3 M 2 2 1 + COL COL the feedthrough of M4 and its influence on C2. it is easy to vin vout . CMOS Analog Circuit Design © P. Since. and therefore the output voltage vout.29 Interestingly enough. the feedthrough is the same as before and is 5. Allen . is given as vout(φ2off) = vC2(φ2off) = 1. Allen . z = Hoe(z) = o C + C C 2 1 2 V in(z) 1 . However.C2 + M 4 M 1 C show that the influence of M3 and M4 will cancel 2 C1 COL COL each other for C1. C1+C2 vout(n 1/2)T C1 o in(n 1)T + v v (n 1/2)T = C2 Avd(0) C2 Converting this to the zdomain and solving for the Hoe(z) transfer function gives e out e Vout(z) C1 1/2 1 . 9.E. CMOS Analog Circuit Design Chapter 9 – Section 2 (2/25/03) © P.00519V0.Chapter 9 – Section 2 (2/25/03) Page 9. Therefore. Fig.0.19mV.0541V It is interesting to note that the last feedthrough has the most influence.
Op amp finite GB CMOS Analog Circuit Design © P.) • The clock period.2003 Page 9.Finite Bandwidth and Slew Rate Finite GB: • In general the analysis is complicated. T.219 Nonideal Op Amps .Switches . (We will provide more detail for integrators. • The settling time of the op amp must be less that T/2.E.220 • • • • • SUMMARY Continuous time amplifiers are influenced by the gain and gainbandwidth of the op amp Charge amplifiers are also influenced by the gain and the gainbandwidth of the op amp Switched capacitor amplifiers replace the resistors of the continuous time amplifier with switched capacitor equivalents The transresistor SC amplifiers can be inverting and noninverting with the positive input terminal of the op amp on ground The nonidealities of the SC amplifier include: .Chapter 9 – Section 2 (2/25/03) Page 9. should be equal to or less that 10/GB. CMOS Analog Circuit Design Chapter 9 – Section 2 (2/25/03) © P. Slew Rate: • The slew rate of the op amp should be large enough so that the op amp can make a full swing within T/2.Op amp finite gain .E.2003 . Allen . Allen .Capacitors .
2003 . (2) CMOS Analog Circuit Design © P. Allen .) R Vout Vin R1 + C2 Vout (a. Ideal Performance: NoninvertingInvertingω I jω I 1 Vout(jω) 1 ω I jω I Vout(jω) = = = = = ω Vin(jω) jω R 1C2 jω Vin(jω) jω R 1C2 jω = ω Frequency Response: Vout(jω)/Vin(jω) 40 dB 20 dB 0 dB 20 dB 40 dB (a.Chapter 9 – Section 3 (2/25/03) Page 9. Allen .s Case 3: 0 < s < ∞ ⇒ Avd(s) = ∞ in Vout(jω)/Vin(jω) Avd(0) dB Eq.) Noninverting and (b.) © P.Avd(0) GB ωI GB Vout Case 2: s → ∞ ⇒ Avd(s) = s ⇒ V ≈ s s in Vout ωI ⇒ V ≈.32 Continuous Time Integrators .E.3 – SWITCHED CAPACITOR INTEGRATORS Continuous Time Integrators Vin R1 + (a.) inverting continuous time integrators.Nonideal Performance Finite Gain: Avd(s) (s/ωΙ) Avd(s) sR1C2 ω I Vout 1 sR1C2 + 1 (s/ωΙ) + 1 = = Vin Avd(s) (s/ωΙ) Avd(s) sR1C2 s sR1C2 1 + (s/ωΙ) + 1 1 + sR1C2+1 Avd(0)ωa GB GB where Avd(s) = s+ωa = s+ωa ≈ s Vout Case 1: s → 0 ⇒ Avd(s) = Avd(0) ⇒ Vin ≈ .31 SECTION 9.) C2 R + Inverter (b. (3) Arg[Vout(jω)/Vin(jω)] ωI 180° 10Avd(0) 10ωI 135° Avd(0) 90° 45° 0° ωI Avd(0) (1) (2) (3) ω ωI ωx1 = I Avd(0) ωx2 = GB log10ω GB 10 10GB GB log10ω Eq.) CMOS Analog Circuit Design Chapter 9 – Section 3 (2/25/03) Arg[Vout(jω)/Vin(jω)] 90° ω I ω I ωI 100 10 10ωI 100ωI 0° log10ω ωI log10ω (b.E.2003 Page 9. (1) 0 dB Eq.
34 Noninverting Switched Capacitor Integrator Analysis: φ1: (n 1)T < t < (n 0. vout(n 1/2)T = C2 CMOS Analog Circuit Design © P.o2 vin (n1)T + + t=0 t=0 1 o o S1 2 vC1(t) + C1 S2 2 + vC2 S4 1 + C2 vout S3 o c2 o out Noninverting. Assume for this example that a ±6° tolerance is satisfactory.5)T vin The voltage across each capacitor is vc1(n1)T = vin(n1)T and v (n1)T = v (n1)T .2003 . Allen .33 Example 9. Solution The “idealness” of an integrator is determined by how close the phase shift is to ±90° (+90° for an inverting integrator and 90° for a noninverting integrator).Frequency Range over which the Continuous Time Integrator is Ideal Find the range of frequencies over which the continuous time integrator approximates ideal behavior if Avd(0) and GB of the op amp are 1000 and 1MHz. stray insensitive integrator.E. The actual phase shift in the asymptotic plot of the integrator is approximately 6° above 90° at the frequency 10ωI/Avd(0) and approximately 6° below 90° at GB /10. The frequency range can be found by evaluating 10ωI/Avd(0) and GB/10.+ C2 . Equivalent circuit at the moment the φ2 switches close.Chapter 9 – Section 3 (2/25/03) Page 9.E. CMOS Analog Circuit Design Chapter 9 – Section 3 (2/25/03) © P.+ vC2 = 0  vC1 = 0 + o vin (n1)T C1 2 + C1 + Simplified equivalent circuit.5)T < t < n T Equivalent circuit: o vC2 = vout (n1)T e vout (n1/2)T . Therefore the range over which the integrator approximates ideal behavior is from 10Hz to 100kHz. o vout (n1)T C e 2 vout (n1/2)T + . Assume that ωI is 2000π radians/sec. φ2: (n 0. respectively. Allen . C1 o e o vin(n 1)T + vout(n 1)T We can write that.31 . This range will decrease as the phase tolerance is decreased.2003 Page 9.
Chapter 9 – Section 3 (2/25/03) Page 9.ejωΤ/2 V in( e ) Replacing ejωΤ/2 . Allen . o C1 Vout( e jωΤ) C1 1 ejωΤ/2 j ωΤ oo H (e ) = o jωΤ = C2 e jωΤ 1 = C2 e jωΤ/2 .ejωΤ/2 by its equivalent trigonometric identity.1ωc and plot the magnitude and phase response of the noninverting continuous time and switched capacitor integrator from 0 to ωc. o C1 Vout(z) C1 z1 C1 1 o o o 1 1 z Vin(z) + z Vout(z) → Hoo(z) = 1 = o = V out(z) = C2 C2 z1 V in(z) C2 1z Replacing z by ejω Τ gives.8 1 ωI H(jω) oo jω T 0 50 100 ) 150 200 250 300 0 ωI 0.E.e.6 0.5)T If we advance one more phase period.4 0.32 . we see that the voltage at the output is unchanged.8 1 Arg[H oo(ejω T)] Phase Shift (Degrees) Arg[H(j ω )] CMOS Analog Circuit Design © P. vout(n)T = C2 Transferring this equation to the zdomain gives. i.Comparison of a Continuous Time and Switched Capacitor Integrator Assume that ωI is equal to 0. Allen .35 Noninverting Switched Capacitor Integrator .2003 Page 9.2003 .4 ω/ω c 0. Thus. the above becomes Hoo(e jωΤ ωT C1 V out(e jωΤ) C1 ejωΤ/2 ωT/2 jωΤ/2 = e ) = o jωΤ = V in( e ) C2 j2 sin(ωT/2) ωT jωTC2 sin(ωT/2) o Hoo(ejωT) = (Ideal)x(Magnitude error)x(Phase error) where ωI = C1/TC2 ⇒ Ideal = ωI/jω CMOS Analog Circuit Design Chapter 9 – Section 3 (2/25/03) © P.2 0. t = (n)T to t = (n+1/2)T.1ωc gives 1 πω/ωc jπω/ωc 1 e H(jω) = 10jω/ω and Hoo(e jωΤ) = 10jω/ωc sin(πω/ωc) c Plots: 5 Magnitude 4 3 H (e 2 1 0 0 0.2 0.Continued φ1: nT < t < (n + 0.36 Example 9. Solution Letting ωI be 0.E.6 ω/ ωc 0. we may write o e vout(n)T = vout(n1/2)T . Substituting this relationship into the previous gives the desired time relationship expressed as C1 o o o vin(n 1)T + vout(n 1)T .
Chapter 9 – Section 3 (2/25/03)
Page 9.37
Inverting Switched Capacitor Integrator Analysis: φ1: (n 1)T < t < (n 0.5)T The voltage across each capacitor is v (n 1)T = 0 and 3 o o e vc2(n 1)T = vout(n 1)T = vout(n 2)T.
φ2: (n 0.5)T < t < n T
o c1
vin
2
vC1(t) C1 S2
2
S1
1
+
vC2
S4
1
+ C2
vout
S3
Inverting, stray insensitive integrator.
Equivalent circuit:
t=0
C1 
t=0
+ 
2 2 v C1 = 0 e vin(n1/2)T
+
vC2 = e vout (n3/2)T e  + vout (n1/2)T C2 +
e vin (n1/2)T
e vC1 = 0 vout (n3/2)T C2 e vout (n1/2)T +  +  + vC2 = 0 + C1 

+ Simplified equivalent circuit.
Equivalent circuit at the moment the φ2 switches close.
Now we can write that,
C1 e e e vin(n1/2)T . (22) vout(n1/2)T = vout(n3/2)T  C2 CMOS Analog Circuit Design Chapter 9 – Section 3 (2/25/03) © P.E. Allen  2003 Page 9.38
Inverting Switched Capacitor Integrator  Continued Expressing the previous equation in terms of the zdomain equivalent gives, e C1 C1 1 C1 z Vout(z) e e 1 e ee(z) = V in(z) 1 =  → H e = V out(z) = z Vout(z)  C2 C2 1z C2 z1 V in(z) To get the frequency response, we replace z by ejωΤ giving, e jωΤ jωΤ out( e C1 e C1 ) V e jωΤ/2 j ωΤ ee j H (e ) = e jωΤ =  C2 e ωΤ 1 =  C2 e jωΤ/2  ejωΤ/2 V in( e ) jωΤ/2 Replacing e  ejωΤ/2 by 2j sin(ωT/2) and simplifying gives, e j out(e ωΤ) C1 V ωT/2 jωΤ / 2 j ωΤ ee e H (e ) = e jωΤ =  jωTC2 sin(ωT/2) V in( e ) Same as noninverting integrator except for phase error. Consequently, the magnitude response is identical but the phase response is given as Arg[Hee(e jωΤ)] = 2 + 2 . Comments: • The phase error is + for the inverting integrator and  for the noninverting integrator. • The cascade of an inverting and noninverting switched capacitor integrator has no phase error.
CMOS Analog Circuit Design © P.E. Allen  2003
π
ωΤ
Chapter 9 – Section 3 (2/25/03)
Page 9.39
A Sign Multiplexer A circuit that changes the φ1 and φ2 of the leftmost switches of the stray insensitive, switched capacitor integrator.
1 2 x
To switch connected to the input signal (S1). VC
x 2 1 y 1 2
VC
0 1
y
To the left most switch connected to ground (S2).
Fig. 9.38
This circuit steers the φ1 and φ2 clocks to the input switch (S1) and the leftmost switch connected to ground (S2) as a function of whether Vc is high or low.
CMOS Analog Circuit Design Chapter 9 – Section 3 (2/25/03)
© P.E. Allen  2003 Page 9.310
Switched Capacitor Integrators  Finite Op Amp Gain Consider the following circuit which is equivalent of the noninverting integrator at the beginning of the φ2 phase period.
o vin (n1)T
o vout (n1)T 
+
The expression for v (n1/2)T can be written as o e C1 o vout(n1)T vout(n1/2)T C1+C2 e o vin(n1)T + vout(n1)T vout(n1/2)T = Avd(0) + Avd(0) C2 C2
o e
e out
vC1 = 0  + e C1 vout (n1/2)T Avd(0) + 
o vout (n1)T Avd(0) e C2 vout (n1/2)T +  + vC2 = 0 
+
Fig. 9.310
Substituting vout(n)T = vout(n 0.5)T into this equation gives o o C1 o vout(n1)T vout(n)T C1+C2 o o vin(n1)T + vout(n1)T vout(n)T = Avd(0) + Avd(0) C2 C2 Using the previous approach to solve for the zdomain transfer function results in, o Vout(z) (C1/C2) z1 oo H (z) = o = z 1 z1 C1 1 z1 V in(z) 1 1  z + Avd(0)  Avd(0)C2 z1 + Avd(0) z1 or o Vout(z) (C1/C2) z1 HI(z) 1 = oo 1 H (z) = o = 1  z C1 C1 1 1 V in(z) 1  Avd(0)  Avd(0)C2(1z1) 1  Avd(0)  Avd(0)C2(1z1)
CMOS Analog Circuit Design © P.E. Allen  2003
Chapter 9 – Section 3 (2/25/03)
Page 9.311
Finite Op Amp Gain  Continued Substitute the zdomain variable, z, with ejωT to get H I( e jω T ) j T ω Hoo(e ) = 1 C1 C1/C2  j 1  Avd(0) 1 + ωT 2 C 2 2Avd(0) tan 2 where now HI(e jωT) is the integrator transfer function for Avd(0) = ∞. The error of an integrator can be expressed as HI(jω) H(jω) = [1m(ω)] ejθ(ω) where m(ω) = the magnitude error due to Avd(0) θ(ω) = the phase error due to Avd(0) If θ(ω) is much less than unity, then this expression can be approximated by HI(jω) H(jω) ≈ 1  m(ω)  jθ(ω) Comparing Eq. (1) with Eq. (2) gives m(ω) and θ(ω)due to a finite value of Avd(0) as 1 C1/C2 C1 and θ(jω) = m(jω) =  A (0) 1 + 2C2 2Avd(0) tan(ωT/2) vd
(1)
(2)
CMOS Analog Circuit Design Chapter 9 – Section 3 (2/25/03)
© P.E. Allen  2003 Page 9.312
Example 9.33  Evaluation of the Integrator Errors due to a finite value of Av d(0) Assume that the clock frequency and integrator frequency of a switch capacitor integrator is 100kHz and 10kHz, respectively. If the value of Avd(0) is 100, find the value of m(jω) and θ(jω) at 10kHz. Solution The ratio of C1 to C2 is found as C1 2π⋅10,000 = ω T = I 100,000 = 0.6283 . C2 Substituting this value along with that for Avd(0) into m(jω) and θ(jω) gives 0.6283 m(jω) =  1 + 2 = 0.0131 and 0.6283 θ(jω) = 2⋅100⋅tan(18°) = 0.554° . The “ideal” switched capacitor transfer function, HI(jω), will be multiplied by a value of approximately 1/1.0131 = 0.987 and will have an additional phase lag of approximately 0.554°. In general, the phase shift error is more serious than the magnitude error.
CMOS Analog Circuit Design
© P.E. Allen  2003
kT/C Noise Switched capacitors generate an Ron inherent thermal noise given by + + + + kT/C.311 . 822829.) Simple switched capacitor circuit. CMOS Analog Circuit Design (3) © P.E. Allen . the expressions in table reduce to f eπ(GB/f ) m(ω) ≈ 2π fc c † K. Martin and A. Sedra.311b is given as 2kTRon 2/Hz = = 4 kTR Volts Volt2/Rad. 8.” IEEE Trans. Noninverting Integrator C2 m(ω) ≈ ek C1+C2 θ(ω) ≈ 0 1 Inverting Integrator C2 cos(ωT) m(ω) ≈ ek 1 C1+C2 1 cos(ωT) θ ( ω ) ≈ e . on Circuits and Systems. Allen . (1).S.) Approximation of (a. 9. CAS28. capacitor: The noise voltage spectral density of Fig.2003 . “Effects of the Op Amp Finite Gain and Bandwidth on the Performance of SwitchedCapacitor Filters.2003 Chapter 9 – Section 3 (2/25/03) Page 9. The results of such an analysis can be summarized in the following table.(a. vol. (b. (2) by Eq.) An equivalent circuit for a switched Figure 9.k C1+C2 1 C2 C2 GB k1 ≈ π C1+C2 fc If ωT is much less than unity. This noise is verified as vin vin vout vout C C follows.313 Switched Capacitor Integrators ./sec.Chapter 9 – Section 3 (2/25/03) Page 9. August 1981. (a. pp.314 Switched Capacitor Circuits . (1) eR2 on on π The rms noise voltage is found by integrating this spectral density from 0 to ∞ to give ∞ vR2 on ω12dω 2kTRonπω1 kT 2kTRon ⌠ = 2 = π ⌡ω 2+ω2 = π C Volts(rms) 2 1 0 (2) where ω1 = 1/(RonC). no.Finite Op Amp GB The precise analysis of the influence of GB can be found elsewhere† .). CMOS Analog Circuit Design © P.) (b. Note that the switch has an effective noise bandwidth of 1 fsw = 4RonC Hz which is found by dividing Eq.E.
Twoport characterization of a general switched capacitor circuit.41 .E.2003 Page 9.4 – zDOMAIN MODELS OF TWOPHASE SWITCHED CAPACITOR CIRCUITS Introduction Objective: • Allow easy analysis of complex switched capacitor circuits • Develop methods suitable for simulation by computer • Will constrain our focus to twophase.allows both phases to be examined • Twoport . Approach: • Four port . nonoverlapping clocks General TwoPort Characterization of Switched Capacitor Circuits: vin(t) + vout(t) Dependent Switched Independent Unswitched Voltage Capacitor Voltage Capacitor Source Circuit Source Figure 9.315 SUMMARY • The discrete time noninverting integrator transfer function is V out(e jωΤ) C1 ωT/2 jωΤ/2 oo e H (e ) = o jωΤ = V in( e ) jωTC2 sin(ωT/2) • The discrete time inverting integrator transfer function is jωΤ C1 V out(e jωΤ) ωT/2 jωΤ/2 jωΤ ee e H (e ) = e jωΤ = .Chapter 9 – Section 3 (2/25/03) Page 9.41 SECTION 9. Allen .2003 .E. jωTC2 sin(ωT/2) V in( e ) • In general the integrator transfer function can be expressed as H(ejωT) = (Ideal)x(Magnitude error)x(Phase error) e o • Note that the cascade of an noninverting integrator with a inverting integrator has no phase error • A capacitor C and a switch (or switches) has a thermal noise given as kT/C where T is the clock period CMOS Analog Circuit Design Chapter 9 – Section 4 (2/25/03) © P. Allen .simplifies the models but not as general CMOS Analog Circuit Design © P.
9.43 Switched Capacitor FourPort Circuits And ZDomain Models† Switched Capacitor. no. zdomain Equivalent Model Simplified. vol.E. Allen .43 Positive SC Transresistance C + v1(t) φ2 + v2(t)  C Capacitor and Series Switch C(1z1) K. TwoPort zdomain Model Cz1/2 φ1 + v1(t)  φ2 C + v2(t)  Parallel Switched Capacitor φ1 + v1(t) φ2 C φ2 φ1 + v2(t)  + o V1 e V1 + + o V1 e V1 + + o V1 e V1 + + o V1 e V1 + + o V2 e V2 + + o V2 e V2 + + o V2 e V2 + + o V2 e V2 + Cz1/2 Cz1/2 + o V1  Cz1/2 + e V2  C (Circuit connected between defined voltages) + o V1 Cz1/2 + e V2  Cz1/2 C Cz1/2 Cz1/2 C Negative SC Transresistance C + φ2 v1(t) φ1 φ2 + φ1 v2(t)  (Circuit connected between defined voltages) C + + e e V1 V2 (Circuit connected between defined voltages) C(1z1) + + e e V1 V2 (Circuit connected between defined voltages) Fig.E. “Equivalent Circuits for Analysis and Synthesis of Switched Capacitor Networks.2003 † C .” Bell System Technical Journal. TwoPort Circuit FourPort.2003 Page 9. 729769.Chapter 9 – Section 4 (2/25/03) Page 9. 3. pp. 58.42 Independent Voltage Sources v*(t) v(t) Ve(z) Phase Dependent Voltage Source Vo(z) 1 2 1 2 1 2 1 2 1 2 0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5 vO(t) v(t) t/T Phase Independent Voltage Source for the Odd Phase 1 2 1 2 1 2 1 2 1 2 z1/2Vo(z) Vo(z) 0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5 ve(t) v(t) t/T Phase Independent Voltage Source for the Even Phase 2 1 2 1 2 1 2 1 2 1 Ve(z) z1/2Ve(z) 0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5 t/T CMOS Analog Circuit Design Chapter 9 – Section 4 (2/25/03) © P. Allen . CMOS Analog Circuit Design © P.R. Laker. March 1979.
2003 Page 9.44 ZDomain Models for Circuits that must be FourPort Switched Capacitor Circuit C + + v2(t) v1(t) Unswitched Capacitor C + + v2(t) v1(t) φ1 Capacitor and Shunt Switch + o V1 V1 + e Fourport zdomain Model C Cz1/2 Cz1/2 Cz1/2 Cz1/2 Simplified Fourport zdomain Model + o V2 e V2 + + o V1 e V1 + + o V1 e V1 + C Cz1/2 Cz1/2 C + o V1 e V1 + C + o V2 e V2 + + o V2 e V2 + Fig.44 C + o V2 e V2 + C CMOS Analog Circuit Design Chapter 9 – Section 4 (2/25/03) © P.2003 . Allen .E. 9.45 + vi(t) + + vo(t) = Avvi(t)  Time domain op amp model.Chapter 9 – Section 4 (2/25/03) Page 9. Allen .E. zdomain op amp model CMOS Analog Circuit Design © P.45 ZDomain Model for the Ideal Op Amp + Vio(z) Vie(z) + + Voo(z) = AvVio(z) Voe(z) = AvVie(z) + Figure 9.
the capacitor C is e e V2 V 1 charged to v1(t). Let us assume that the time reference + + for this phase is t . timeinvariant model. switched capacitor circuit.Chapter 9 – Section 4 (2/25/03) Page 9.47 e e o e e e o ZDomain. 9.2003 . + + o o Solution V1 V2 For the twoport switched capacitor circuit. 9.64a C vo v1 Fourport. v1 φ1 φ2 φ2 φ1 + v2 v3 φ2 φ1 v4 φ2 φ1 + Fig.2003 Page 9. HandAnalysis of Switched Capacitor Circuits General.46 Example 9. the capacitor is inverted and v2 can be expressed as v2(t) = vC = v1(t . Allen . V2(z) V1(z) φ1 φ2 V1(z) V2(z) e e o o + V3(z) φ2 φ1 o V4(z) φ2 φ1 e o + Vo(z) o φ2 φ1 + e V3(z) V4(z) + Vo(z) Fig9. let us sum the currents flowing away from the positive V 2 node of the fourport zdomain model in Fig. 9. model of the above circuit. φ2.46b e Simplification of the above circuit to a twoport.T/2). we observe that during the φ1 phase. This equation can be simplified as V 2 = z1/2V 1 which when translated to the time domain gives v2(t) = vC = v1(t . 9.T/2 so that the capacitor voltage is Negative SC Transresistance Model vC = v1(t .E.T/2). Cz1/2 C Cz1/2 Cz1/2 Next. timevariant. CMOS Analog Circuit Design Chapter 9 – Section 4 (2/25/03) © P. During the next phase. Allen . This equation is. Thus.43. the fourport zdomain model is equivalent to the time domain. CMOS Analog Circuit Design V2(z) φ1 V1(z) o e V3(z) φ2 + φ1 e V4(z) φ2 φ1 + Fig.E.T/2).41.V 1 ) + Cz1/2V 2 + CV 2 = 0.43 is equivalent to the twoport switched capacitor circuit. Cz1/2(V 2 .47 e φ2 φ2 φ1 Vo(z) e © P.Illustration of the Validity of the zdomain Models Show that the zdomain fourport model for the negative switched capacitor transresistance circuit of Fig.
49 Example 9. Heo(z) is found by using the relationship that V o (z) = z1/2V o (z) to get Heo(z) = V o (z) V i (z) e o o e C1 = C (1z1) . Since zdomain models use admittance. 9.48a. zdomain model for Fig.) Figure 9. (b. 9. Note that C2 and the indicated φ2 switch are modeled by the bottom row.) Modified equivalent circuit of inverting SC integrator. 9.zdomain Analysis of the Noninverting SC Integrator e Find the zdomain transfer function V o (z)/V i (z) and o o V o(z)/V i (z) of the noninverting switched capacitor integrator using the above methods. (b. 9.47.Chapter 9 – Section 4 (2/25/03) Page 9. Allen . we may use the twoport modeling approach of Fig. Summing the currents flowing to the inverting node of the op amp gives + =0 which can be rearranged to give Hee(z) = V o (z) e e e C1V i (z) e C2(1z1)V o (z) o e vi(t) e e C1 φ2 φ1 φ2 φ1 φ2 + C2 vo C1 e (a.34a using the above methods. Allen . 9. Solution First redraw Fig.49a is shown in Fig. 9.) C2(1z1) V e(z) o + z1/2Vo(z) e Vo(z) o Vi(z) V i (z) which is equal to inverting.48a is shown in Fig. we get o C1 φ1 vi(t) φ2 φ2 φ1 φ2 + C1z1/2 o C2 vo (a.43 .2003 CMOS Analog Circuit Design .34a.) C2(1z1) V e(z) o + z1/2Vo(z) e Vo(z) o Vi(z) (b.E.48 Example 9.) Modified equivalent circuit of Fig.43. 2 (b. 9.) Twoport.48b.48 .(a. Because this circuit is timeinvariant. 9. 9. We have added an additional φ2 switch to help in using Fig.) Twoport.49b. The twoport. Hoo(z) is found by using the relationship that V o (z) = z1/2V o (z) to get C1z1 o o Hoo(z) = (V o (z)/V i (z)) = C2(1z1) which is equal to zdomain transfer function of the noninverting SC integrator. zdomain model for Fig. switched capacitor integrator zdomain transfer function.zdomain Analysis of the Inverting Switched Capacitor Integrator Find the zdomain transfer function V o (z)/V i (z) and V o (z)/V i (z) of Fig.48a.2003 Page 9.43. 9. CMOS Analog Circuit Design Chapter 9 – Section 4 (2/25/03) © P.49a shows the modified equivalent circuit of Fig. 9. zdomain model for Fig.34b.42 .) Figure 9.E.34a as shown in Fig.(a.49a C1z1/2 = C (1z1) . 9. 9. Solution Fig.49 . right column of Fig 9. The resulting zdomain model for Fig. C1 z1/2V o i (z) + e C2(1z1)V o (z) =0 → Hoe(z) o = e o (V o (z)/V i (z)) e C1z1/2 = C2(1z1) . 2 © P. 9.
C1z1/2V 1 (z) .C3 + + o Vo(z) o (1) Summing the currents flowing away from the V i (z) nodes.410 Example 9.44 .C3(1z1) .E.C3z1V o (z) = 0 (3) o Solving for V o (z) gives. o o C1z1V 1 (z) C2V 2 (z) o V o (z) = C3(1z1) . Solution This circuit is timevariant because C3 is charged from a different circuit for each phase.zdomain Analysis a TimeVariant Switched Capacitor Circuit Find V o (z) and V o (z) as function of V 1 (z) and for the summing.C3z1/2V o (z) + C3V o (z) = 0 (2) Multiplying (2) by z1/2 and adding it to (1) gives o o o + C3V o (z) . The resulting zdomain model for Fig. Allen .C3z1/2V o (z) = 0 e o o e o o e o C3z1/2 C1z1/2 o Vi(z) . 9.Fourport.410a . 9. CMOS Analog Circuit Design Chapter 9 – Section 4 (2/25/03) © P. Allen . (1) by z1/2 and adding it to Eq.C3(1z1) Multiplying Eq. switched capacitor integrator of Fig. 9.Summing Integrator.2003 o o CMOS Analog Circuit Design . e V o (z) e o o e e C1z1/2V 1 (z) C2z1/2V 2 (z) = C3(1z1) . we must use a fourport model. zdomain model for Fig.2003 Page 9. 9.410b . © P.Chapter 9 – Section 4 (2/25/03) Page 9.E.410a is shown in Fig.C3z1V o (z) + C3V o (z) = 0 Solving for V o (z) gives.C1z1V 1 (z) .411 Example 9.410b. C2z1/2V 2 (z) .44 .410a. Therefore. 9. 9. (2) gives o C2V 2 (z) V1(z) V2(z) C2 Vi(z) e o  C3 e (z) Vo C3z1/2 Fig.Continued Summing the currents flowing away from the V i (z) node gives C2V 2 (z) + C3V o (z) .410a.C1z1V 1 (z) . o V 2 (z) o e o C1 φ1 v1(t) φ2 φ2 φ1 + C1 φ1 v2(t) φ2 φ1 φ2 C3 vo Fig.
6283F. Allen .” IEEE Trans. No. 1. Also. 9. switched capacitor integrator. C1z1/2 C1 C1z1/2 C2z1/2 C2z1/2 C2z1/2 C1z1/2 CMOS Analog Circuit Design C1 C2z1/2 © P. Next we replace the switched C2 1 3 5 capacitor C1 and the unswitched + +o 106V3 o Vi Vo capacitor of integrator by the z0 0 0 domain model of the second row of e e V Vi o Fig. 9. I(z) I(z) zdomain: V1(z) V2(z) ±Cz1/2 I(z) = ±Cz1/2 [V1(z) . † 4 R CMOS Analog Circuit Design Chapter 9 – Section 4 (2/25/03) © P. Note that in Figure 9.SPICE Simulation of A Noninverting SC Integrator Use SPICE to obtain a frequency domain simulation of the noninverting. 9.D.45 for the op amp and assumed that the op amp had a differential voltage gain of 106.2003 .43 and the first row of Fig. 1983.V2(z)] Fig. As the op amp gain becomes large.2 2 2 1 ±Cv3(t) i(t) Delay of T/2 + v2(t) +v3(t)  + v1(t)  Rin = ∞ T 2 + 2  Fig. on Circuits and Systems. 9.E. 9. Z0 = R Fig. Jan.2003 Page 9.6283 AssumeC2 = 1F →C1 = 0.413 Example 9. 9.411b SPICE Primitives: 1 3 V1V2 ±CV4 LosslessTransmission Line TD = T/2. C1 2πfI = ω T = I C2 fc = 0.E. addition we used Fig. CAS30.45 .411a i(t) Timedomain: T T t .412 zdomain model for noninverting switched capacitor integrator. the unswitched C’s are conductances. 4348. Assume that the clock frequency is 100kHz and design the ratio of C1 and C2 to give an integration frequency of 10kHz.412 Frequency Domain Simulation of SC Circuits Using Spice Storistors† A storistor is a twoterminal element that has a current flow that occurs at some time after the voltage is applied across the storistor. Nelin.412. the important components are indicated by the darker shading. vol. 9. Allen .411c B.4+ + 106V4 2 4 6 C2 4 to obtain Fig. v i(t) = ±C v t . “Analysis of SwitchedCapacitor Networks Using GeneralPurpose Circuit Simulation Programs. pp. Solution The design of C1/C2 is accomplished from the ideal integrator transfer function.Chapter 9 – Section 4 (2/25/03) Page 9.
PRINT AC V(6) VP(6) V(5) VP(5) .6283 X43PC2 4 3 43 DELAY G43 4 3 43 0 1 R35 3 5 1.6283 R40C1 4 0 1.0 X56PC2 5 6 56 DELAY G56 5 6 56 0 1 R46 4 6 1.E. CMOS Analog Circuit Design © P. Allen .END CMOS Analog Circuit Design Chapter 9 – Section 4 (2/25/03) © P. nonoverlapping clocks.ENDS DELAY ******************** . • If the op amp gain is large. VIN 1 0 DC 0 AC 1 R10C1 1 0 1. 9.PROBE .414 Example 9.2003 Page 9. some simplification is possible in the fourport zdomain models.45 . • The primary advantage of this approach is that it is not necessary to learn a new simulator.592 X10PC1 1 0 10 DELAY G10 1 0 10 0 0.Continued Simulation Results: 5 4 200 150 Phase Shift (Degrees) 100 50 0 50 100 150 Phase of H (jw) oo Magnitude 3 Both H 2 1 0 oe and H oo Phase of H (jw) oe 0 20 40 60 Frequency (kHz) (a. Allen .) 80 100 200 0 20 40 60 Frequency (kHz) (b.Chapter 9 – Section 4 (2/25/03) Page 9.45 .592 X40PC1 4 0 40 DELAY G40 4 0 40 0 0.0 X36NC2 3 6 36 DELAY G36 6 3 36 0 1 X45NC2 4 5 45 DELAY G45 5 4 45 0 1 EODD 6 0 4 0 1E6 EVEN 5 0 3 0 1E6 ******************** .6283 X14NC1 1 4 14 DELAY G14 4 1 14 0 0.412 is shown below.SUBCKT DELAY 1 2 3 ED 4 0 1 2 1 TD 4 0 3 0 ZO=1K TD=5U RDO 3 0 1K .2003 .Continued The SPICE input file to perform a frequency domain simulation of Fig.) 80 100 Comments: • This approach is applicable to all switched capacitor circuits that use twophase.AC LIN 99 1K 99K .415 Example 9.E.
Suyama. b. zdomain quantities can also be computed.) BuiltIn Sampling Functions . Users’ Manual for SWITCAP2. piecewise linear. Frequencydomain group delay and sensitivity analyses are also provided. CMOS Analog Circuit Design © P. The switches in the linear SCN’s are controlled by periodic clock waveforms only. linear VCVS’s.) Switching Intervals . OR. The ONOFF switches in the SC/D network may be controlled not only by periodic waveforms but also by nonperiodic waveforms from the output of comparators and logic gates. Columbia University.An arbitrary number of switching intervals per switching period is allowed. 4.2003 Page 9.417 SWITCAP .416 Simulation of Switched Capacitor Circuits Using SWITCAP† Introduction Signal SCN's or Mixed SWITCAP is a general simulation Outputs Generators SC/D Networks program for analyzing linear switched capacitor networks (SCN’s) and mixed switched capacitor/digital (SC/D) Clocks networks. 5. linear capacitors.) Both types of networks: Transient response without computing the steadystate values as initial conditions. of Elect. The independent voltage source waveforms may be continuous or piecewiseconstant. and dc sources. Dept. New York. A mixed SC/D network may contain comparators. pulse train.Pulse. NOT. exponential cosine.A singlefrequency sinusoidal input can produce a steadystate output containing many frequency components. and XNOR.) Linear SCN’s only: The transient response to any prescribed input waveform for t ≥ 0 after computing the steadystate values for a set of dc inputs for t < 0.) Frequency Domain Analyses of Linear SCN’s . † K. SWITCAP can determine all of these output frequency components for both continuous and piecewiseconstant input waveforms. Feb. Version 1. General Setup of SWITCAP Major Features 1. exponential. The output waveforms may also be sampled with a train of impulse functions for zdomain analyses.) TimeDomain Analyses of Linear SCN’s and Mixed SC/D Networks a.may be specified by the user. Allen .Major Features.E. A set of the initial condition of analog and digital nodes at t = 0. NOR.and frequencydomain analyses of linear SCN’s except for sensitivity analysis.) Network Elements ONOFF switches. and independent voltage sources. XOR. NAND. Engr.Chapter 9 – Section 4 (2/25/03) Page 9.E. NY 10027.Both the input and output waveforms may be sampled and held at arbitrary instants to produce the desired waveforms for time.. Continued 3. cosine. The durations of the switching intervals may be unequal and arbitrary.2003 . Allen .1. 1992. logic gates such as AND. 2. 6.) Various Waveforms for Time Domain Analyses . CMOS Analog Circuit Design Chapter 9 – Section 4 (2/25/03) © P.
2003 Page 9.) Finite Resistances. .Subcircuits. may be defined with symbolic values for capacitances. + v  Av SCN . Hierarchical use of subcircuits is allowed. clocks.E.Major Features. Allen . and other parameters. Op Amp Poles.418 SWITCAP .Function Generation CMOS Analog Circuit Design © P.Mixed SC/D Networks Structure of mixed SC/D networks as defined in SWITCAP2. Allen . and Switch Parasitics . .419 SWITCAP .Finite resistance is modeled with SCN’s operating at clock frequencies higher than the normal clock. Timing Threshold + + +  Logic . . . VCVS gains. CMOS Analog Circuit Design Chapter 9 – Section 4 (2/25/03) © P. Continued 7. 8.) Subcircuits .E. . Capacitors are added to the switch model to represent clock feedthrough. including analog and/or digital elements.2003 . These “resistors” permit the modeling of op amp poles.Chapter 9 – Section 4 (2/25/03) Page 9.
edu CMOS Analog Circuit Design © P.Resistors RQ RQ Ceq R= T 4Ceq RQ RQ RQ t RQ t The clock. RQ. NY 10027 suyama@elab.E. Allen . CMOS Analog Circuit Design Chapter 9 – Section 4 (2/25/03) © P.Chapter 9 – Section 4 (2/25/03) Page 9.MOS Switches MOS Transistor Switch Model: High Clock Voltage G MQ MQ MQ MQ MQ G S D Cgs S Cbs Frequency Higher than MQ clock RON MQ Cgd D Cbd More information: SWITCAP Distribution Center Columbia University 411 Low Memorial Library New York.columbia.421 SWITCAP .E. for the resistor is run at a frequency. much higher than the system clock in order to make the resistor model still approximate a resistor at frequencies near the system clock. Allen .420 SWITCAP .2003 .2003 Page 9.
E.Positive and negative conductances .Chapter 9 – Section 4 (2/25/03) Page 9.E. Allen .5 – FIRSTORDER SWITCHED CAPACITOR CIRCUITS Introduction Objective: • Examine firstorder SC circuits • Illustrate various design methods of SC circuits Approach: • Lowpass: Design using oversampled assumption and direct zdomain design • Highpass: Design using oversampled assumption and direct zdomain design • Allpass: Design using oversampled assumption and direct zdomain design CMOS Analog Circuit Design © P.Delayed conductances (storistor) .422 SUMMARY • Can replace various switchcapacitor combinations with a zdomain model • The zdomain model consists of: . Allen .2003 .51 SECTION 9.2003 Page 9.Independent sources • These models permit SPICE simulation of switched capacitor circuits • The type of clock circuits considered here are limited to twophase clocks CMOS Analog Circuit Design Chapter 9 – Section 5 (2/25/03) © P.Controlled sources .
B0 = 1 . 9. firstorder low pass circuit.51a.C1 + vi(t) vo(t) φ1 φ2 φ2 α C φ1 2 1 φ1 φ2 C1 vo(t) α1C1 φ1 vi(t) α1C1 φ2 φ1 + (a.52 General. (b.2003 .52 .51 . Allen .) Noninverting. a0 = 0 ⇒ High Pass. Low Pass Circuit α2C1 φ2 φ1 φ1 φ2 vo(t) φ2 φ2 φ1 .51b. a0 ≠ 0 and a1 ≠ 0 ⇒ All pass Note that the zero can be in the RHP or LHP.E. 9.zdomain model of Fig.α1C1z1/2V i (z) + C1(1z1)V o (z) o o Solving for V o (z)/V i (z) gives α1z1 o V o (z) α1z1 1+α2 = = o 1 z1 V i (z) 1 + α2 .53 Noninverting.) (b.1+α2 Vo(z) e C1α2 C1α1z1/2 C1(1z1) V e(z) o Vi(z) o =0 + z1/2Vo(z) e Vo(z) o Figure 9. Allen .B z1 0 CMOS Analog Circuit Design Chapter 9 – Section 5 (2/25/03) © P.) Equivalent circuit of Fig.z 1 . A general firstorder transfer function in the zdomain: zA1 ± A0 A1 ± A0z1 H(z) = z . FirstOrder.2003 Page 9.E.(a. Equating the above to H(z) of the previous page gives the design equations as α1 = A0/B0 and α2 = (1B0)/B0 CMOS Analog Circuit Design © P. Transfer function: Summing currents flowing toward the inverting op amp terminal gives o e e α2C1V o (z) .) Figure 9.Chapter 9 – Section 5 (2/25/03) Page 9. FirstOrder Transfer Functions A general firstorder transfer function in the sdomain: sa1 ± a0 H(s) = s + b0 a1 = 0 ⇒ Low pass.
0628 and α1 = 0.51a. (2). It can be shown that. FirstOrder.54 Inverting. fc.z1 = z1 V i (z) 1 .55 Example 9. Solution Assume that the clock frequency. we get (3) V Equating Eq.2003 Page 9. if sT<<1. α 1 α 1 1+α2 = 1 + α2 . (3) to the specifications gives α1 = 10α2 and α2 = ω3dB/fc ∴ α2 = 6283/100. is much larger than the 3dB frequency. Use a clock frequency of 100kHz. 9. Based on this assumption. we note from Eq. firstorder low pass circuit.C1 + Equivalent circuit. α2C1 φ2 φ1 φ1 φ2 vo(t) φ2 φ1 φ1 . Making these substitutions in Eq.2003 V o (s) o α1 α 1/α 2 ≈ α2 + sT = 1 + s(T/α2) . (1) that 1z1 ≈ sT.z1 o V (z) o (2) Next.6283 o i (s) CMOS Analog Circuit Design © P. we approximate z1 as z1 = esT ≈ 1.E.Design of a Switched Capacitor FirstOrder Circuit Design a switched capacitor firstorder circuit that has a low frequency gain of +10 and a 3dB frequency of 1kHz. Allen .000 = 0. Low Pass Circuit An inverting low pass circuit can be obtained by reversing the phases of the leftmost two switches in Fig.Chapter 9 – Section 5 (2/25/03) Page 9. vi(t) vo(t) φ2 φ2 φ2 α2C1 φ1 φ1 φ2 C1 vo(t) α1C1 φ2 vi(t) α1C1 φ1 φ1 + Inverting. Give the value of the capacitor ratios α1 and α2.sT + ··· (1) Rewrite the zdomain transfer function as V o (z) i α1z1 = α2 + 1. In this example. Furthermore.1+α 2 Equating to H(z) gives the design equations for the inverting low pass circuit as 1B A1 0 α1 = B0 and α2 = B 0 e V o (z) e CMOS Analog Circuit Design Chapter 9 – Section 5 (2/25/03) © P.E. then z1 ≈ 1.51 . the clock frequency is 100 times larger so this assumption should be valid. Allen .
) High or low frequency boost circuit. α1+α3 1. α1(1z1)V o (z) + α2V o (z) + (1z1)V i (z) = 0 (1) Solving for the Hee(z) transfer function gives α1 e V o (z) α1(1z1) α2+1 (1z1) (2) Hee(z) = e = α +1z1 = 1 2 1 V i (z) 1 . High Pass Circuit α2C φ2 φ1 φ1 α1C .) Version of Fig.) Modification of (a.2003 . 9.zdomain model for Fig.55b.53.) (a. then the above becomes Since Vo i (z) = z i o Vi(z) e + e z1/2Vo(z) 1 1 e Ve o(z) α2+1z = α1z V i (z) . (b.A0 ⇒ α = α = and α = Hee(z) = α +(1z1) = α2+1 1 2 B0 3 B0 B0 z1 2 1α2+1 CMOS Analog Circuit Design © P.Chapter 9 – Section 5 (2/25/03) Page 9.57 FirstOrder. (b.) Figure 9.) (b. Allen .(a.55 .E.α +1 z 2 Equating Eq.α3(1z 1)V i (z) Solving for Hee(z) gives Figure 9. Allpass Circuit α3C φ2 α2C φ1 φ1 + φ2 vo(t) φ1 vi(t) α1C φ2 φ1 φ2 C vi(t) φ1 α C φ2 1 φ1 φ2 + C α3C φ2 φ2 α2C φ1 φ1 φ2 vo(t) Transfer function: (a. © P.) Summing the currents Figure 9. 9.) Switchedcapacitor.zdomain model for Fig.C + α2C φ2 φ1 φ1 φ2 vo(t) Transfer function: Summing currents at the inverting input node of the op amp gives e e (b. 9.2003 Page 9.E.α3 z1 1B0 α1z1α3(1z1) α 3 A1+A0 .54 .(a.56 FirstOrder.53a that constrains the charging of C1 to the φ2 phase. high pass circuit. Allen .C vi(t) φ2 vo(t) + vi(t) α1C φ2 .53 .56 . (2) to H(z) gives.) to simplify flowing into the the zdomain modeling inverting input of the α3(1z1) α2 op amp gives e e 1 e 1 e o α1z1/2 (1z1) V e(z) α1z1/2Vo Vi(z) i (z)+α3(1z )V i (z)+α2Vo(z)+(1z )Vo(z) = 0 Vo(z) o 1/2Ve(z). 1B0 A1 α1 = B0 and α2 = B 0 CMOS Analog Circuit Design Chapter 9 – Section 5 (2/25/03) e α2 α1(1z1) e (1z1) e (z) Vo Vo(z) o Vi(z) + z1/2Vo(z) e Figure 9.
Chapter 9 – Section 5 (2/25/03)
Page 9.58
Example 9.52  Design of a Switched Capacitor Bass Boost Circuit Find the values of the capacitor ratiosα1, α2, 20 and α3 using a 100kHz clock for Fig. 9.55 dB that will realize the asymptotic frequency response shown in Fig. 9.57. 0 10Hz 100Hz 1kHz 10kHz Solution Frequency Since the specification for the example is Figure 9.57  Bass boost response for Ex. 9.52. given in the continuous time frequency domain, let us use the approximation that z1 ≈ 1 and 1z1≈ sT, where T is the period of the clock frequency. Therefore, the allpass transfer function can be written as sTα3 + α1 α1 sTα3/α1  1 Hee(s) ≈ sT + α2 =  α2 sT/α + 1 2 From Fig. 9.57, we see that the desired response has a dc gain of 10, a righthalf plane zero at 2π kHz and a pole at 200π Hz. Thus, we see that the following relationships must hold. α1 α1 α2 = 10 , = 2000 π , and α2 Tα 3 T = 200π From these relationships we get the desired values as 2000π 200π α1 = fc , α2 = fc , and α3 = 1
CMOS Analog Circuit Design Chapter 9 – Section 5 (2/25/03) © P.E. Allen  2003 Page 9.59
Practical Implementations of the FirstOrder Circuits
φ1 α 1C φ1 vi(t) φ1 α 1C φ2 C1 φ2 φ1 φ2 φ2 φ1 φ2 φ1 φ2 + vo(t) vi(t) vo(t) α 2C φ2 φ1 α 1C φ2 φ2 α 1C φ2 φ1 φ2 φ1 φ2 + vo(t) vi(t) vo(t) α 2C φ2 φ1 φ1 α 3C φ2 φ1 φ1 φ2 φ2 φ1 α 1C φ2 α 1C φ2 + +C φ1 φ2 + vo(t) vo(t) φ 2 α 2C φ2 φ1
α 2C C
α 2C C
α 3C
φ 2 α 2C
+ +
+ +
C
C
C
φ1 φ1 (c.) (a.) (b.) Figure 9.58  Differential implementations of (a.) Fig. 9.51, (b.) Fig. 9.53, and (c.) Fig. 9.55.
Comments: • Differential operation reduces clock feedthrough, common mode noise sources and enhances the signal swing. • Differential operation requires op amps or OTAs with differential outputs which in turn requires a means of stabilizing the output common mode voltage.
CMOS Analog Circuit Design
© P.E. Allen  2003
Chapter 9 – Section 5 (2/25/03)
Page 9.510
SUMMARY • Examined firstorder SC circuits (lowpass, highpass, allpass) • Illustrated design by assuming the clock frequency is higher than the signal frequency (sdomain design) • Illustrated direct design by equating coefficients between the desired and design in the zdomain (requires the specifications in the zdomain)
CMOS Analog Circuit Design Chapter 9 – Section 6 (2/25/03)
© P.E. Allen  2003 Page 9.61
SECTION 9.6 – SECONDORDER SWITCHED CAPACITOR CIRCUITS
Why SecondOrder Circuits? They are fundamental blocks in switched capacitor filters. Switched Capacitor Filter Design Approaches • Cascade design
Vin SecondOrder Circuit Stage 1 FirstOrder Circuit Stage 1 SecondOrder Circuit Stage 2 (a.)
SecondOrder Circuit Stage n
Vout
SecondSecondVout Order Order Circuit Circuit Stage 2 Stage n (b.) Figure 9.61  (a.) Cascade design when n is even. (b.) Cascade designwhen n is odd. Vin
• Ladder design Also uses first and secondorder circuits There are also other applications of first and secondorder circuits: • Oscillators • Converters
CMOS Analog Circuit Design © P.E. Allen  2003
Chapter 9 – Section 6 (2/25/03)
Page 9.62
Biquad Transfer Function A biquad has two poles and two zeros. Poles are complex and always in the LHP. The zeros may or may not be complex and may be in the LHP or the RHP. Transfer function: (sz1)(sz2) Vout(s) (K2s2+ K1s + K0) = K Ha(s) = Vin(s) = (sp )(sp ) ωo 1 2 s2 + Q s+ ωo2
jω
ωo
σ
ωo 2Q
Low pass: zeros at ∞ Bandstop: zeros at ±jωo High pass: zeros at 0 Allpass: Poles and zeros are complex Bandpass: One zero at 0 and the other at ∞ conjugates
CMOS Analog Circuit Design Chapter 9 – Section 6 (2/25/03)
© P.E. Allen  2003 Page 9.63
LowQ, Switched Capacitor Biquad Development of the Biquad: Rewrite Ha(s) as: ω os s2Vout(s) + Q Vout(s) + ωo2Vout(s) = (K2s2 + K1s + K0)Vin(s) Dividing through by s 2 and solving for Vout(s), gives ωo 1 1 2V (s)) Vout(s) = s ( K + K s ) V ( s ) + V ( s ) + ( K V ( s ) + ω 1 2 in o out Q out s 0 in If we define the voltage V1(s) as K 1 0 V1(s) = s ωo Vin(s) + ωoVout(s) , then Vout(s) can be expressed as ω 1 o ( K + K s ) V ( s ) + V ( s ) ω V ( s ) Vout(s) = s 1 2 in o 1 Q out Synthesizing the voltages V1(s) Vin(s) K2 CA=1 and Vout(s), gives Vout(s) 1/ωo
Vin(s) ωo/K0 + Vin(s) 1/K1 V1(s) Vout(s) Q/ωo V1(s) 1/ωo
CB=1 + Vout(s)
(a.) (b.) Figure 9.62  (a.) Realization of V1(s). (b.) Realization of Vout(s).
CMOS Analog Circuit Design © P.E. Allen  2003
62b. φ2 φ2 φ1 α 2C 1 e V1(z) φ1 φ2 α 5C 2 α 6C 2 φ2 C2  φ2 φ1 Vout(z) e  + If we assume that ωT<<1.62a.65 o e LowQ. Switched Capacitor Biquad . From these circuits we can write that: α1 e α2 e e V 1 (z) = . Hee(s) as follows.sT Vin(s) . 9.2003 + . Switched Capacitor Biquad . CMOS Analog Circuit Design Chapter 9 – Section 6 (2/25/03) © P.(a. 9. T These equations can be combined to give the transfer function.63 together gives e α 1C 1 the desired.) Switched capacitor realization of Fig. α 4C 2 e φ1 φ1 then 1z1 ≈ sT and V1(z) α 3C 2 e andVout(z) can be Figure 9.E.sT Vout(s) = s in T Vout(s) T and α5 e α6 e 1 α4 e e ( + s α ) V ( s ) V ( s ) + V out(s) ≈ s in 1 3 T T Vout(s) .Low Q. lowQ. switched capacitor.E. approximated as α1 e α2 e α2 e 1 α1 e e V ( s ) + V 1 (s) ≈ . biquad realization. Note that we multiplied the V 1 (z) input of Fig.1z1 Vout(z) and α4 e α5z1 e α6 e e e V out(z) = α3 Vin(z) .) Switched capacitor realization of Fig.64 LowQ. (b.63b by z1/2 to convert it to V 1 (z).) Figure 9.) (b.Chapter 9 – Section 6 (2/25/03) Page 9. biquad C1 Vin(z) realization.63 .Continued Connecting the two circuits of Fig.1z1 Vin(z) . sα4 α1α5  α3s2 + T + T2 Hee(s) ≈ sα6 α2α5 s2 + T + T2 CMOS Analog Circuit Design © P. Allen .1z1 Vin(z) + 1z1 V 1(z) .64 .2003 Page 9. Allen .Continued Replace the continuous time integrators with switched capacitor integrators to get: Vin(z) Vout(z) φ2 φ1 e Vin(z) φ2 φ1 e e α3C2 α4C2 φ2 φ1 φ2 α2C1 φ2 C1  V1(z) e Vin(z) o e C2 V e (z) out  α1C1 φ1 + α5C2 φ1 φ2 V1(s) e + α6C2 φ2 φ1 φ1 Vout(z) (a. 9.1z1 Vout(z) . 9.
K0 = K2 = 0. Setting K0 = K2 = 0.83. and α6 = Q .0628/0. (Note that this number will decrease as the clock frequency becomes closer to the signal frequencies. α2 = α5 = 0.Chapter 9 – Section 6 (2/25/03) Page 9. Solution From the previous slide we have ωoT K0T α1 = ωo . αminC. switched capacitor biquad is restricted to Q < 5.E. α2 = α5 = ωoT. Q = 2. 9. The sum of the normalized capacitors associated with each op amp will be the sum of the capacitance connected to that op amp.2003 Page 9.61. including the integrating capacitor. and K1 = 2πfo/Q (a bandpass filter).916. α3 = K2. Σ capacitors connected to the second op amp = 0. Biquad Assume that the specifications of a biquad are fo = 1kHz. α1 = ωo . Switched Capacitor Biquad .0314 + 1/0.0314. Allen .) CMOS Analog Circuit Design © P. Largest capacitor ratio: If Q > 1 and ωoT << 1. CMOS Analog Circuit Design Chapter 9 – Section 6 (2/25/03) © P. Thus. and K1 = 2πfo/Q and letting fo = 1kHz.64 and determine the maximum capacitor ratio and the total capacitance assuming that C1 and C2 have unit values. Sum of capacitance: To find this value. Therefore. 1 n ΣC = αmin ∑αi i =1 where there are n capacitors connected to the op amp inverting terminal.Continued sα4 α1α5 2  α s + 3 T + T2 (K2s2+ K1s + K0) Equating Hee(s) to Ha(s) gives = ωo sα6 α2α5 s2 + Q s+ ωo2 s2 + T + T2 ωoT K0T which gives.85.0628. the lowQ.0628 + 1 = 16. The largest capacitor ratio is α4 or α6 and is 1/31. Q = 2 gives α1 = α3 = 0. normalize all of the capacitors connected or switched into the inverting terminal of each op amp by the smallest capacitor.2003 . α2 = α5 = ωoT. The clock frequency is 100kHz. Design the capacitor ratios of Fig. LowQ. Σ capacitors connected to the input op amp = 1/0. and α4 = α6 = 0.0314 + 2 = 35. α3 = K2.E. Allen .67 Example 9. and α6 = Q . the largest capacitor ratio is α6. α4 = K1T. For this reason. the total biquad capacitance is 52.Design Of A Switched Capacitor. α4 = K1T.76 units of capacitance.66 LowQ.
1z1 Vout(z) .1z1 Vout(z) and α4 e α6 α5z1 e e e e V out(z) = α3 Vin(z) . Allen . Q(v1) = Q(v1’) so that C1’ = C1/k1 and C2’ = C2/k1.α4 . α6 = b21. The choice above of α2 = α5 results in a nearoptimally scaled dynamic range realization.Chapter 9 – Section 6 (2/25/03) Page 9. one could let α2 = α5 which makes the integrator frequency of both integrators in the feedback loop equal. α1C1 + C1 v1 α2C2 + C2 The charge associated with v1 is: Q(v1) = C1v1 + α2C2v1 Suppose we wish to scale the value of v1 by k1 so that v1’ = k1v1.2)z + 1 e 6 2 5 6 V in(z) A general zdomain specification for a biquad can be written as a2z2 + a1z + a0 H(z) = .b z2 + b z + 1 2 1˚ Equating coefficients gives α3 = a0. Allen . For example. If the voltage at the output node of an op amp in a switched capacitor circuit is to be scaled by a factor of k. and α2α5 = b2+b1+1 Because there are 5 equations and 6 unknowns. Biquad Combining the following two equations.α .E.2003 Page 9. CMOS Analog Circuit Design Chapter 9 – Section 6 (2/25/03) © P.2003 . One approach would be to select α5 = 1 and solve for the remaining capacitor ratios. α1α5 = a2+a1+a0.E.1z1 Vin(z) .(1 + α )z2 + (α α . Therefore.2α3)z + α3 V out(z) ee = H (z) = .68 ZDomain Characterization of the LowQ. α1 e α2 e e V 1 (z) = . an additional relationship can be introduced. α4 = a2a0. gives. e (α3 + α4)z2 + (α1α5 . This can be done by voltage scaling.69 Voltage Scaling It is desirable to keep the amplitudes of the output voltages of the two op amps approximately equal over the frequency range of interest. This scaling is based on keeping the total charge associated with a node constant. then all switched and unswitched capacitors connected to that output node must be scaled by a factor of 1/k.1z1 Vin(z) + 1z1 V 1(z) . Alternately. CMOS Analog Circuit Design © P. Q(v1’) = C1v1’ + α2C2v1’ = C1k1v1 + α2C2k1v1 But.
9.E. Note that we multiplied the V 1 (z) input of Fig.2003 o e .1z1 Vin(z) .66 .) (b. 1 Vout(s) = .α4Vout(z) and α5z1 e e e V out(z) = α6 Vin(z) + 1z1 V 1(z) .2003 Page 9.(a.s K2sVin .s ωo + ωo s Vin(s) + ωo + Q Vout(s) Synthesizing these equations: Vout(s) 1/ωo Vout(s) 1/Q Vin(s) K1/ωo Vin(s) ωo/K0 CA=1 Vin(s) K2 + V1(s) V1(s) 1/ωo CB=1 + Vout(s) Realization of V1(s). 9. From these circuits we can write that: α1 e α2 e e e e V 1 (z) = .610 HighQ. CMOS Analog Circuit Design © P. Development of such a biquad: Reformulate the equations for V1(s) and Vout(s) as follows.ωoV1(s) and K K1 1 s 0 V1(s) = .E.611 HighQ.65a.) Switched capacitor realization of Fig.1z1 Vout(z) .66b by z1/2 to convert it to V 1 (z).) Switched capacitor realization of Fig. 9. (b.65b.Chapter 9 – Section 6 (2/25/03) Page 9. Switched Capacitor Biquad . Allen .Continued Replace the continuous time integrators with switched capacitor integrators to get: e Vout (z) α4C1 α3C1 α2C1 φ2 φ1 φ 2 Vin(z) Vout(z) e Vin(z) φ2 φ1 e e C1 + V1(z) Vin(z) V1(s) φ1 φ2 o e e α6C2 φ α5C2 2 φ1 C2 V e (z) out + α1C1 φ1 (a.) Figure 9. Realization of Vout(s). CMOS Analog Circuit Design Chapter 9 – Section 6 (2/25/03) © P. Allen . Switched Capacitor Biquad Desired: A biquad capable of realizing higher values of Q without suffering large element spreads.α3Vin(z) .
Continued Connecting the two circuits of Fig. the largest capacitor ratio is α2 (α5) or α4 depending on the values of Q and ωoT. approximated as e 1 α1 1 α2 e e V (s) + s α + s α V 1 (s) ≈ .E.66 together gives α3C1 the desired. switched capacitor. e α C C Vin(z) 1 1 α2C1 α4C1 α5C2 φ1 φ2 φ1 φ2 φ2 φ1 1 Ve (z) 1 C2 + Vout(z) e If we assume that ωT<<1. Switched Capacitor Biquad . and α6 = K2 . These equations can be combined to give the transfer function. α2 = α5 = ωoT. highQ biquad realization.2003 Page 9. Hee(s) as follows.612 HighQ.Continued Equating Hee(s) to Ha(s) gives sα3α5 α1α5 2 α6s + T + T2 (K2s2+ K1s + K0) = ωo sα4α5 α2α5 s2 + Q s+ ωo2 s2 + T + T2 which gives.High Q. Allen .67 . α3 = ωo. e then 1z1 ≈ sT and V1(z) e andVout(z) φ2 φ1 φ1 φ 2 + α6C2 can be Figure 9. Switched Capacitor Biquad . Largest capacitor ratio: If Q > 1 and ωoT << 1. CMOS Analog Circuit Design © P. 9.2003 .E. K0T K1 1 α1 = ωo .Chapter 9 – Section 6 (2/25/03) Page 9.613 HighQ.s in 3 4V out(s) s T T and α5 e 1 e e V out(s) ≈ s ( s α ) V ( s ) in 6 T V 1(s) . Allen . sα3α5 α1α5 2 α s + + T2  6 T ee H (s) ≈ sα4α5 α2α5 s2 + T + T2 CMOS Analog Circuit Design Chapter 9 – Section 6 (2/25/03) © P. biquad realization. α4 =Q.
103.0628 + 1 = 16. 9. and K1 = 2πfo/Q (a bandpass filter). The largest capacitor ratio is α2 or α5 and is 1/15.b z2 + b z + 1 = z2 + (b1/b2)z + (b0/b2) 2 1˚ Equating coefficients gives a2 a2a0 a2+a1+a0 b1+1 1 α6 = b2. Σ capacitors connected to the input op amp = 1/0. one could let α2 = α5 which makes the integrator frequency of both integrators in the feedback loop equal. Alternately. Allen .1/0.614 Example 9.α α ) e 4 5 2 5 4 5 V in(z) A general zdomain specification for a biquad can be written as a2z2 + a1z + a0 (a2/b2)z2 + (a1/b2)z + (a0/b2) H(z) = . K0T K1 1 α1 = ωo . α2 = α5 = ωoT. the total biquad capacitance is 36. an additional relationship can be introduced. e α6z2 + (α3α5 .02 units of capacitance. Σ capacitors connected to the second op amp = 1/0.64 and determine the maximum capacitor ratio and the total capacitance assuming that C1 and C2 have unit values. α3 = ωo. and K1 = 2πfo/Q (a bandpass filter) gives α1 = α6 = 0.2α6)z + (α6 .62 .2003 Page 9.E.2003 . Solution From the previous slide we have.z2 + (α α + α α .0628 + 2(0. α1 e α2 e e e e V 1 (z) = . CMOS Analog Circuit Design Chapter 9 – Section 6 (2/25/03) © P. Allen .α3α5) V out(z) ee = H (z) = . The clock frequency is 100kHz. K0 = K2 = 0.α4Vout(z) and α5z1 e e e V out(z) = α6 Vin(z) + 1z1 V 1(z) gives. Q = 10 and setting K0 = K2 = 0. α4α5 = 1. Design the capacitor ratios of the highQ biquad of Fig. Therefore.916. Biquad Assume that the specifications of a biquad arefo = 1kHz. CMOS Analog Circuit Design © P.E. Q = 10. α4 =Q.Chapter 9 – Section 6 (2/25/03) Page 9.1z1 Vout(z) . α2 = α5 = 0. α3α5 = b2 . Biquad Combining the following two equations. and α3 =α4 = 0.α1α5 .Design of a Switched Capacitor.2)z + (1 .α3Vin(z) . α1α5 = b2 .1z1 Vin(z) . Using fo = 1kHz.b2 and α2α5 = 1 + 2 Because there are 5 equations and 6 unknowns.0628. HighQ.615 ZDomain Characterization of the HighQ.1.92.0628) + 1 = 20. and α6 = K2 . One approach would be to select α5 = 1 and solve for the remaining capacitor ratios.
AE) + z (AC + AE .FleischerLaker.2BD) + BD and V 1 z2(EJ .GB) e = z2(DB .Chapter 9 – Section 6 (2/25/03) Page 9. Allen .2BD) + BD V in CMOS Analog Circuit Design © P.HB) + z1(GB + HB .zdomain equivalent circuit for the FleischerLaker biquad of Fig. G ^ = H+L .2003 Page 9. Switched Capacitor Biquad† E K φ2 C φ2 Vin(z) φ2 φ1 e G φ2 D + V1(s) φ1 φ2 e A F φ2 φ1 B + Vout(z) e H φ1 I J φ1 φ2 φ1 L φ2 Figure 9. 9.2003 e e . e ^˚˚A ^)z2˚˚[D( Vout(z) ^)˚˚AG (D˚ J ˚H ˚I^˚+˚ ˚ J ˚^]z˚˚DI ˚^ = e Vin(z) (DB˚˚AE)z2˚˚[2DB˚˚A(C˚+˚E)˚+˚DF]z1˚+˚D(B˚+F) e ^˚˚BH ^+˚ V1(z) (E˚ ^)˚+˚FH ^)˚˚CJ ^(F+B)] J ˚^)z2+[B(˚ G H ˚^˚˚E( ˚I^+˚ J ˚^]z1˚˚[ ˚I^(C+E)˚˚ ˚G = e (DB˚˚AE)z2˚˚[2DB˚˚A(C˚+˚E)˚+˚DF]z1˚+˚D(B˚+F) Vin(z) where CMOS Analog Circuit Design Chapter 9 – Section 6 (2/25/03) ^ = G+L.DI) + DI e = 2 1 V in z (DB .E.AE) + z1(AC + AE .617 ZDomain Model Of The FleischerLaker Biquad E(1z1) C K(1z1) D(1z1) V e(z) Az1 1 + I Jz1 L(1z1) F B(1z1) + e (z) Vout G e Vin(z) Hz1 Figure 9.HA) + z1(AG .E.69 . Allen .68 . Type 1E Biquad (F = 0) V out z2(JD .CJ .616 FleischerLaker.DJ .EJ) + (IC + IE .68. switched capacitor biquad.IE . H ^ = I+K I and ^ = J+L J © P.
003 and G = 0.9485z1 + 1 Solution Let us begin by selecting a Type 1E FleischerLaker biquad.Design of a Switched Capacitor. Equating the denominator terms of Eq. gives BD = 1 BDAE = 0.Chapter 9 – Section 6 (2/25/03) Page 9.003 JD = 0.0396 AC+AE2BD = 1. Type 1F Biquad (E = 0) z2(JD .0119 Because we have selected D = A = 1. E = 0.619 e e Example 9.012.2BD .Continued E(1z1) C K(1z1) D(1z1) V e(z) Az1 1 + I Jz1 L(1z1) F B(1z1) + e Vout (z) G e Vin(z) Hz1 Figure 9.68.9485 → AC+AE = 0.0515 → AC = 0.009 DJHA = 0. FleischerLaker Biquad Use the FleischerLaker biquad to implement the following zdomain transfer function which has poles in the zdomain at r = 0.DI) + DI V out = e 2 1 V in z DB + z (AC . 9.003z2 + 0. (1) with the numerator of H(z) gives DI = 0.69 .9604z2 .003 H(z) = 0.0396. 0. Equating the numerator of Eq.006 → AGDJ = 0.003. we get B = 1. Allen .98 and θ = ±6.0119. CMOS Analog Circuit Design © P.1.006z1 + 0. (1) with the denominator of H(z).DF) + (BD + DF) V in CMOS Analog Circuit Design Chapter 9 – Section 6 (2/25/03) © P.2003 Page 9.DF) + (BD + DF) and V 1 z2HB + z1(GB + HB + HF .HA) + z1(AG . and C = 0.E.63 . J = 0.CJ) + (IC + GF .2003 .003 AG = 0.012 Picking D = A = 1 gives I = 0. If any capacitor value was negative.E. Allen .DJ .003 If we arbitrarily choose H = 0.2BD .zdomain equivalent circuit for the FleischerLaker biquad of Fig. we get DI = 0.618 ZDomain Model of the FleischerLaker Biquad .003 AGDJDI = 0. the procedure would have to be changed by making different choices or choosing a different realization such as Type 1F.9604 → AE = 0.GB) e = z2DB + z1(AC .2°.
620 Example 9.Continued Since each of the alphabetic symbols is a capacitor. Allen .E.Chapter 9 – Section 6 (2/25/03) Page 9.9604 will cause large capacitor ratios. the largest capacitor ratio will be D or A divided by I or J which gives 333.63 .2003 . CMOS Analog Circuit Design Chapter 9 – Section 6 (2/25/03) © P.E.Assume that fc>>fsig and using continuous time specifications and design . If we switch to the Type 1F. Allen . The large capacitor ratio is being caused by the term BD = 1. This example is a case where both the E and F capacitors are needed to maintain a smaller capacitor ratio.2003 Page 9.Direct design – equate the zdomain transfer function to a zdomain specification and solve for the capacitor ratios CMOS Analog Circuit Design © P.621 • • • • SUMMARY The secondorder switched capacitor circuit is a very versatile circuit The secondorder switched capacitor circuit will be very useful in filter design LowQ biquad is good for Qs up to about 5 before the elements spreads become large Design methods: . the term BD = 0.
Chapter 9 – Section 7 (2/25/03) Page 9. Three basic properties of filters. (b.) Stopband frequency = ωSB. we develop filter approximations which closely approximate the ideal filter but are realizable. Filter Switched → Continuous → Specifications Time Filter Capacitor Filter Ideal Filter: Magnitude 1. ECE 6414 . Consequently.) Passband ripple = T(j0) . it is expedient to briefly review the subject of continuous time filters.) Stopband gain = T(jωSB)/T(j0) = T(jωSB) if T(j0) = 1. 2. 3.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.(a.) Normalized.E.71 SECTION 9.) (a. Therefore. ECE 6414 . For a normalized filter the basic properties are: 1.72 Characterization of Filters A low pass filter magnitude response.) Stopband frequency (called the transition frequency) = Ωn = ωSB/ωPB.) Stopband gain/attenuation = T(jωSB).0 0 Stopband Frequency Phase 0° 0 Slope = Time delay fcutoff = fPassband Frequency This specification cannot be achieve by realizable filters because: • An instantaneous transition from a gain of 1 to 0 is not possible.0 Passband 0. Allen .2002 Page 9.71 .) Low pass filter.2002 . 1.T(jωPB). 2. 3.7 – SWITCHED CAPACITOR FILTERS Continuous Time Filter Theory Today’s switched capacitor filters are based on continuous time filters.E. low pass filter.) Figure 9.Analog Integrated Systems Design © P. Allen . • A band of zero gain is not possible.) Passband ripple = T(jωPB)/T(j0) = T(jωPB) if T(j0) = 1. T(jω) T(j0) T(jωPB) T(jωSB) 0 0 ω Tn(jωn) 1 T(jωPB)/T(j0) T(jωSB)/T(j0) 0 0 ωn ωPB ωSB 1 ωSB/ωPB=Ωn (b.
E. (b. Allen . 9. (jω ) = n 1 2N 0.73 Filter Specifications in Terms of Bode Plots (dB) Tn(jωn) dB T(jωPB) T(jωSB) 0 1 An(jωn) dB Ωn log10(ωn) A(jωSB) A(jωPB) 0 0 log10(ωn) 1 Ωn (b. Allen .(a.2002 . Passband ripple = T(jωPB) dB Stopband gain = T(jωSB) dB or Stopband attenuation = A(jωPB) Transition frequency is still = Ωn = ωSB/ωPB ECE 6414 .72a shown in terms of attenuation (A(jω) = 1/T(jω)).8 0.5 1 1.71 as a Bode plot.5 3 20 log10(TSB) = TSB (dB) = 10 log10 1 + ε2 Ω n 2N ECE 6414 .5 2 where N is the order of the Normalized Frequency.2002 Page 9.) Figure 9.) Low pass filter of Fig.4 A 1 1+ε N=5 N=4 N=6 N=8 N=3 N=2 2 T N=10 1 + ε2 ω n 0 0 0. ωn approximation and ε is defined in the above plot. 9.Chapter 9 – Section 7 (2/25/03) Page 9.74 Butterworth Filter Approximation This approximation is maximally flat in the passband. The magnitude of the Butterworth filter approximation at ωSB is given as jω SB 1 T = T ( j Ω ) = T = LPn LPn n SB 2N ω PB 1 + ε2 Ω n This equation in terms of dB is useful for finding N given the filter specifications.72 .) Low pass filter of Fig.E. Therefore.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.6 T LPn (jω n) 0. Butterworth Magnitude Approximation: LPn 1 0.) (a.Analog Integrated Systems Design © P.2 2.
39018 1.97538 1.70711 a1 coefficient 1.98481 0.78202 0.45399 ± j0.34202 0.5.97493 0. Find the smallest integer value of N of the Butterworth filter approximation which will satisfy this specification. Thus.70711 ± j0.84776 0.00000 0.64279 0.38268 0.41421 © P. and Ωn = 1. ECE 6414 .30902 ± j0. TSB = 20 dB.55557 0.87938 0.83 dB for N = 2 10. low pass Butterworth functions for ε = 1.76604 ± j0.90097 ± j0.43388 0.31286 1.71 .15643 0.70711 0.2002 Page 9.96593 ± j0.70711 ± j0.80194 1.92388 ± j0.75 Example 9.E.98769 ± j0.96158 0.5 Substituting values of N into this equation gives.2002 ECE 6414 .53208 1.51764 1.68 dB for N = 5 21.19509 ± j0. Allen .58779 0.17365 ± j0.78183 0.86603 0.76536 1.70711 0.83147 ± j0.25 dB for N = 4 17.45399 0.Chapter 9 – Section 7 (2/25/03) Page 9.98079 ± j0.34730 1.Analog Integrated Systems Design .89101 0.00000 1.15643 ± j0.50000 ± j0.41421 1. lowpass filter is specified as TPB = 3dB. Solution TPB = 3dB corresponds to TPB = 0.92388 0.E.80902 ± j0.16 dB for N = 6.76 Poles and Quadratic Factors of Butterworth Functions Table 9.93969 ± j0.89101 ± j0.24698 0. Allen .41421 0.55557 ± j0. Thus.25882 ± j0.93186 1.90798 1.98079 0.25882 0.38268 ± j0. substituting ε = 1 and Ωn = 1.50000 ± j0. TSB = 7.61804 0.62349 ± j0.71 .Determining the Order of A Butterworth Filter Approximation Assume that a normalized.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.83147 0.10 log10 1 + 1.Pole locations and quadratic factors (sn2 + a1sn + 1) of normalized.707 which implies that ε = 1. N 2 3 4 5 6 7 8 9 10 Poles 0. Odd orders have a product (sn+1).86603 0. N must be 6 or greater to meet the filter specification.98769 0.19509 0.61804 1.93 dB for N = 3 14.5 into the equation at the bottom of the previous slide gives 2N TSB (dB) = .22252 ± j0.44505 1.95106 0.96593 0.70711 ± j0.66294 1.11114 1.
78 Chebyshev Filter Approximation The magnitude response of the Chebyshev filter approximation for ε = 0. lowpass. ωn > 1 n where N is the order of the filter approximation and ε is defined as 1 TLPn(ωPB) = TLPn(1) = TPB = 1+ε2 .77 Example 9. ωn ≤ 1 and LPn 1 0.5 2 Normalized Frequency.6180sn+1 Illustration of the individual magnitude contributions of each product of TLPn(sn).Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.5 1 1.and secondorder products are obtained from Table 9.5 A 1 1+ ε2 N=2 N=3 N=4 N=5 1 1.5 Magnitude TLPn(j ωn ) 1 T1(j ωn ) 0. Solution For N = 5.5 3 ECE 6414 .71 1 1 1 2 2 TLPn(sn) = T1(sn)T2(sn)T3(sn) = sn+1 sn+0.E. Allen . Chebyshev.5 T3 (jωn) 0 0 0.Finding the Butterworth Roots and Polynomial for a given N Find the roots for a Butterworth approximation with ε =1 for N = 5. ωn 2.5 3 1 ( jω n ) = 1 + ε2 cosh2[Ncosh1(ω )] . N is determined from 20 log10(TSB) = TSB (dB) = 10log10{1 + ε2cosh2[Ncosh1(Ωn)]} T ECE 6414 . 2 T 2 (jωn) 1. The magnitude of the normalized.2 0 0 0.6180sn+1sn+1.2002 .72 .6 TLPn(jωn ) 0. Allen . ωn 2.5 2 Normalized Frequency.Analog Integrated Systems Design © P. the following first.Chapter 9 – Section 7 (2/25/03) Page 9.5088. filter approximation can be expressed as TLPn(jωn) = 1 1 + ε2 cos2[Ncos1(ωn)] .8 0.2002 Page 9.E.4 0.
44294 0.40733 0.14 dB.99073 0.E.79 Example 9. For N = 2.27907 0.10251 0. 9.46413 0.23206 ± j0.17892 0.5088 (1dB).11.99341 0.72.09142 0.12807 ± j0. Now we substitute ε = 1 into 20 log10(TSB) = TSB (dB) = 10log10{1 + ε2cosh2[Ncosh1(Ωn)]} and find the value of N which satisfies TSB = . ECE 6414 .E.2002 Page 9. 9.49417 0. Allen .20dB.Determining the Order of A Chebyshev Filter Approximation Repeat Ex.37014 © P.24709 ± j0.61192 0.23045 a1 1.72 .707.23421 ± j0.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.09773 0.43 dB.98650 0.73 . ε = 1 which means the ripple width is 3 dB or TPB = 0.13954 ± j0. Thus N = 4 must be used although N = 3 almost satisfies the specifications.710 Poles and Quadratic Factors of Chebyshev Functions Table 9. low pass Chebyshev functions for ε = 0.46841 0.16988 ± j0.54887 ± j0.Analog Integrated Systems Design .55772 0.49417 0. Allen .27940 0. Solution In Ex.99528 0. → TSB = 27.22 dB.33687 ± j0.25615 0.99420 0.18507 ± j0.67374 0.Pole locations and quadratic factors (a0 + a1sn + sn2) of normalized.26618 0.98831 0.08946 ± j0.99011 0.79816 0.12471 0.99268 0. For N =3.28949 0.71 for the Chebyshev filter approximation.72723 0.98338 0. For N = 4.04571 ± j0.Chapter 9 – Section 7 (2/25/03) Page 9.42930 0.20541 a0 1.06218 ± j0.89513 0.33976 0.65346 0. → TSB = 19.12436 0. N 2 3 4 5 Normalized Pole Locations 0.2002 6 7 ECE 6414 . → TSB = .96600 0. This result compares with N = 6 for the Butterworth approximation.
© P.2895 TLPn(sn) = T1(sn)T2(sn)T3(sn) = sn+0.2002 Page 9. 1 2 W.I.2 An excellent collection of filter approximations and data is found in A. IEEE.9883sn+0. 487490. the smallest transition region of all filters.9883 0. NY. New York.Maximally flat magnitude and linear phase1 Elliptic Filters . Thomson. Inc. vol.711 Example 9.4293 0.1789sn+0.E. 1958..Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.E. Cauer. Synthesis of Linear Communication Networks. Allen . pp.” Proc.Analog Integrated Systems Design . “Delay Networks Having Maximally Flat Frequency Characteristics. 1949. New York. Allen .2002 W.712 Other Approximations Thomson Filters .2895 2 2 sn+0. 1967. McGrawHill Book Co.. part 3.Ripple both in the passband and stopband. Solution For N = 5. 96. Nov. we get the following quadratic factors which give the transfer function as 0.4293 . John Wiley & Sons. ECE 6414 .Finding the Chebyshev Roots for a given N Find the roots for the Chebyshev approximation with ε =1 for N = 5.Chapter 9 – Section 7 (2/25/03) Page 9.4684sn+0. ECE 6414 .74 . Zverev. Handbook of Filter Synthesis.E.
Laker and W. low pass. 4. ECE 6414 .4. Allen . Design of Analog Integrated Circuits and Systems. Sansen. and Ωn (or APB.E. 3. and Ωn) determine the required order of the filter approximation. Introduction to the Theory and Design of Active Filters. ECE 6414 . Switched Capacitor Circuits. 1980.) Ladder approach .E. Allen. New York. SanchezSinencio.Analog Integrated Systems Design © P.P.) From TPB.) Realize each of the terms using the first.Chapter 9 – Section 7 (2/25/03) Page 9. 1 2 3 4 K.E. L. ASB. For oddorder realizations there will be one firstorder term.C. McGraw Hill. Allen and E. 1984.C.714 A Design Procedure for the Low Pass.E.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P. Huelsman and P.) Group the complexconjugate poles into secondorder realizations. TSB.M. N.2002 Page 9. 2. or BS Frequency Transform the L's and C's to HP.) From tables similar to Table 9.3. John Wiley & Sons. 2. Temes. New York. or BS Cascade of First. Normalized LP Filter Root Locations Normalized LowPass RLC Ladder Realization Frequency Transform the Roots to HP. McGraw Hill Book Company. 1.2.71 and 9. P.starts with the normalized. SC Filters Using the Cascade Approach 1. Normalized Filter with a passband of 1 rps and an impedance of 1 ohm. BP.2002 .713 GENERAL APPROACH FOR CONTINUOUS AND SC FILTER DESIGN Approach LowPass.R. low pass filter with a passband of 1 radian/second and an impedance of 1Ω that will satisfy the filter specification.starts with the normalized. Gregorian and G. 5. 1987. Van Nostrand Reinhold.and/or SecondOrder Stages FirstOrder Replacement of Ladder Components Denormalize the Filter Realization All designs start with a normalized. More information can be found elsewhere1. 1994. RLC ladder realizations.) Cascade approach . New York. R.72 find the normalized poles of the approximation. BP. low pass filter root locations. New York.) Cascade the realizations in the order from input to output of the lowestQ stage first (firstorder stages generally should be first). Analog MOS Integrated Circuits for Signal Processing. Allen .and secondorder blocks of the previous lectures.
Eq. (2) can be written as α11/α21 α11/Tn (4) T1(sn) ≈ 1 + sn(Tn/α21) = sn + α21/Tn where α11 = C11/C and α21 = C21/C.4293 Next. TSB = 25dB. sT = (3) PB n n ω PB Therefore. Solution First we see that Ωn = 1. Use a clock frequency of 20kHz. Next. we design each of the three stages φ1 individually.715 Example 9.9dB).000 The sum of capacitances for the first stage is 1 Firststage capacitance = 2 + 0.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.716 Example 9.e.2895·2000π α21 = α11 = 0.2002 .Analog Integrated Systems Design © P. Also simulate the realization and compare to an ideal realization.4293 2 TLPn(sn) = (1) 2 sn+0.E.5088.Firstorder Stage φ1 φ2 .Continued Note that we have used the second subscript 1 to denote the first stage.4684sn+0. This normalization is accomplished by s · (ω T) = s T .0909 = 13 units of capacitance ECE 6414 . recall that when TPB = 1dB that this corresponds to ε = 0.Chapter 9 – Section 7 (2/25/03) Page 9.5kHz.5.75 .E. α21C11 α C φ 11 11 2 Vin(ejω) V2(ejω) Stage 1 .2895·ωPB 0. Stage 1 α11/α21 (2) T1(s) ≈ 1 + s(T/α21) ECE 6414 .0909 fc 20. Allen . fPB = 1kHz and fSB = 1.9883 0. SC Filter using the Cascade Approach Design a cascade.Fifthorder. switched capacitor realization for a Chebyshev filter approximation to the filter specifications of TPB = 1dB.2002 Page 9. Low Pass. We will + assume that fc is much greater than fBP (i.1789sn+0. Allen .2895Tn = = = 0.2895 sn+0. Using the results of previous lecture. Equating Eq. We find that N = 5 satisfies the specifications (TSB = 29. (4) to the first term in TLPn(sn) gives the design of firstorder stage as 0. Give a schematic and component value for the realization. Before we can use this equation we must normalize the sT factor. we may write TLPn(sn) as 0.2895 0.75 . 100) and use transfer function shown below to accomplish the design.9883sn+0.C11 φ2 φ1 Let us select the firstorder stage shown.
C23 2 φ1 φ1 φ2 φ1 T(0)ω n + + = 2 (8) 2 s n + (ωn/Q)sn + ω n Stage 3 where we see that T(0) = 1. Thus we get.9883 α12C12 α52C22 V3(ejω) V2(ejω) 2 φ2 φ1 φ2 φ2 s n + 0. α12 = α22 = α52 = 0. ωn = 0. select the low pass version of the lowQ biquad.4684) = 1. (3) to get ECE 6414 .1789) = 5. Therefore. (6) T2(sn) ≈ snα42α52 α22α52 2 s n + Tn + 2 Tn To get a low pass realization.C22 φ φ φ φ 2 1 1 2 1 + + T(0)ω n (5) = 2 ωn Stage 2 2 sn + Q sn + ω n where T(0) = 1. apply the normalization of Eq.E. LowQ Stage The last product of TLPn(sn) is φ1 0.717 Example 9. The secondstage capacitance is 3(0.1789·2π α42α52 = 0. select α32 = α62 = 0 to get 2 (α12α52/T n ) (7) T2(sn) ≈ snα42α52 α22α52 .05620 fc 20 Choose a12 = a22 = α52 to get optimum voltage scaling.3123 = 0.9941 and Q = (0.1789·ωPB 0.56.75 . (3) to get snα32α52 α12α52 2 α62s n + Tn + 2 Tn .C12 .Secondorder.Chapter 9 – Section 7 (2/25/03) Page 9.316 units of capacitance Stage 3 .4293 φ2 φ1 φ2 φ2 .C13 .4293 α21C13 α C α C α C 63 23 φ j ω 13 13 53 23 2 V3(e ) 2 Vout(ejω) sn + 0.1789Tn = = = 0. Allen .05620/0. Allen .1800 + 0.718 Example 9.2002 Page 9.9883·4π2 2 α12α52 = α22α52 = 0.6552/0. select the lowpass version of the highQ biquad.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P. (7) to the middle term of TLPn(sn) gives 0. highQ Stage α22C12 α42C12 φ2 The next product of TLPn(sn) is 0.1800. Therefore.6552 and Q = (0. First.Continued φ1 Stage 2 – 2ndorder.3123 and α42 = 0.2002 .Analog Integrated Systems Design © P.9941/0. Apply the normalization of Eq.3123) 2 Secondstage capacitance = 1 + 0.09754 fc2 400 and 0.1800 = 17.9883Tn = = = 0.1789sn + 0.75 .9883·ωPB2 0.4684sn + 0.Continued Equating Eq.3988.E. 2 + s n + Tn 2 Tn ECE 6414 .9883 . ωn = 0.
(9) snα63 α23α53 2 s n + Tn + 2 Tn To get a low pass realization.10 units of capacitance.4684·ωPB/fc) = (0.78 = 49.720 Example 9.75 .E.Continued α α sα 2 + n 43 + 13 53 α33s n 2 Tn Tn T3(sn) ≈ .2002 .4293T n = = = 0.1472) =18.E.4684·2π/20) = 0.75 . low pass. α13 = α23 = α53 = 0.2058)/0.78 units of capacitance The total capacitance of this design is 13 + 17.32 + 18.4293·4π2 2 α13α53 = α23α53 = 0. ECE 6414 .Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P. The thirdstage capacitance is 3rdstage capacitance = 1+(3(0.(α13α53/T n (10) T3(sn) ≈ snα63 α23α53 .719 Example 9. Chebyshev.4293·ωPB2 0.1472 Choose a13 = a23 = α53 to get optimum voltage scaling. 2 s n + Tn + 2 Tn Equating Eq. Stage 1 α11C11 Vin(ejω) φ1 φ2 φ1 φ2 α21C11 + φ1 φ2 C11 Stage 3 α13C13 φ2 φ1 φ1 φ2 + α23C13 C13 φ1 φ1 α53C23 φ2 α63C23 φ2 φ1 + φ2 C23 Stage 2 α22C12 α12C12 φ2 φ1 φ1 φ2 + φ1 α42C12 φ2 Vout(ejω) φ2 + α52C22 C12 φ1 φ2 φ1 C22 Figure 9.77 .1472)+(2/0. switched capacitor filter of Example 9.Continued Final design with stage 3 second to maximize the dynamic range. Thus .2002 Page 9.75. ECE 6414 .04184 fc2 400 and α63 = 0. select α33 = α43 = 0 to get 2 ) .4684Tn = (0. Allen .1472.Chapter 9 – Section 7 (2/25/03) Page 9. (10) to the last term of TLPn(sn) gives 0. Allen .Analog Integrated Systems Design © P.Fifthorder.2058 and α63 = 0.
• Stopband specifications met • None of the outputs of the biquads exceeds 0 dB (Need to check internal biquad nodes) ECE 6414 .78a .Simulated phase response of Ex.PARAM CNC=1 CNC_1=1 CPC_1=1 XNC1 1 2 3 4 NC1 XUSCP1 3 4 5 6 USCP XPC1 5 6 3 4 PC1 XAMP1 3 4 5 6 AMP XPC2 5 6 7 8 PC2 XUSCP2 7 8 9 10 USCP XAMP2 7 8 9 10 AMP XNC3 9 10 11 12 NC3 XAMP3 11 12 13 14 AMP XUSCP3 11 12 13 14 USCP XPC4 13 14 11 12 PC4 XPC5 13 14 7 8 PC2 XPC6 13 14 15 16 PC6 XAMP4 15 16 17 18 AMP XUSCP4 15 16 17 18 USCP ECE 6414 .721 Example 9. This can be avoided by prewarping the specifications before designing the filter.722 Example 9.8581 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0. Allen .SUBCKT NC1 1 2 3 4 RNC1 1 0 11.78b . and node 21 is the *final output of the *filter. 9.0909 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.E.ENDS NC1 .0909 RNC2 4 0 11.75 – Continued SPICE Input File: ******** 08/29/97 13:17:44 ********* *******PSpice 5.0011 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.E.2 (Jul 1992) ******** *SPICE FILE FOR EXAMPLE 9.SUBCKT NC3 1 2 3 4 RNC1 1 0 4.75 0 500 1000 Stage 2 Output (Filter Output) Stage 3 Output Stage 1 Output 200 150 Phase (Degrees) 100 50 0 50 100 150 200 0 500 Stage 1 Phase Shift 1500 2000 2500 3000 3500 Frequency (Hz) Figure 9.2002 *.75 1000 Stage 2 Phase Shift (Filter Output) Stage 3 Phase Shift Comments: • There appears to be a sinx/x effect on the magnitude which causes the passband specification to not be satisfied. Allen . low Q stage).8581 Ends NC3 © P. **** CIRCUIT DESCRIPTION **** VIN 1 0 DC 0 AC 1 XNC7 17 18 19 20 NC7 XAMP5 19 20 21 22 AMP XUSCP5 19 20 21 22 USCP XUSCP6 21 22 15 16 USCP1 XPC8 21 22 15 16 PC6 SUBCKT DELAY 1 2 3 ED 4 0 1 2 1 TD 4 0 3 0 ZO=1K TD=25US RDO 3 0 1K .Chapter 9 – Section 7 (2/25/03) Page 9.0011 .Analog Integrated Systems Design .Simulated magnitude response of Ex.2002 Page 9.Continued Simulated Frequency Response: 0 10 Magnitude (dB) 20 30 40 50 60 70 1500 2000 2500 3000 3500 Frequency (Hz) Figure 9.2058 RNC2 4 0 4.ENDS DELAY .2058 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.0909 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.75 *EXAMPLE 975: nodes 5 is the output *of 1st stage.2058 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0. 9. node 13 : second stage (in *the figure it is second while in design it *is third.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.75 .
Analog Integrated Systems Design .ENDS PC1 .ENDS NC .SUBCKT NC7 1 2 3 4 RNC1 1 0 3.SUBCKT USCP 1 2 3 4 R1 1 3 1 R2 2 4 1 XUSC1 1 2 12 DELAY GUSC1 1 2 12 0 1 XUSC2 1 4 14 DELAY GUSC2 4 1 14 0 1 XUSC3 3 2 32 DELAY GUSC3 2 3 32 0 1 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 1 .SUBCKT PC2 1 2 3 4 RPC1 2 4 4.END © P.3123 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.ENDS PC2 .0011 .3123 RNC2 4 0 3.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.E.AC LIN 100 10 3K .PRINT AC V(5) VP(5) V(13) VP(13) V(21) VP(21) .PROBE .Continued Spice Input FileContinued .1799 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 . Allen .1799 .1799 XUSC2 1 4 14 DELAY GUSC2 4 1 14 0 .ENDS AMP .SUBCKT PC6 1 2 3 4 RPC1 2 4 3.5586 R2 2 4 5.2018 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.ENDS USCP .SUBCKT PC4 1 2 3 4 RPC1 2 4 6.8581 .2002 Page 9.PRINT AC V(5) VP(5) V(13) VP(13) V(21) VP(21) . Allen .2018 .3123 RNC2 4 0 3.SUBCKT USCP1 1 2 3 4 R1 1 3 5.SUBCKT PC1 1 2 3 4 RPC1 2 4 11.3123 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.ENDS PC2 .Continued Spice Input FileContinued .ENDS PC1 .E.END ECE 6414 .SUBCKT NC7 1 2 3 4 RNC1 1 0 3.724 Example 9.ENDS USCP1 .SUBCKT USCP1 1 2 3 4 R1 1 3 5.3123 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.7980 .75 .1799 XUSC3 3 2 32 DELAY GUSC3 2 3 32 0 .2018 .AC LIN 100 10 3K .1799 XUSC3 3 2 32 DELAY GUSC3 2 3 32 0 .ENDS USCP1 .SUBCKT PC2 1 2 3 4 RPC1 2 4 4.1799 XUSC2 1 4 14 DELAY GUSC2 4 1 14 0 .5586 XUSC1 1 2 12 DELAY GUSC1 1 2 12 0 0.723 Example 9.2018 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0.3123 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.8581 .ENDS PC6 .PROBE .2002 ECE 6414 .SUBCKT PC6 1 2 3 4 RPC1 2 4 3.2018 .SUBCKT USCP 1 2 3 4 R1 1 3 1 R2 2 4 1 XUSC1 1 2 12 DELAY GUSC1 1 2 12 0 1 XUSC2 1 4 14 DELAY GUSC2 4 1 14 0 1 XUSC3 3 2 32 DELAY GUSC3 2 3 32 0 1 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 1 .75 .SUBCKT AMP 1 2 3 4 EODD 3 0 1 0 1E6 EVEN 4 0 2 0 1E6 .2018 .5586 R2 2 4 5.ENDS AMP .0011 .1799 XUSC4 3 4 34 DELAY GUSC4 3 4 34 0 .SUBCKT AMP 1 2 3 4 EODD 3 0 1 0 1E6 EVEN 4 0 2 0 1E6 .7980 .SUBCKT PC4 1 2 3 4 RPC1 2 4 6.ENDS USCP .Chapter 9 – Section 7 (2/25/03) Page 9.ENDS NC7 .ENDS PC4 .5586 XUSC1 1 2 12 DELAY GUSC1 1 2 12 0 0.SUBCKT PC1 1 2 3 4 RPC1 2 4 11.ENDS PC6 .1799 .ENDS PC4 .
TLP(jω) 1 TPB TSB 0 0 TBP(j ω) 1 TPB Transition Region One possible filter realization B THP(j ω) 1 TPB A One possible filter realization A B ωPB ωSB (a.0909.Continued Switcap2 Input File (The exact same results were obtained as for SPICE) TITLE: EXAMPLE 975 OPTIONS. S3 (3 0) CLK. bandpass or bandstop to achieve other types of filters. TIMING. S2 (2 0) CLK. SUBCKT (100 200) STG3. END. CL63 (9 7) 0. END. CL11 (2 3) 0. CLOCK CLK 1 (0 25/50).E. X2 (100 200) STG3.) Practical magnitude responses of (a. We will use transformations from the normalized.Chapter 9 – Section 7 (2/25/03) Page 9. ECE 6414 . S7 (7 0) CLK. PERIOD 50E6. (8 200) 1. S9 (200 9) #CLK. (6 7) 0. low pass filter to the normalized high pass. S3 (3 0) CLK.725 Example 9.2058. END. ANALYZE SSS.) low pass.1471. S5 (5 100) #CLK. GRID.1799. S2 (2 0) #CLK. PRINT vdb(100) vp(100). (200 0 0 8)1E6 CIRCUIT. PLOT vdb(300). CL13 (2 3) 0. S4 (3 0) CLK.) bandstop filter. NOLIST.E.3123. ECE 6414 .0. (c. Allen . INFREQ 1 3000 LIN 150. C13 (4 5) 1. PRINT vdb(200) vp(200).2058.) bandpass. S5 (6 5) CLK. S6 (5 0) CLK. and (d. S5 (6 5) CLK. S1 (100 2) #CLK. (300 0 0 8)1E6 CL53 C23 E1 E2 END. X1 (1 100) STG1.0909. S2 (2 0) CLK.0 0.3123.3123. (4 5) 1. (7 8) #CLK. © P. V1 (2 0). (6 0) #CLK. E1 (100 0 0 4)1E6.2002 Page 9. X3 (200 300) STG2. S6 (6 0) #CLK.) One possible filter realization TSB ω (rps) 0 0 Transition Region ωSB ωPB TBS(jω) (b. (6 7) 0. S4 (3 4) #CLK. SUBCKT (200 300) STG2.) Upper TransiTSB B D tion Region 0 ω (rps) 0 ωPB1 ωSB1 ωSB2 ωPB2 (d.Analog Integrated Systems Design © P.2058. (4 300) 0. (3 9) 0. END. (5 0 0 4) 1E6. S4 (3 4) #CLK. PRINT vdb(300) vp(300).726 Using the Cascade Approach for Other Types of Filters Other types of filters are developed based on the low pass approach. END. SET V1 AC 1. CL21 (3 5) 0. S1 (1 2) CLK. S1 (200 2) #CLK. (2 3) 0. CL23 (3 9) 0. (b. Allen .Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) S6 S7 S8 S9 S10 CL12 CL22 CL42 C12 CL52 C22 E1 E2 END. END.75 . S8 (7 8) #CLK. (8 300) 1. (300 9) #CLK. S10 (9 0) #CLK. (7 0) CLK. (5 0 0 4) 1E6.) high pass.2002 . SUBCKT (1 100) STG1. (9 0) #CLK. S3 (3 4) #CLK.) ω (rps) Lower Transition Region B C Upper Transition Region 1 TPB ω (rps) One possible Lower filter realization Transition A Region C TSB A D 0 0 ωSB1 ωPB1 ωPB2 ωSB2 (c.
12 dB which is the lowest.728 N N Example 9. p5ln = 0. p5hn = 0.7071 and p3ln.9659 ± j 0.9659 + We note the inversion of the Butterworth poles simply changes the sign of the imaginary part of the pole. lowpass to highpass transformation toTLPn(sln) gives p1lnp2lnp3ln···pNln shn THPn(shn) = 1 1 1 1 = 1 1 1 1 + p + p + p ··· + p s + s + s + ··· s + 1lnshn 2lnshn 3ln shn Nln shn hn p1ln hn p2ln hn p3ln hn pNln shn = shn+p1hnshn+p2hnshn+p3hn···shn+pNhn where pkhn is the kth normalized highpass pole.76 . A general form of the normalized.7071 + and . lowpass transfer function is p1lnp2lnp3ln···pNln TLPn(sln) = (sln+p1ln)(sln+p2ln)(sln+p3ln)···(sln+pNln) where pkln is the kth normalized. Next. lowpass poles are found from Table 9. Therefore. Also.9659 p1hn.j 0.9659 p2ln.Analog Integrated Systems Design © P. find that N = 6 will give TSB = 36.2588 + . Solution From the specification. Use high pass switched capacitor circuits to achieve the implementation. integer value of N which meets the specifications.2002 Page 9. p6ln = 0.E. HighPass Filter Design a highpass filter having a 3dB ripple bandwidth above 1 kHz and a gain of less than 35 dB below 500 Hz using the Butterworth approximation. Allen .7071 p2hn. ωPB 1 Ωn is defined for the high pass normalized filter as: Ωn = Ωhn = ωSB ECE 6414 . we know that TPB = 3 dB and TSB = 35 dB.7071 ± j 0.2588 ± j 0. p6hn = 0. ε = 1 because TPB = 3 dB. p4ln = 0.5).Design of a Butterworth. Ωn = 2 (Ωhn = 0.2002 . highpass frequency variable.71 as p1ln.j 0. SC Filters Using the Cascade Approach Normalized. Allen . ECE 6414 . the normalized. lowpass pole. p3hn.j 0.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P. Use a clock frequency of 100kHz.2588 . highpass poles which are . Applying the normalized.2588 Inverting the normalized. lowpass poles gives the normalized. low pass to normalized high pass transformation: 1 sln = shn where shn is the normalized.E.Chapter 9 – Section 7 (2/25/03) Page 9.727 High Pass. p4hn = 0.
9318 = 0.1214 Realization → Lowest Q stages are first in the cascade realization.932.76 .06283. and α6 = (ωonTn/Q) .707. Allen . ωonTn K0=K1=0 and K2=1. α31 = 1. α33 = 1. This result gives the following normalized. α4 = K1Tn. Stage 1 α21=α51=(ωPB/fc)=(2π·103/105)=0. Σ capacitances = 104. since there are no firstorder products. The lowQ biquad design equations are: α1 = (K0Tn/ωon) .76 . α3 = K2 and α6 = Q .E.5176.03252 ECE 6414 .5176 = 1.06283. and ωPB 0.932) = 0.Continued The next step is to group the poles in secondorder products. We see that the Q’s of each stage are Q1 = 1/0.E. α2 = α5 = ωonTn.730 φ1 Stage 1 φ1 α61C21 φ1 φ2 φ1 φ2 α51C21 α21C11 φ2 φ1 α31C21 φ2 C21 + ECE 6414 . and α61 = (ωPB/Qfc) = (0. and ωPB 0.06283 α63 = Qfc = 0. For the high pass. and Q3 = 1/1.414 = 0. α32 = 1.06283/1. we will choose the lowQ biquad to implement the realization of this example.62 units of capacitance Stage 3 α63C23 φ1 e α33C23 Vin(z) φ1 φ2 C23 φ2 φ1 φ2 α53C23 α23C13 φ2 φ1 φ1 φ2 C13 + V3(z) e + Stage 2 φ2 e V2(z) φ1 α52C22 φ1 α62C22 φ1 φ2 φ1 C12 φ2 α21C12 C22 φ2 α32C22 φ1 φ2 e C11 + Vout(z) © P.Analog Integrated Systems Design + φ2  +  Example 9.4141shn+1shn+1.Chapter 9 – Section 7 (2/25/03) Page 9. Allen .729 Example 9.08884 Stage 3 ωPB 2π·103 α23 = α53 = fc = 105 = 0.2002 .9318shn+1 Now we are in a position to do the stagebystage design.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P. α3 = K2.707 = 0. Therefore. = 2 2 2 shn+0. so that α1=α4=0 and α2=α5 = ωonTn.06283.Continued Stage 2 ωPB 2π·103 α22 = α52 = fc = 105 = 0.06283 α62 = Qfc = 0. THPn(shn) = T1(shn)T2(shn)T3(shn) 2 2 2 shn shn shn = (shn+p1hn)(shn+p6hn)(shn+p2hn)(shn+p5hn)(shn+p3hn)(shn+p4hn) 2 2 2 shn shn shn .5176 = 0. highpass transfer function.2002 Page 9. Q2 = 1/1.5176shn+1shn+1.
(a.Illustration of the development of a bandpass filter from a lowpass filter. (c.) for bandpass transformation. to get 1 ωr sb 1 ωr sb = sbn + + where s = sln = bn ωr .710 .2002 .sln sln/2 . by the geometric center frequency.2002 Page 9.E. 2. (d.) Multiply by BW/ωr and define yet a further normalization as BW ' = B W sln = Ωbsln = Ωb sl = sbn + 1 where Ω = sln b ω ω ωr .) Normalization of (a.) Ideal normalized. (b.) Denormalized bandpass filter.) Solve for sbn in terms of sln 2 ' 2 ' sbn + 1 = 0 → sbn = ' sbn .Chapter 9 – Section 7 (2/25/03) Page 9. 6. sb 4. sln/2 ± ECE 6414 .731 Bandpass.) Geometrically centered bandpass filters have the following relationship: ωr = ωPB1ωPB2 = ωSB2ωSB1 3.) Ωb 1 TPBn (jωb ) 1 BW BW ωr 0 0 (d.) Define a normalized lowpass to unnormalized bandpass transformation as 2 2 ω2 1 1 r sb + ω r sln = B W = BW sb + sb .Analog Integrated Systems Design © P.732 Illustration of the Above Approach TLPn(jωln ) 1 Bandpass Normalization Ωb s ln = BW s ln → s 'ln ωr 1 (a. sbn r PB ' from the following quadratic equation. sb. ωSB2 (ωSB1) is the larger (smaller) stopband frequency.) A normalized lowpass to normalized bandpass transformation is achieved by dividing the bandpass variable. Allen .) Define the passband and stopband as and SW = ωSB2 .) 1 ω 'ln (rps) Normalized 2 s 'ln lowpass to s 'ln ± 1 normalized 2 2 bandpass ↓ transformation s bn TBPn(jωbn ) Bandpass Denormalization sb ← Ωb s bn = BW sbn ωr ωb (rps) 1 Ωb 1 0 0 (c.E.) Application of lowpass to bandpass transformation.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P. (sb/ωr) B W sbn B W ωr 5.ωPB1 where ωPB2 (ωPB1) is the larger (smaller) passband of the bandpass filter.) ωr ωln (rps) ω PB TLPn(jω 'ln ) 1 0 1 0 0 Ωb 0 Ω b (b.ωSB1 BW = ωPB2 . lowpass filter. SC Filters Using the Cascade Approach 1. ωr.) ωr ω bn (rps) Figure 9. Allen .1 . ECE 6414 .
Illustration of how the normalized. and σ2bn+ω2 kbn ωkon = and Qk = 2σbn .E.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.) The ratio of the stop bandwidth to the pass bandwidth is defined as S W ωSB2 . 2 σkbn +ω2 kbn ECE 6414 . Allen . p ‘ . 3.2002 .734 Bandpass Design Procedure for the Cascade Approach .ωPB1.) The normalized bandpass poles can be found from the normalized.ωSB1 Ωn = B W = ωPB2 . Figure 9.Analog Integrated Systems Design © P. lowpass poles. Kk is a gain constant. kln ‘ 4. and Ωn.Chapter 9 – Section 7 (2/25/03) Page 9. complex conjugate poles are transformed into two normalized. For each pole of the lowpass filter. 2.) Realize each secondorder product with a bandpass switched capacitor biquad and cascade in the order of increasing Q. Allen .Continued 5. pkln using ‘ p ‘ jωbn pkln kln2 ' p jωln jbn pkbn = 2 ± 2 1 .) From TPB. lowpass.733 Bandpass Design Procedure for the Cascade Approach 1. two poles result for the bandpass filter. find the order N or the filter. complex conjugate poles.2002 Page 9. TSB.) Find the normalized. bandpass. p'jln σ'ln p'kln * = p'jln Lowpass Poles ω ω Normalized by PB r BW p* jbn p* kbn Normalized Bandpass Poles pkbn σbn ECE 6414 .) Group the poles and zeros into secondorder products having the following form Kk sbn Kk sbn Tk(sbn) = (s + p )(s + p* ) = (sbn+σkbn+jωkbn)(sbn+σkbnjωkbn) bn kbn bn jbn ωkon sbn T ( ω ) k kon Kk sbn Qk = = s2 2 2 ωkon bn+(2σkbn)sbn+(σbn+ωkbn) s s2 + ω2 bn + kon Qk bn where j and k corresponds to the jth and kth lowpass poles which are a complex conjugate pair.711 . low pass poles.E. 6.
(a.9159. and the normalized bandpass poles.5000 σln p2ln 1 p'2ln p'3ln p3ln j1 3 zeros at ±j∞ σbn σ'ln 1 p 2bn p3ln j0. Allen . the bandpass normalized.1000 + j0. pkln.5000 ± j0.0543 + j1.0457 .8660 and p2ln = 1.Continued The normalized lowpass pole locations. integer value of N which meets the specifications. geometrically centered at 1 kHz. 0. p6bn = 0.E. pkln bandpass poles have very high poleQs if BW < ωr. we find that N = 3 will give TSB = 41.1000 ± j 0.0000 .) Bandpass normalized lowpass poles. lowpass pole ' . Therefore. pkbn are shown below.1000 ± j 0. Note that the locations.0457 + j0. p3ln = 0.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.) Normalized bandpass poles.543 . For p3ln’= 0. Also. Ωn = 1000/200 = 5.9159.94 dB which is the lowest. Next.2002 .8660 j1 p6bn p4bn j1 (a.j0.Design of a Cascade Bandpass Switched Capacitor Filter Design a bandpass.78.2000 .1732 → p1bn. → p5bn. ECE 6414 . lowpass poles from Table 9. Normalizing these poles by the bandpass normalization of Ωb = 200/1000 = 0.1732 → p3bn.) Normalized lowpass poles.Chapter 9 – Section 7 (2/25/03) Page 9.) Pole locations for Ex.8660 jω'ln p1ln p'1ln j1 p1bn jωbn p5bn p3bn j1 p2ln 1 0. p3ln’= 0. we know that TPB = 3 dB and TSB = 40 dB.77 .E.71 as p1ln.0891. Use a clock frequency of 100kHz.1 which results in 6 poles given as.2002 Page 9. Allen . (c. p4bn = 0. ε = 1 because TPB = 3 dB.) (c. jωln p1ln j1 j0.2 gives p1ln’.2000 ECE 6414 .j 1. The gain at 1 kHz is to be unity.j0. (b. Each one of the pkln’will contribute a secondorder term. we evaluate the normalized.77 .Analog Integrated Systems Design © P. For p2ln’= 0.) (b. Butterworth filter having a 3dB ripple bandwidth of 200 Hz geometrically centered at 1 kHz and a stopband of 1 kHz with an attenuation of 40 dB or greater.1732 and p2ln’= 0. 0.735 Example 9. For p1ln’= 0.736 Example 9.9950. p2bn = 0.1000 . The normalized bandpass ' 2 ' poles are found by using sbn = sln/2 ± sln/2 .0891. 9. Solution From the specifications.
9170 2 2 sbn+10. and α42 =0.9170 s 10.0891) 1.77 .9159 and K3sbn K3sbn T3(sbn) = (s+p5bn)(s+p6bn) = (sbn+0.00002 s2 + bn 5.E.2002 .0904 s 10.0000 s 5.06283. α21=α51= fc = =0.0333sbn+0. and α6 = 0 Stage 1 ωo1 1. α32=0.77 . For the bandpass realization K0 = K2 = 0 and K1 = ωon/Q. and Q3 = 5.0000 s +1. α2 = α5 = ωon.0000.05755. α3 = ωon = ωon = Q . α3 = ωon.E. α4 =Q.09042 s2 bn+ 10.09967.Chapter 9 – Section 7 (2/25/03) Page 9.738 Example 9.0904 s +1. α31 = 0.1000j0. so that the design equations simplify to K1 ωon/Q 1 ωon·ωr 1 α1 = 0.0410.2000. K1sbn K1sbn T1(sbn) = (s+p1bn)(s+p4bn) = (sbn+0. = 0.737 Example 9.0457+j0.0000·2πx103 α13=α63=0. α31=0.9950)(sbn+0. use the highQ biquad whose design equations are: K0Tn K1 1 α1 = ωon . α4 =Q.9159·2πx103 α12=α62=0.0410 bn = 1.0333 bn . α22=α52= fc = =0.0410 bn K2sbn K2sbn T2(sbn) = (s+p2bn)(s+p3bn) = (sbn+0. Allen . α2 = α5 = ωonTn . Note that the Q’s of the stages are Q1 = 10.09967 105 Stage 3 ωo3 1.06815.Analog Integrated Systems Design © P.0543+j1. Q2 = 10.0000 bn .9159)(sbn+0.0904·2πx103 α11=α61=0. and α41 =0.Tn = fc .Continued Grouping the complex conjugate bandpass poles gives the following secondorder transfer functions.Continued Now we can begin the stagebystage design. = 1.2002 Page 9. Therefore. α23=α53= fc = = 0.0333. Allen . and α41 = 0. and α6 = K2 .09959.0891)(sbn+0.1000+j0.9950) 1.2000 105 ECE 6414 .0457j0.0543j1.9159) 0.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.0000 bn ECE 6414 .09959 105 Stage 2 ωo2 0.
Ladder Approach The ladder approach to filter design starts from RLC realizations of the desired filter specification.) N even.Continued Realization: e φ1 φ2 α23C13 α43C13 C13 + φ1 φ2 φ2 φ1 Vin(z) α33C13 α53C23 φ1 φ2 C23 + V3(z) e Stage 3 φ1 φ2 α22C12 α42C12 C22 φ2 φ1 φ2 φ1 φ2 e V2(z) α52C22 φ1 C12 φ2 α32C12 Stage 2 α21C11 α41C11 C11 α51C21 φ1 φ2 φ1 φ1 φ2 α31C11  + Stage 1 ECE 6414 .Singlyterminated.n C3n L2n C1n 1 + Vout (sn )  Figure 9. Allen .2002 Page 9. Disadvantage: • Design approach more complex • Requires a prototype realization Singlyterminated RLC prototype filters: + Vin (sn ) (a.Chapter 9 – Section 7 (2/25/03) Page 9. (b. Allen . RLC prototype filters.739 Example 9.n L3n C2n L1n 1 + Vout (sn ) LN.) + Vin (sn ) (b.E.712 . ECE 6414 . (a.740 Higher Order Switched Capacitor Filters .Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.) LN.n CN1.77 . Advantage: • Less sensitive to capacitor ratios.2002 + φ2 φ1 +  C21 + Vout(z) e . These RLC realizations are called prototype circuits.E.n CN1.Analog Integrated Systems Design © P.) N odd.
E. we really would prefer Vout as a state variable instead of I5.sC4nV4(s) .741 Formulation of the State Variables of a Prototype Circuit State Variables: The state variables of a circuit are the current through an element or the voltage across it.R6nI5n(s) = 0 I5: However.sL1nI1(s) .) ECE 6414 .inductor cutsets and capacitor loops. This is achieved using Ohm’s law to get for the last two equations: Vout(s) I3(s) .R6n = 0 V 4: and sL5nVout(s) V 4(s) . • Convert this function to a form synthesizable by switched capacitor. Vin(s) .Analog Integrated Systems Design © P. respectively.I1(s)R0n . V4.V4(s) = 0 I3: V 4: I3(s) . I3. V2.E.I3(s) = 0 V2(s) .742 Writing the State Equations for a RLC Prototype Circuit Alternately use KVL and KCL for a loop and a node.sL3nI3(s) . Allen .2002 .sL5nI5(s) . A capacitor loop is a loop where only capacitors are in series. A low pass example: I1 I3 I5 + Vin (s n) R0n L1n C2n + L3n V2 C4n + L5n V4 R 6n + Vout (s n )  The state variables are I1 .sC4nV4(s) . The number of state variables to solve a circuit = number of inductors and capacitors . (The “correct” state variables will be the currents in the series elements and the voltage across the shunt elements.V2(s) = 0 I1: V 2: I1(s) .2002 Page 9.I5(s) = 0 and V4(s) . The approach: • Identify the “correct” state variables and formulate each state variable as function of itself and other state variables.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.Vout = 0 Vout: R6n ECE 6414 . and I5. An inductor cutset is a node where only inductors are connected.sC2nV2(s) . Allen .Chapter 9 – Section 7 (2/25/03) Page 9.
V4(s)] R' 1 Vout(s)] V4(s) = sR'C4n [V3'(s) .2002 Page 9. of a current Ij is defined as Vj’ = RIj where R’is an arbitrary resistance (normally 1 ohm). R0n R' '(s) V V V ( s ) V ( s ) 1' (s) = sL1n in 2 1 R ' 1 ' ' V2(s) = sR'C2n [V 1 (s) .E.Chapter 9 – Section 7 (2/25/03) Page 9.sL3n .2002 . Allen .Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P. Rewriting the five state equations using voltage analogs for current gives: V ’(s) 1 Vin(s) .V 3 (s) ] R' V3'(s) = sL3n [V2(s) .E. Vj’.743 Voltage Analogs of Current A voltage analog.Vout(s)] Note that each of these functions is the integration of voltage variables and is easily realized using switched capacitor integrators. (R0n + sL1n) .V 4(s) = 0 R V3’(s) Vout(s) sC V ( s ) 4 n 4 R R6n = 0 ECE 6414 .744 The State Variable Functions Solve for each of the state variables a function of itself and other state variables. ECE 6414 . R6n R6n Vout(s) = sL5n [V4(s) .Analog Integrated Systems Design © P. Allen .V2(s) = 0 V 1’: R V 2: V3’: V 4: and Vout: V 4(s) sL5nVout(s) .Vout = 0 R6n V ’(s) V1’(s) 3 sC V ( s ) = 0 2 n 2 R R V ’(s) 3 V2(s) .
ECE 6414 . SC Ladder Filters 1. 3.1349 H L3n =3.Chapter 9 – Section 7 (2/25/03) Page 9.E. Fortunately. TSB.78 . 1.745 General Design Procedure for Low Pass. and Ωn) determine the required order of the filter approximation.0009 H L1n=2. Switched Capacitor Filter using the Ladder Approach Design a ladder.Analog Integrated Systems Design © P. Low Pass. 2.73 and 9. ECE 6414 .Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P. Adjust your design so that it does not suffer the 6dB loss in the pass band.0911 F 1Ω Vout(s n)  Next. we must find the state equations and express them in the form of an integrator.) Write the state equations and rearrange them so each state variable is equal to the integrator of various inputs.5 kHz. Allen . fPB = 1kHz and fSB = 1. Also simulate the realization and compare to an ideal realization. (Note that this example should be identical with Ex.) From tables similar to Table 9.) Realize each of rearranged state equations by switched capacitor integrators. the above results can be directly used in this example.72 find the RLC prototype filter approximation. and Ωn (or APB.) From TBP. Give a schematic and component value for the realization.746 Example 9. ASB.2002 Page 9. use switchedcapacitor integrators to realize each of the five state functions and connect each of the realizations together. TSB = 25dB.0911 F C2n = 1. switched capacitor realization for a Chebyshev filter approximation to the filter specifications of TBP = 1dB.E. Finally.Fifthorder.2002 . Use a clock frequency of 20 kHz. we know that a 5thorder. Chebyshev approximation will satisfy the specification. RLC prototype filter is L5n =2.) Solution From previous work. Allen . 4.1349 H + Vin (sn) 1Ω + C 4n= 1. The corresponding low pass.
(6) yields the design of the capacitor ratios for the second integrator as ωPB Tn 2000π α12 = α22 = R’C2n = R’fcC2n = 1·20. α31C1 1 ’ ‘ jω) V' ( e 1 φ2 (2) V1(z) = z1 α11Vin(z) .E.2002 . replace z by 1 and z1 by sT.α31zV1(z) φ1 φ1 However.0911 = 0. (1) to Eq. ECE 6414 . double the value of α11 (α11 = 0. Therefore.718 which has one φ1 φ1 noninverting input and one inverting input.717 . 1 ‘ ‘ α V (z) . 1 ‘ ‘ V 1(sn) ≈ s T α V (s) .2879.E.1472 and R0nTn R0nωPB 1·2000π α31 = L1n = fcL1n = 20.V 3 (sn)] φ2 α22C2 + This equation can be realized by the switched V'3(ejω) φ2 capacitor integrator of Fig. (3) gives the capacitor ratios for the first integrator as R’Tn R’ωPB 1·2000π α11 = α21 = L1n = fcL1n = 20. since fPB < fc.2002 Page 9.Analog Integrated Systems Design © P.000·1.000·2.2879 + 2 = 5.α31V1(s) (3) n n 11 in Equating Eq.1472 + 0.718 . ECE 6414 .748 Example 9. 9. The second integrator has a total capacitance of 1 Second integrator capacitance = 0.78 – Continued α11C1 C1 V' (ejω) R0n R' 1 ' V ' (s ) Vin(ejω) φ1 L1n: V V ( s ) V ( s ) (1) φ 1 (sn) = sn L1n in 2 1 n n n 2 R' φ2 α21C1 This equation can be realized by the switched capacitor + integrator of Fig.717 which has one noninverting input V2(ejω) φ2 φ1 and two inverting inputs. (4) to Eq. Allen .2943) in order to get 0dB gain.1349 = 0. Equating Eq. 9. As before we write that Figure 9. (5) V2(z) = z1 12 1 Simplifying as above gives 1 ‘ ‘ (6) V2(sn) ≈ snTn α 12V 1 (sn) . Figure 9. Also.Realization of V2.1472) 1 First integrator capacitance = 2 + 0.Realization of V1'.78 – Continued α12C2 C2 V (ejω) 2 V'1(ejω) 1 φ1 φ2 ' ' C2n: V2(sn) = sn R'C2n [V (4) 1 (sn ) . Allen .1472 Assuming that R0n = R’ = 1Ω. The total capacitance of the first integrator is 2(0.000·2.α21V2(s) .Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.α22zV3(z) .747 Example 9.α22V3(sn) .Chapter 9 – Section 7 (2/25/03) Page 9.1472 = 10.47 units of capacitance.α21zV2(z) .1349 = 0.79 units of capacitance.
if R’ = R0n. (7) can be realized by the switched capacitor α23C3 + integrator of Fig.1047 + 2 = 11.α24Vout(sn) .2002 . As before we write that 1 ‘ α V (z) .Analog Integrated Systems Design © P.0911 = 0.719 . (9) yields the capacitor ratios for the third integrator as R’Tn R’ωPB 1·2000π α13 = α23 = L3n = fcL3n = 20.719 which has one noninverting V4(ejω) φ2 input and one inverting input.000·3.000·1. we note that fourth integrator is identical to the second integrator with the same total integrator capacitance.α24zVout(z) V4(z) = z1 .750 Example 9.Realization of V4.α23zV4(z) .Realization of V3'. (12) Equating Eq. ECE 6414 .Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.Chapter 9 – Section 7 (2/25/03) Page 9. (10) can be realized by the switched capacitor α24C4 + Vout(ejω) integrator of Fig.0009 = 0.2002 Page 9. 9.720 with one noninverting and φ2 φ1 φ1 one inverting input.55 units of capacitance ECE 6414 . Simplifying as above gives 1 ‘ (9) V 3(sn) ≈ snTn α13V2(sn) . 14 3 Assuming that fPB < fc gives 1 ‘ V4(sn) ≈ snTn α 14V 3 (sn) . (12) yields the design of the capacitor ratios for the fourth integrator as ωPB Tn 2000π α14 = α24 = R’C4n = R’fcC4n = 1·20. Figure 9.V4(sn)] (7) j ω V2(e ) φ1 φ2 φ2 Eq.E.78 – Continued α14C4 C4 V (ejω) R' 1 4 j ω ' V' ( e ) φ1 2 C4n: V4(sn) = sn R'C4n [V3 ( sn). For this circuit we get φ1 φ1 1 ‘ (8) V 3(z) = z1 α13V2 (z) . (10) to Eq.720 . Allen . Equating Eq.2879. 9. (11) Figure 9. In this case. (7) to Eq.749 Example 9.R6nVout(sn)] (10) φ2 φ2 Eq.78 – Continued R' α13C3 C3 V' (ejω) 3 L3n: V3'(sn) = sn L3n [V2(sn) .E. Allen . The third integrator has a total capacitance of 1 Third integrator capacitance = 0.α23V4(sn) .1047.
α31C1 Vin(ejω) φ1 2α11C1 φ2 φ2 C1 + φ1 φ2 α21C1 φ1 φ2 C2  φ1 φ2 V'1(ejω) α12C2 φ1 φ2 φ1 φ2 α13C3 φ2 α23C3 φ1 φ2 φ1 C4 φ2 φ1 φ2 α15C5 φ2 α25C5 φ1 φ2 φ1 ECE 6414 .79 = 42.Analog Integrated Systems Design + V4(ejω) +  V2(ejω) α22C2 φ1 C3 + φ1 φ2 V'3(ejω) α14C2 φ1 φ2 α24C4 φ1 C5 + φ1 φ2 Vout(ejω) © P.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.752 Example 9.Chapter 9 – Section 7 (2/25/03) Page 9. (15) yields the capacitor ratios for the fifth integrator as R6nTn R6nωPB 1·2000π α15 = α25 = L3n = fcL3n = 20.E. Simplifying as before gives 1 Vout(sn) ≈ s T α V (s ) .Realization of Vout. Allen .751 Example 9. 1 Fifth integrator capacitance = 0. ECE 6414 .E.78 – Continued Final realization of Ex.2002 Page 9. 9. 9.000·2.Vout(sn)] (13) out V4(ejω) φ1 φ2 φ2 The last state equation.79 units of capacitance We see that the total capacitance of this filter is 10. Allen . We note that Ex.53 + 5.1472 + 2 = 8.721 which V (ejω) + out φ2 has one noninverting input and one inverting input. n n 15 4 n Equating Eq.10 units of capacitance. can be realized by α25C5 the switched capacitor integrator of Fig. (14) Vout(z) = z1 α15V4 (z) .79 + 5.α25Vout(sn) (15) . φ1 φ1 For this circuit we get 1 Figure 9.2002 .05.47 + 8.78.1472 where R6n = 1Ω.721 .47 + 11.78 – Continued R6n α15C5 C5 V (ejω) L5n: Vout(sn) = snL5n [V4(sn) . (13).1349 = 0.α25zVout(z) . (13) to Eq. Eq. 1 which used the cascade approach for the same specification required 49.
754 Example 9.SUBCKT NC1 1 2 3 4 RNC1 1 0 6.753 Example 9.E.Chapter 9 – Section 7 (2/25/03) Page 9.E.SUBCKT DELAY 1 2 3 ED 4 0 1 2 1 TD 4 0 3 0 ZO=1K TD=25US RDO 3 0 1K .78 – Continued SPICE Input File: ******* 08/29/97 13:12:51 ********* ******PSpice 5.78 – Continued Simulated Frequency Response: 10 0 10 Magnitude (dB) 20 30 40 50 60 70 0 500 1000 1500 2000 2500 Frequency (Hz) 3000 3500 V4 Output Filter Output V1' Output Phase Shift (Degrees) V2 Output V3' Output 200 150 100 50 0 50 100 150 200 0 500 1000 1500 2000 2500 Frequency (Hz) 3000 3500 V1' Phase V4 Phase V2 Phase V3' Phase Filter Phase Comments: • Both passband and stopband specifications satisfied.1472 RNC2 4 0 6.7934 .1472 XNC2 1 4 14 DELAY GNC2 4 1 14 0 .78 : ladder filter *Node 5 is the output at V1' *Node 7 is the output at V2 *Node 9 is the output of V3' *Node 11 is the output of V4 *Node 15 is the final output VIN 1 0 DC 0 AC 1 ************************** * V1' STAGE XNC11 1 2 3 4 NC11 XPC11 7 8 3 4 PC1 XPC12 5 6 3 4 PC1 XUSC1 5 6 3 4 USCP XAMP1 3 4 5 6 AMP ************************** *V2 STAGE XNC21 5 6 19 20 NC2 XPC21 9 10 19 20 PC2 XUSC2 7 8 19 20 USCP XAMP2 19 20 7 8 AMP ************************** *V3' STAGE XNC31 7 8 13 14 NC3 XPC31 11 12 13 14 PC3 XUSC3 9 10 13 14 USCP ECE 6414 .ENDS NC1 © P. Allen .Analog Integrated Systems Design XAMP3 13 14 9 10 AMP ************************** *V4 STAGE XNC41 9 10 25 26 NC2 XPC41 15 16 25 26 PC2 XUSC4 11 12 25 26 USCP XAMP4 25 26 11 12 AMP ************************** *VOUT STAGE XNC51 11 12 17 18 NC1 XPC51 15 16 17 18 PC1 XUSC5 15 16 17 18 USCP XAMP5 17 18 15 16 AMP ************************* . • Some of the op amp outputs are exceeding 0 dB (need to voltage scale for maximum dynamic range) ECE 6414 .7934 XNC1 1 0 10 DELAY GNC1 1 0 10 0 .ENDS DELAY .2 (Jul 1992) ******** **** CIRCUIT DESCRIPTION **** *SPICE FILE FOR EXAMPLE 9.1472 XNC3 4 0 40 DELAY GNC3 4 0 40 0 .2002 . Allen .2002 Page 9.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.7_5 *Example 9.
2879 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.1472).ENDS NC4 . X32 (7 8) PC (0.4730 . E21 (3 0 0 6) 1E6. END.78 . E31 (5 0 0 8) 1E6.SUBCKT PC2 1 2 3 4 RPC1 2 4 3. C31 (8 5) 1.Analog Integrated Systems Design © P.2002 Page 9.0. END. GRID. V1 (1 0).2943 XNC3 4 0 40 DELAYGNC3 4 0 40 0 . X12 (3 2) PC (0.Chapter 9 – Section 7 (2/25/03) Page 9.4730 . C51 (10 100) 1.SUBCKT NC11 1 2 3 4 RNC1 1 0 3. E11 (4 0 0 2) 1E6. ECE 6414 .2943 XNC2 1 4 14 DELAY GNC2 4 1 14 0 . X13 (4 2) PC (0. END. S4 (3 4) #CLK.4730 XNC1 1 0 10 DELAY GNC1 1 0 10 0 .4730 XNC1 1 0 10 DELAY GNC1 1 0 10 0 . END.2879). C41 (9 7) 1. X52 (100 10) PC (0. X42 (100 9) PC (0.ENDS PC2 .2879).5521 . END.1472).1047 XNC3 4 0 40 DELAY GNC3 4 0 40 0 0.1047 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0.0 0. PERIOD 50E6. /***** V4 STAGE ****/ X41 (5 9) NC (0.1472). C11 (2 4) 1.2943 RNC2 4 0 3. /***** VOUT STAGE ****/ X51 (7 10) NC (0. INFREQQ 20 3000 LOG 80.2943). E41 (7 0 0 9) 1E6. PRINT VDB(100) VP(100). C21 (2 3) CAP1.SUBCKT NC2 1 2 3 4 RNC1 1 0 3. CIRCUIT /***** V1’ STAGE ****/ X11 (1 2) NC (0.1472).5521 .3978 .2879 RNC2 4 0 3.756 Example 9.ENDS PC3 ECE 6414 .SUBCKT PC3 1 2 3 4 RPC1 2 4 9.SUBCKT NC4 1 2 3 4 RNC1 1 0 3.1047). SUBCKT (1 4) NC (P:CAP).ENDS PC1 . TIMING.755 Example 9. Allen .1047 RNC2 4 0 9.2879). SUBCKT (1 4) PC (P:CAP1).5521 XNC1 1 0 10 DELAY GNC1 1 0 10 0 0. S4 (3 4) #CLK. C21 (6 3) 1. ANALYZE SSS. C11 (2 3) CAP. NOLIST. PRINT VDB(4) VP(4) VDB(3). CLOCK CLK 1 (0 25/50). PLOT VDB(100).3978XNC1 1 0 10 DELAY GNC1 1 0 10 0 .E.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.1047).7934 .2879 XNC2 1 4 14 DELAY GNC2 4 1 14 0 .78 – Continued SPICE Input File: . E51 (100 0 0 10) 1E6.ENDS NC3 .Continued Switcap2 Input File (The results are exactly the same as for the SPICE simulation) TITLE: EXAMPLE 9711 OPTIONS. S1 (1 2) #CLK.E. SET V1 AC 1. S2 (2 0) CLK. S1 (1 2) CLK. /***** V3’ STAGE ****/ X31 (3 8) NC (0. S3 (3 0) CLK. PRINT VP(3) VDB(7) VP(7). /***** V2 STAGE ****/ X21 (1 2) NC (0.2879).2002 .ENDS NC2 . Allen . X22 (3 2) PC (0.2879 XNC2 1 4 14 DELAY GNC2 4 1 14 0 0. END. END.1472 RNC2 4 0 6. S3 (3 0) CLK.2879 XNC3 4 0 40 DELAY GNC3 4 0 40 0 .SUBCKT NC3 1 2 3 4 RNC1 1 0 9.ENDS NC11 .7955 . S2 (2 0) #CLK.SUBCKT PC1 1 2 3 4 RPC1 2 4 6.
) Stray insensitive version of (a.E. (c.) Switched capacitor differentiatior circuit. low pass to high pass transformation.C (1z1)Vin(z) Hee(z) = = e C2 (1z1) 2 2 2 V in(z) ECE 6414 .) C2 + (a.726 .E. Allen . ECE 6414 .) Figure 9.) Identify the appropriate RLC Pass Network Pass Network prototype.Chapter 9 – Section 7 (2/25/03) Page 9. (b. 4.2002 e .).5)T e o vc1(n 0. low pass to normalized. switched capacitor filters using the ladder approach are achieved by applying the following normalized. 2. 1 sln = shn This causes the following transformation Chn = 1 Lln on the inductors and capacitors of the Lln RLC prototype: 1 C ln s ln → s hn Lhn = 1 Cln Design Procedure: Normalized LowNormalized High1. 3.5)T = vin(n 1)T φ2: (n0.z1 C V in(z) = .758 Switched Capacitor Derivative Circuit C1 Vin(z) C1 φ2 φ1 C2 φ2 φ1 Vout(z) Vin(z) C1 φ2 φ2 φ1 φ1 φ1 + (b. The problem: The realizations are derivative circuits. low pass circuit to meet the specifications.) Realize the state functions using switched capacitor circuits.5)T = 0 C1 vin(n) e vin(n1) + e C2 e vout (n) C1 e C1 e e vout(n )T = .C2 vin(n )T + C2 vin(n 1)T Vout(z) C1 e C1 e C1 C1 e e ∴ Vout(z) = C V in(z) . Allen .) φ2 Vout(z) Vin(z) C1 φ2 C2 Vout(z) + (c.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.2002 Page 9. high pass transformation on the RLC prototype circuit.) Transform each inductor and capacitor by the normalized.757 High Pass Switched Capacitor Filters Using the Ladder Approach High pass.Analog Integrated Systems Design © P.) Modification to keep op amp output from being discharged to ground during φ1.5)T < t < (n )T and o vc2(n 0.(a. Transfer function: φ1: (n1)T < t < (n 0.) Choose the state variables and write the state functions.
5H V2 =1Ω .2002 . Solution? 1. State Variable Eqs: I1 R 0n Vin=I1R0n+snC1hn+V2 → I1 = snC1hn [Vin .High Pass.E.) Use inverters.R ] → V = s L [ 2 n 2hn R .Chapter 9 – Section 7 (2/25/03) Page 9. low pass Butterworth prototype filter.C 1 e = = 2jω sin(ωT/2) e C2 C2 ejωT/2 2 or jωTC1 sin(ωΤ/2) jω sin(ωΤ/2) (εjωΤ/2) = ejωT/2 = .) Redefine the polarity of the voltages at internal nodes (180° phase reversal). jωT/2 .V2] → V1’ = snC1hnR [Vin .ejωT/2 C1 C1 C1 e j ω T jωT/2 Hee(ejωT) = .760 Example 9. switched capacitor ladder filter starting from a thirdorder. Assume the cutoff frequency is 1kHz and the clock frequency is 100kHz. to get integrators where possible.759 Frequency Response of the Derivative Circuit Replace z by ejωT to get. 3.I3R4n] → Vout = snR4nC3hn [V2 . Switched Capacitor Ladder Filter Design a high pass.out =2F =1Ω pass filter is shown.79 .2πC1: Hee(ejωT) 5 10 π 1 0 Continuous Time Discrete Time Phase 0 90° 180° ω 270° Discrete Time ωc ωc 2 Continuous Time ω ωc 0 ωo= 10 ωc 2 ωc ECE 6414 .Analog Integrated Systems Design © P. ECE 6414 .R4n ] n 2hn n 2hn 4n 4n I3 V2 = snC3hn + I3R4n → I3 = snC3hn [V2 .2002 Page 9. 2. Error)x(Phase Error) where ωo = C2/(C1T). Use the doubly terminated structure.) Rearrange the eqs.I1R0n .Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P. normalized. Allen . Allen . Frequency Response for C2 = 0.R V 1’V 2] V2 V2 Vout Vout V1’ Vout I1 = s L + I3 = s L + R → V2 = snL2hn [I1 .Vout] Problem! Derivative circuit only has inverting inputs.E. Solution A thirdorder L3n C3hn L1n C1hn R0n R0n prototype filter =1H =1F I3 =1Ω =1H =1Ω =1F s = 1 transformed to the + ln shn + + L2hn C2n R R normalized high I 4 n 4 n 1 Vout V Vin Vin =0.C2 ωΤ/2 ωo ωΤ/2 = (Ideal)x(Mag.
Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.762 Example 9.V 1’ R0n V 1’ R R ' ' ' ' V 1=snC1hnR [Vin. Vin V1' α11C1 α11z V1' φ2 φ2 ∴ V 1’ (z) = z 1 V 1’ (z) . Therefore the rewrite the first state equation as: Note that V1 .V 1’ Vout V1’ Vout out V2 = snL2hn[ R .Continued Make the first eq. Σ capacitances =100.E.06283.79 .R4n ] → V2 = snL2hn[ R . ∴ Vout(z) = (1z1)[α13 V2 (z) + α23Vout(z)] Vout(s) ≈ sT [α13 V2 (s) + α23Vout(s)] α13C3 V2 Vout α23C3 φ2 C3 Vout φ2 φ1 φ1 + φ1 φ2 φ2 Normalizing T by ωPB gives Vout(sn) = snTn [α13 V2 (sn) + α23Vout(sn)] R4nC3hn 1·105 ∴ α13 = α23 = Tn = 2π·103 = 15. Allen .E.5·105 ∴ α12 = α22 = T = 2π·103 = 7.V1 ' andV2 = . we write that α11 V 1’ (s) ≈ sT V 1’ (s) .V2 . reverse the sign of V2 and V1’.V2 . α11 Tn 2π·103 ' (sn)α21Vin(sn)α31 V2 (sn) → α11=R C ' (sn) ≈ s T V 1 = V1 1·105 =0.49 units of C ECE 6414 .2002 .Chapter 9 – Section 7 (2/25/03) Page 9.α31 V2 (s) Normalizing this equation gives.9577 if R = R0n = 1Ω.2002 Page 9. ' = .α31 V2 (z) + φ1 φ1 Assuming that z 1 ≈ sT and z ≈ 1. α21=α31=1 n n 0n 1hn ECE 6414 .Continued L2hn: This state eq.915 if R4n = 1Ω.Vout] α31C1 C1hn: V2 α21C1 This state equation can be realized by the SC C1 integrator shown with two inverting unswitched inputs.761 Example 9. can be realized by the SC differentiator circuit shown with two inputs. into an integrator. n L2hn: This state equation can be realized by the SC differentiator circuit shown with two inputs.α21Vin(s) .α21Vin(z) . and use one inverter.R V1V2] →V1=snC1hnR0n +R0n(Vin V2) → V 1 =snC1hnR0n R0n(Vin+ V2 ) V 1’ V .R4n ] → V2 =snL2hn R + R4n Vout = snR4nC3hn [.79 .Analog Integrated Systems Design © P. ∴ V2(z) = (1z1)[α12 V 1’ (z) + α22Vout(z)] V2(s) ≈ sT [α12 V 1’ (s) + α22Vout(s)] α12C2 V1' Vout α22C2 C2 φ2 V2 C C V2 φ2 φ1 φ1 + φ1 φ2 + φ2 Normalizing T by ωPB gives V2(sn) = snTn [α12 V 1’ (sn) + α22Vout(sn)] L2hn 0. Allen .
V1(s)] sL1bn(1/sC1bn) s/C1bn s/C1bn = 2 where Z1bn = sL1bn + (1/sC1bn) = 2 s + (1/L1bnC1bn) s +1 ∴ s/R0nC1bn R 0n V1(s) = Vin(s) . fc = 128kHz.2002 ECE 6414 .R V 2’(s) .E.7659F  Applying the lowpassbandpass transformation on the elements gives. low pass to bandpass transformation. In this case.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.6B The state equations for this circuit can be written as illustrated below.) Identify the appropriate RLC Normalized Lbn = BW 1 LowPass ωr Cln prototype.710 . V1(s) Z1bn Vin(s) = I2(s) + Z1bn R0n + V1(s) → V1(s) = R0n [Vin(s) .763 Bandpass Switched Capacitor Filters Using the Ladder Approach Bandpass switched capacitor ladder filters are obtained from low pass RLC prototype circuits by applying the normalized. low pass to normalized bandpass transformation given as 1 ωr 1 ωr sb = ω + sbn + sln = r B W / ω ) B W s ( s b r bn This causes the following ωr Lln Cbn = BW 1 Lbn = transformation on the inductors and ωr Lln BW Lln capacitors of the RLC prototype: Cln sn → Design Procedure: 1. low pass circuit to meet Network Normalized Bandpass Network the specifications. R0n Vin(sn) C1bn = ωr C 1ln BW L2bn = C2bn = ωr L2ln 1/L2bn BW L4bn = + V3  ωr L4ln C4bn = BW 1/L4bn R5n + Vout(sn)  + I2 C 3bn = V1 L1bn = ω rC 3ln 1/ C 1 bn BW I4 L3bn = 1/C3bn Ex.) Realize the state functions using switched capacitor circuits. bandpass. Allen .74) 1. the state functions will be secondorder. ECE 6414 .) Transform each inductor and capacitor by the normalized. Butterworth Bandpass.8478F 0.I2(s)R0n . switched capacitor ladder filter.8478H L 4n=0. 3.Analog Integrated Systems Design .Chapter 9 – Section 7 (2/25/03) Page 9. Allen .E. 2. The filter is to have a center frequency (ωr) of 3kHz and a bandwidth (BW) of 600 Hz.Design of a 4thOrder.) Choose the state variables and write the state functions.764 ωr s bn + 1 sbn BW Cbn = ωr Cln BW Example 9. bandpass functions which can be realized by switchedcapacitor biquads. Solution R0n =1Ω L2n=1.V 1’(s) 2 s +1 (1) © P.2002 Page 9.7659H The low pass normalized prototype + + + filter is shown (Note that this form is slightly V (s ) R5n V (sn ) C = C out = 3n in n 1n =1Ω different than the form used in Table 9. 4. SC Ladder Filter Design a fourthorder.
let Also.Analog Integrated Systems Design © P. we get (α4s/T) .2002 Page 9. Therefore. we shall use the lowQ biquad to realize the above state equations because it can have both inverting and noninverting inputs (α4C2).Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) Example 9. For the lowQ biquad.V3(s)] → sR/L2bn [V (s) . if we let α1 = α3 = α6 = 0.E. biquad BP realization. Allen . Allen . of inputs) ECE 6414 .Continued I2(s) = Y2bn[V1(s) .710 .E. biquad realization. © P.1473 c 128x105 Now all that is left is to design α4 for each stage (assuming R0n = R5n = R = 1Ω).Continued Note that the highQ biquad can only have inverting inputs.Chapter 9 – Section 7 (2/25/03) Page 9. switched capacitor.766 ECE 6414 .(α 4 s n /T n ) Normalizing by Ωn gives ee(sn) ≈ Hee(s) ≈ 2˚ H → s + (α2α5/T˚2) sn2˚+ (α2α5/Tn2) All the α2’s and α5’s will be given as: α2α5 = Tn2 = Ωn2T 2 = ωr2/fc2 = (2π)2(fr/fc)2 2π·fr 2π·3x103 α2 = α5 = f = = 0. switched capacitor. the sum of capacitances per stage will be: α2 α4 α5 2 Σ capacitances/stage = αmin + αmin + αmin + αmin x (no.2002 .710 . High Q.765 Example 9.V (s)] V2’(s) = 3 s 2+1 1 (2) V 2 ’(s) Vout(s) s/RC3bn R V3(s)=Z3bn(I2(s)I4(s))=Z3bn → V ( s )= V ’( s )V (3) 3 2 out R R R 2 5n s +1 5n and I4(s) =Y4bn[V3(s)Vout(s)] → Vout(s) = R5nY4bn[V3(s)Vout(s)] sR5n/L4bn [V3(s)Vout(s)] or Vout(s) = s 2+1 How to realize? Consider the bandpass form of the lowQ and highQ biquads: α2C1 φ1 φ2 (4) α2C1 α5C2 α6C2 φ2 C1 + e V1(z) φ1 φ2 C2  φ2 φ1 e Vout(z) e φ1 φ 2 φ1 α4C1 C1 Ve (z) 1 + φ1 φ2 φ2 Vin(z) α3C1 α5C2 φ1 φ2 C2 + Vout(z) e Vin(z) φ2 φ1 e α4C2 φ1 + Low Q. Therefore.
03848 There will be one noninverting input (Vin) and two inverting inputs (V2’ and V1).E.03848.2002 ECE 6414 .03848 + 0.03848 + 3 = 62.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.E.Analog Integrated Systems Design + φ1 α23 = α53 = 0.1473 φ 1α43C23 α43C23 φ2 φ2 α24 = α52 = 0.1437) Σ capacitances = 0.Continued Total capacitance of this example is 414.767 Example 9.768 Example 9.01594 + 0.50 units of capacitance Stage 4 Same as stage 1 except Σ capacitances = 61. 2 2(0. α44 = 0.α5 Using this simplification gives: C21 Vin φ 1 α 41 φ2 α 41 C21 α 21 = α51 = 0. Σ capacitances = 145. There will be one noninverting input (V3) and one inverting input (Vout).1473 φ2 Vout φ 1 φ2 φ1 φ2 V1 φ α C C22 φ V3 φ2 α44C42 α44C42 φ 2 42 22 α 42 1 1 © P. 2(0.8478 = 0.01594 Tn L2bn There will be one noninverting input (V1) and one inverting input (V3).9.01594 + 2 = 145.1473 α 41 C21 φ2 V' 2 α22 = α52 = 0. α43 = 0. ECE 6414 . Realization: α5C2 φ1 φ1 φ2 C2 φ2 + Ex.1437) 2 Σ capacitances = 0.710 .44 units of capacitance Stage 2 α42 ω r·BW Tn·BW R 2π·600 = → α = = = 42 ωrL2ln fc·ωr·L2ln 128x103·1.44 units of capacitance.88 units of capacitance. Allen .2002 Page 9.710 .713B C1 φ2 φ1  α2C1 φ2 φ1 α2.1473 φ1 φ1 .Chapter 9 – Section 7 (2/25/03) Page 9.7658 = 0.01594 There will be one noninverting input (V2’) and one inverting input (Vout).Continued Stage 1 Tn α41 ω r·BW 1 2π·600 = → α = = = 41 Tn R0nC1bn R0nC1bn fc·ωr·C1ln 128x103·0.50 = units of capacitance Stage 3 Same as stage 2. Allen .
769 General Approach to Designing Switched Capacitor Ladder Filters Choose State Variables Write State Equations Use SC Integrators to Design Each State Equation Low Pass Switched Capacitor Filter Normalized LP to Normalized High pass Transformation Low pass Prototype RLC Ckt.E.E.Chapter 9 – Section 7 (2/25/03) Page 9. The primary problem of aliasing is that there are undesired passbands that contribute to the noise in the desired baseband.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P. to Design Each State Equation Bandpass Switched Capacitor Filter Normalized LP to Normalized Bandpass Transformation Normalized LP to Normalized High pass Transformation Choose State Variables Write State Equations Use SC BS Ckts.2002 .Spectrum of a discretetime filter and a continuoustime antialiasing filter. Eliminate Lcutsets and Cloops Normalized LP to Normalized Bandpass Transformation Choose State Variables Write State Equations Use SC Differentiators to Design Each State Equation High Pass Switched Capacitor Filter Choose State Variables Write State Equations Use SC BP Ckts. T(jω) T(j0) T(jωPB) AntiAliasing Filter Baseband ωcωPB ωc+ωPB 2ωcωPB 2ωc+ωPB ω 0 ωc 2ωc ωPB 0 ωPB Figure 9. Allen .2002 Page 9.728 .Analog Integrated Systems Design © P.770 ANTIALIASING IN SWITCHED CAPACITOR FILTERS A characteristic of circuits that sample the signal (switched capacitor circuits) is that the signal passbands occur at each harmonic of the clock frequency including the fundamental. ECE 6414 . to Design Each State Equation Bandstop Switched Capacitor Filter ECE 6414 . Allen .
771 Noise Aliasing in Switched Capacitor Circuits In all switched capacitor circuits.E. ECE 6414 . From higher bands Noise Aliasing Baseband fcfsw .Analog Integrated Systems Design © P.E. simulators like SPICE do not permit the multiplication of the thermal noise. The gain of the voltage dependent source should be 2fB/fc..) Convert the switched capacitor filter to a continuous time equivalent filter by replacing each switched capacitor with a resistor whose value is 1/(fcC). Another approach is to assume that the resistors are noisefree and build a noise generator that represents the effect of the noise of vBN2. It can be shown that the aliasing enhances the baseband noise voltage spectral density by a factor of 2fsw/fc. Therefore.) A voltage source that is dependent on the voltage across this resistor can be placed at the input of an op amp to implement vBN2. fc+fsw f Simulation of Noise in Switched Capacitor Filters The noise of switched capacitor filters can be simulated using the above concepts.772 .731 .5fc fc 0 fsw fB Figure 9.) Put a zero dc current through a resistor identical to the one being modeled. to make the resulting noise to approximate that of the switched capacitor filter. Unfortunately. Therefore.2002 . Magnitude fcfB fB fc+fB 0. 2. 2.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P. 1.2002 Page 9. Allen . 1. . Allen .Chapter 9 – Section 7 (2/25/03) Page 9. ECE 6414 . a noise aliasing occurs from the passbands that occur at the clock frequency and each harmonic of the clock frequency.) Multiply the noise of this resistance by 2fB/fc.Illustration of noise aliasing in switched capacitor circuits. . The resulting noise source model along with the normal noise sources of the op amp will serve as a reasonable approximation to the noise in a switched capacitor filter.) Model all resistors that represent switched capacitors in the same manner.. the baseband noise voltage is 2kT 2f 2kT /C 2kT B 2 vBN = fcC 2fB = C fc = OSR volts(rms)2 where OSR is the oversampling ratio. the baseband noise voltage spectral density is kT/C 2fsw 2kT 2 2 eBN = f x f = f C volts /Hz c sw c Multiplying this equation by 2fB gives the baseband noise voltage in volts(rms)2. 3.
Analog Integrated Systems Design © P. Thus.) (b. we get two design equations which are 1 ωo = mnRC m 1 Q = (n +1) n The approach to designing the components of Fig.2002 Page 9. Allen .Chapter 9 – Section 7 (2/25/03) Page 9.E. n. Low Pass Filter C2 R1 R3 K=1 C4 Vout (s) Voltage Amplifier Vin (s) K=1 (a.773 CONTINUOUS TIME ANTIALIASING FILTERS Sallen and Key. Allen .774 Design Equations for The Unity Gain.729a is to select a value of m compatible with standard capacitor values such that 1 m ≤ 4Q 2 .1 ± 2mQ 2 14mQ . 9. Sallen and Key Low Pass Filter Equating Vout(s)/Vin(s) to the standard secondorder low pass transfer function. With K = 1. these filters have excellent linearity because the op amp is in unity gain. This equation provides two values of n for any given Q and m.E. Then. the use of either one produces the same element spread. 1 R1R3C2C4 1/mn(RC)2 Vout(s) = = 1 s 2 + (1/RC)[(n+1)/n]s + 1/mn(RC)2 1 1 Vin(s) + s2+s + R3C2 R1R3C2C4 R1C2 where R3 = nR1 = nR and C4 = mC2 = mC. It can be shown that these values are reciprocal.) Transfer function: K TLP(0) ωo2 R1R3C2C4 Vout(s) = = 1 ω o 1 1 K 1 Vin(s) 2+ s+ω 2 + s2+s + + s o R1C2 R3C2 R3C4 R1R3C2C4 R3C4 Q We desire K = 1 in order to not influence the passband gain of the SCF.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P. ECE 6414 .2002 . ECE 6414 . Incidentally. Unity Gain. can be calculated from 1 1 2 n= 2mQ 2 .
C4 = 250pF and R3 = 450kΩ.Analog Integrated Systems Design © P. SecondOrder.776 A Negative Feedback.Chapter 9 – Section 7 (2/25/03) Page 9. It is readily apparent that the antialiasing filter will require considerable area to implement.E.707.5.730 . 9. Let us choose C = C2 = 500pF. Let us choose m = 0. Allen . This filter uses frequencydependent negative feedback to achieve complex conjugate poles. low pass filter. m = 0.711 .730. Low Pass AntiAliasing Filter Another continuoustime filter suitable for antialiasing filtering is shown in Fig.77a if Q = 0. 1 2TLP(0)ωoQC C4= 4Q2(1+TLP(0))C 1 2ωoQC R1= R2= C5=C + Vin R3= 1 2(1+TLP(0))ωoQC Vout Figure 9. Thus.5 → n = 1.Analog Integrated Systems Design Chapter 9 – Section 7 (2/25/03) © P.2002 .775 Example 9.225x103. lowpass filter using Fig. one has to try different values to see what is best for the given situation (typically the area required). This gives R = R1 = 450kΩ. ECE 6414 .E.Application of the SallenKey AntiAliasing Filter Use the above design approach to design a secondorder.5 for this example. This gain of this circuit in the passband is determined by the ratio of R2/R1. use ωo = to find the RC product → RC = 0. These choices guarantee that Q = 0.707 and fo = 1 kHz Solution We see that m should be less than 0. 9. Allen . 1 Now.2002 Page 9.A negative feedback realization of a secondorder. ECE 6414 . mnRC At this point.
2832)(2)(106) = 56.54 kΩ and 2 R3 = (2)(6. and fo = 10kHz. Such circuits can operate to within half of the clock frequency.2002 Page 9. • The accuracy of the signal processing is proportional to the capacitor ratios. ECE 6414 . Solution Let us use the design equations given on Fig.Analog Integrated Systems Design © P. Allen . Assume that C5 = C = 100pF. 9. SecondOrder.E.2832)(106) = 112.2832)(106) = 112. we get C4 = (8)(0.81 SUMMARY • Switched capacitor circuits have reached maturity in CMOS technology.5)C = 400pF.27 kΩ Unfortunately we see that again because of the passive element sizes that antialiasing filters will occupy a large portion of the chip. ECE 6414 . lowpass active filter of Fig. Allen .730.712 . Therefore.54 kΩ 2 R2 = (2)(6. • SPICE or SWITCAP permits frequency domain simulation of switched capacitor ckts.2002 .E.730 to design a lowpass filter having a dc gain of 1. • The switched capacitor circuit concept was a pivotal step in the implementation of analog signal processing circuits in CMOS technology.Design of A Negative Feedback.Analog Integrated Systems Design Chapter 9 – Section 8 (2/25/03) © P. • Switched capacitor circuits have been developed for: Amplification Integration Differentiation Summation Filtering Comparison Analogdigital conversion • Approaches to switched capacitor circuit design: Oversampled approach – clock frequency is much greater than the signal frequency zdomain approach – the specifications are converted to the zdomain and directly realized.777 Example 9. The resistors are 2 R1 = (2)(1)(6. Q = 1/ 2 . LowPass Active Filter Use the negative feedback. 9. secondorder. • Clock feedthrough and kT/C noise represent the lower limit of the dynamic range of switched capacitor circuits.Chapter 9 – Section 7 (2/25/03) Page 9.
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