319 views

Uploaded by Marc Jacob Manguray

A Lab Report for CMPE012L .

save

- Logic Gates
- Logic Gates
- Digital Lab Report
- Basic Logic Gates
- Digital Electronics Lab Report No. 01
- 4 the TTL Logic Series
- 206 C1 Lab Report
- 1.a. Gate Verification (1) EL LAB
- Basic Logic Gates
- Physics Project
- logic gates
- Basic Gates and Functions.docx
- BEDD Lab
- Basic Logic Gates
- Digital Logic Design
- NAND GATE
- TSPICE
- 48025049-logic-gates
- Cad Lab Manual
- Digital Logic Gates
- dica
- Introduction to Digital Logic Families.pdf
- 441 Spice Project2 Writeup
- VL7301
- Intel Interview Questions
- Logic Gates
- Refresher-Elex 6(April, 2007)
- VLSI Placement Papers
- balugdi1
- 9 Electronics
- Entrevista
- 287a Study on Quality Function Deployment in Construction Projects PDF
- Personal Likes
- Ecuaciones Diferenciales Separables y Sus Técnicas
- Lembar Biodata Peserta
- Bahaya Keberadaan Tambang bagi Lingkungan.doc
- 2.4-Herramientas_nube.pdf
- MIT22_51F12_Ch9
- 6. TEMA 1
- t-table.pdf
- 11155544jkkjhgt.txt
- aaa-andrew-loomis-dibujo-tridimensional-espac3b1ol.pdf
- DBM-CSC Form No. 1 Position Description Forms
- D4001-13_Standard_Test_Method_for_Determination_of_Weight-Average_Molecular_Weight_of_Polymers_By_Light_Scattering.pdf
- Unit 2
- Oracle Manufacturing Analytics
- SILABUS Dasar Desain Grafis.docx.docx
- UFV毕业证菲莎河谷大学毕业证Q/微457202606UFV学历认证UFV托福成绩单UFV本科毕业证UFV硕士毕业证University of the Fraser Valley
- Resumen Capitulo VIII y Capitulo IX
- Song
- Ingles.docx
- Harga Akseseris Wanita Terbaru
- Beyond Vision - Essays on the Perception of Art
- corbata nudo part 1
- 0405.pdf
- 2W8xRoLa
- a-an-some-any
- October 2018 CTE Spotlight - BSD
- LEVANTAMIENTO
- 2014_0224_Aspen_Capital_Cost_Estimator_Overview-AACE_25_Feb_2014.pdf

You are on page 1of 3

Lewis Due: Jan 18, 2014 Lab Partner: NONE Title: Lab 1: Introduction to Digital Logic Purpose: The purpose of this lab is to get familiar with using the MultiMedia Logic (MML) application and how to simulate a simple logic schematic. The other parts of the lab will show the properties of Boolean algebra and how it applies and affects digital logic gates. Procedure: Part A of the lab was mostly following instructions provided by the lab sheet and the YouTube video that showed the basics of using the MML software. De Morgan’s Law (A’B’ = (A+B)’) is demonstrated by first connecting each switch A and B to an inverter, then connecting those inverters to an AND gate, after that, the AND gate is connected to an LED output, this represents A’B’. Next, connect the same A and B switches to a NOR gate, and connect the NOR to a different LED output; this will represent (A+B)’. The testing results in both outputs show that A’B’ and (A+B)’ are exactly the same, therefore results as proof for De Morgan’s law. For Part B, The truth table is deconstructed using the “Sums of Products” technique (See Table 1and Part B1a). Then, each AND combination is given its own AND gate with three inputs, proper NOT inverters are also included for each respective gate based on the non-simplified algorithm. The AND gates are then connected to a three-input OR gate, which is then connected to the output. For the second piece of Part B, only NAND gates are used for the logic. In order to do so, the “Sums of Products” algorithm needed to be simplified so that only NAND gates were used (Algorithm Part B2a). The second construction was almost a complete redesign of the first construction. First, the inverters for switch A were merged to become just one inverter. Second, switch B also gets a single inverter also, which then connects with a NAND gate along with the now inverted A. Next, A’ is also connected to a different NAND gate, this time it’s connected with switch C. C gets no inverters at all. Then the NANDs are connected to another NAND which is then connected to an output. To make testing more obvious, instead of making an entirely different set of switches for the second construction, the switches for the first construction are connected to the second. Because both constructions have identical outputs, this means that the implementation of the NAND gates is correct. After doing the simplification for Part B, Part C’s algorithm follows Part B’s up until only one of each switch is mentioned (minimization steps are detailed in Algorithm Part C). Its respective gates are then connected to each switch and are then connected to an output. The output is the same as the implementations in Part B which means that the implementation is correct.

) a.) Other Data NOT gates * transistors in NOT gates: 6*2 3-input AND gates * transistors in 3-in AND gates: 3*8 3-input OR gates * transistors in 3-in OR gates: 1*8 # of Transistors = 38 2.Algorithms and Other Data TABLE 1: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 OUTPUT 1 1 0 1 0 0 0 0 A’B’C’ A’B’C A’BC PART A: De Morgans = (A+B)’ = A’B’ Since A’B’ = OUTPUT and (A+B)’ = OUTPUT Then.) A’B’C’ + A’B’C + A’BC = OUTPUT A’B’(C’ + C) + A’BC A’B’(1) + A’BC A’B’ + A’BC A’(B’+BC) A’(B’+B’C+BC) A’(B’+C(B’+B)) A’(B’+C(1)) A’(B’ + C) A’B’ + A’C ((A’B’)’(A’C)’)’ = OUTPUT (Sums of Products) (Distributive) (Complement) (Identity) (Distributive) (Factor) (Distributive) (Complement) (Identity) (Distributive) (De Morgans) .) SUMS OF PRODUCTS: A’B’C’ + A’B’C + A’BC = OUTPUT b. A’B’ = (A+B)’ PART B: 1.) a.

it was much easier to progress to the rest of the lab. and how to run a simple simulation was understood and accomplished. The original design for the first circuit has 38 transistors. that using De Morgan’s law. 4 from the inverter gates. 8 in a 3-input AND gate 8 in a 3-input OR gate. AND and OR gates have more transistors because the basic construction of those gates rely on an inverted NAND or NOR gate which adds another CMOS pair to the build. logic gates. Basic placement of switches. As expected. De Morgan’s Theorem was proven through a simple MML simulation as well as implemented during the challenge of reducing an algorithm consisting of many OR and AND logics to a purely NAND based construction. Conclusion: Familiarity of the MML program has been achieved. output devices. 6 from the OR gate.b. The numbers of transistors in each logic construction were calculated and recorded based on the number of gates times the number of transistors in that specific gate added all together (Algorithm Part B1b and Part B2b). A’B’ + A’C if we make x’ = A’B’ and y’ = A’C then it because (x’y’)’ becomes ((A’B’)’(A’C)’)’. . 4 in a 2-input NAND gate. The final circuit (Part C) has 16 transistors. This provides a good introduction to what Boolean algebra and digital logic can do in terms of simplifying complex inefficient structures into something simpler to understand. while the purely NAND redesign has 16 transistors. Although once that obstacle was solved. The basics of labeling the constructions properly and how to connect gates with wires were also learned. Other Information: There are 2 transistors in an inverter. and 6 from the AND gate.) Other Data NOT gates * transistors in NOT gates: 2*2 NAND gates * transistors in NAND gates: 3*4 # of Transistors = 16 PART C: A’B’C’ + A’B’C + A’BC = OUTPUT A’B’(C’ + C) + A’BC A’B’(1) + A’BC A’B’ + A’BC A’(B’+BC) A’(B’+B’C+BC) A’(B’+C(B’+B)) A’(B’+C(1)) A’(B’ + C) = OUTPUT (Sums of Products) (Distributive) (Complement) (Identity) (Distributive) (Factorization) (Distributive) (Complement) (Identity) Challenges: The simplification of the algorithm towards a purely NAND gate logic structure was rather tricky because of the lack of experience and familiarity regarding Boolean algebra and the process of changing an OR logic into an AND logic. if (x’+y’) can become (x’y’)’ then for. It turns out for example.

- Logic GatesUploaded byShabnam Zakir
- Logic GatesUploaded byAgrippa Mungazi
- Digital Lab ReportUploaded bychalla_seshagiri
- Basic Logic GatesUploaded byVasu Reddy
- Digital Electronics Lab Report No. 01Uploaded byShuvodip Das
- 4 the TTL Logic SeriesUploaded byRayeYagami
- 206 C1 Lab ReportUploaded byJustin Kan
- 1.a. Gate Verification (1) EL LABUploaded byHimangshu Baruah
- Basic Logic GatesUploaded byVenkatesh Subramanya
- Physics ProjectUploaded byApoorva Panchal
- logic gatesUploaded byS Prasad Shiva Pulagam
- Basic Gates and Functions.docxUploaded byMrinal Kanti Roy
- BEDD LabUploaded byBharathi Muni
- Basic Logic GatesUploaded byHifdzul Malik Zainal
- Digital Logic DesignUploaded bynayab
- NAND GATEUploaded byNeeraj Sharma
- TSPICEUploaded byMohamed Shimil
- 48025049-logic-gatesUploaded byDheeraj Kumar
- Cad Lab ManualUploaded bySougata Ghosh
- Digital Logic GatesUploaded bydambokkazone
- dicaUploaded byandhracolleges
- Introduction to Digital Logic Families.pdfUploaded bygutterbc
- 441 Spice Project2 WriteupUploaded bykmt340
- VL7301Uploaded bySaranya Ramaswamy
- Intel Interview QuestionsUploaded byRuchi Gujarathi
- Logic GatesUploaded byLalit Kumar Kataria
- Refresher-Elex 6(April, 2007)Uploaded byvon kervy onrade
- VLSI Placement PapersUploaded byAsn Roy
- balugdi1Uploaded bybalakrishna_batta
- 9 ElectronicsUploaded byKalai Selvi