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Cadence Tutorial

for Cadence version 6.1
Inkwon Hwang
Feb, 2010

1. Create Library ................................................................................................................ 2
2. Schematic......................................................................................................................... 3
A. Create a cell view ............................................................................................................ 3
B. Draw a schematic............................................................................................................ 4
3.
A.
B.
C.
D.
E.
F.
G.

Run Spectre simulation .................................................................................................. 9
Launch ADE (Analog Design Environment) L............................................................ 9
Basic setup ..................................................................................................................... 10
Model Libraries ............................................................................................................ 10
Simuli ............................................................................................................................. 11
Choose a type of analysis - transient........................................................................ 13
Select signals to plot...................................................................................................... 14
Run simulation.............................................................................................................. 14

4.
A.
B.
C.
D.
E.
F.
G.
H.
I.

Layout ............................................................................................................................ 16
Create a layout .............................................................................................................. 16
Add an instance - nmos ................................................................................................ 17
Add more instances – pmos, ptap, ntap, and m1_ploy ............................................. 18
Draw metal1 .................................................................................................................. 19
Run DRC ....................................................................................................................... 20
Add pins......................................................................................................................... 22
Extract ........................................................................................................................... 24
Run LVS......................................................................................................................... 25
Run Spectre simulation ................................................................................................ 26

1. Create Library
A. Tools Æ Library Manager

B. File Æ New Æ Library

C. Give a name and attach it to a technology library

Create a cell view . Schematic A.2.

Draw a schematic i.B. Don’t modify length unless you have a special purpose. . You should select a NCSU_Analog_Parts library. Add instances – pmos You can modify Width of transistors.

Add instances – nmos. vdd.ii. and gnd .

iii. Add wires: Create Æ Wire .

InputOutput type is for supply changes. .iv. input and output. We will discuss about this later. and it is necessary only for layout. Add pins: Create Æ Pin We have for different types of direction. we only use two types. For schematics.

Let’s move on the next phase. .Now. we completed a schematic design.

I will show an example for a schematic. A. This section is for both schematics and layouts. Launch ADE (Analog Design Environment) L Launch Æ ADE L . Run Spectre simulation We will run spectre simulation. You can do the same thing for a layout.3.

You can modify project directory.B. Model Libraries You can download a library file at the DEN blackboard. Basic setup Check if your simulator is spectre. . C.

Simuli Define input signals include supply nets .D.

Global sources Input .

Give Stop time which means how long you want to simulate C.transient You can choose ‘dc’ if you want to do dc analysis A. Do not Noise check E. Choose a type of analysis . Select moderate as accuracy defaults D. Check Enabled Transient . Choose tran B.E.

G.F. Select signals to plot Outputs Æ To Be Plotted Æ Select On Schematic Click a signal (Pin) on a schematic/extracted. Run simulation Simulation Æ Run .

.If you see a waveform like above picture. you followed every step properly. Good job!.

It is for check if your layout is identical to the schematic or not. this step is very important. but it has additional step which is LVS check. After determining your design variables by schematics. Hence. Design flow of layouts is very similar to one of schematics. you need to draw layouts. you may lose significant points for that. They don’t consider physical features like parasitic capacitances. Create a layout . Schematics are for verifying your design very roughly. A.4. Layout It’s time to draw layout. If your logic doesn’t pass this step.

B. .nmos You can modify width of transistors. Add an instance .

Add more instances – pmos. and m1_ploy You can select alternate view of a layout.C. . ptap. ntap. Try ‘Shift + f’ and ‘Ctrl + f’.

D. Draw metal1 There are few ways for drawing metal. It’s quite convenience than others. which means 300nm (3 λ). you should select metal1 on LSW window. You can draw metal layer simply by clicking .3. Default width for metal1 is 0. but I recommend you use ‘path’. Create Æ Shape Æ Path First of all.

Run DRC This step checks if your layout follows design rules.E. Verify Æ DRC .

After modifying layout. It is because a gnd metal layer is too close to an nmos transistor. run DRC again. There is no error!! .We have five errors.

we have 4 pins for the layout. which are ‘in’. Hence. Pins are for assigning signals to physical device. Create Æ Pin Check ‘Display Terminal Name’ if you want to see pin name on the layout. ‘out’. ‘gnd!’. Click ‘Display Terminal Option . and ‘vdd!’. so we assign voltage level of gnd and vdd by using pins. which are ‘in’ and ‘out’.F. Add pins We had two pins on a schematic.

.

It’s something like compiling a code. It is done by extracting. otherwise your extracted design won’t have parasitic capacitances. Select ‘Extract_parastic_cap’ as a switch name. Extract A layout is just a picture. .G. you should convert it to the other format. If you need to run simulation using the layout.

More complicated design. Run LVS As I mentioned before. If there are errors. you can check the results by clicking ‘Output’ button. . this step is very important for your grading. Verify Æ LVS Keep in mind. more time will be required for debugging LVS. ‘Error Display’ also might be helpful. You SHOULD compare your schematic with EXTRACTED. I hope all of you will see the following window.H.

I. Let’s do the same thing for more complicated designs. Congratulations!! You followed all steps I prepared. Go to step ‘4. Run Spectre simulation’. Run Spectre simulation It is same as schematics. .