COM 353 Microprocessors

Computer Organization and Introduction to Microprocessors
Prof. Dr. Halûk Gümüşkaya
haluk.gumuskaya@gediz.edu.tr haluk@gumuskaya.com http://www.gumuskaya.com

Prof. Dr. Halûk Gümüşkaya
haluk@gumuskaya.com http://www.gumuskaya.com

Computer Engineering Department

Saturday, October 06, 2012

1

Saturday, October 06, 2012

2

Lecture Outline
1. Introduction
2. Views of Computer Systems 3. Processor Based System 4. Processor 5. Memory 6. Input/Output 7. Interconnection: The Glue 8. Historical Perspective • Introduction
 Basic Terminology and Notation

Outline
• Processor
 Execution cycle  Pipelining  RISC and CISC

Views of Computer Systems • User’s view • Programmer’s view
 Advantages of high-level languages  Why program in assembly language?

• Memory
 Basic memory operations  Design issues

• Architect’s view • Implementer’s view

• Input/Output • Interconnection: The glue • Historical Perspective

3

4

Views of Computer Systems 3.Introduction • Some basic terms         Computer organization Computer architecture Computer design Computer programming User’s view Programmer’s view Architect’s view Implementer’s view 5 1. Processor 5. Introduction 2. Interconnection: The Glue 8. Historical Perspective • Various views of computer systems 6 From Personal Computer to Mobile Devices Personal Computer: Components RAM storage tape control unit hard disk floppy CD-ROM registers flags ALU cache central processing unit keyboard monitor modem address memory buses ROM data I/O mouse data address 7 8 . Processor Based System 4. Memory 6. Input/Output 7.

A User’s View of Computer Systems A Programmer’s View • Depends on the type and level of language used • A hierarchy of languages     Machine language Assembly language High-level language Application programs increasing level of abstraction • Machine-independent  High-level languages/application programs • Machine-specific  Machine and assembly languages 9 10 A Programmer’s View (cont’d) A Programmer’s View (cont’d) • Machine language  Native to a processor  Consists of alphabet 1s and 0s 1111 1111 0000 0110 0000 1010 0000 0000B • Assembly language  Slightly higher-level language  Human-readable  One-to-one correspondence with most machine language instructions inc 11 count 12 .

count1 AX.count3 AX.A Programmer’s View (cont’d) • Readability of assembly language instructions is much better than the machine language instructions » Machine language instructions are a sequence of 1s and 0s A Programmer’s View (cont’d) • Assemblers translate between assembly and machine languages  TASM  MASM  NASM Assembly Language inc mov and add result class_size.45 mask.count2 AX.AX 16 .128 marks.10 Machine Language (in Hex) FF060A00 C7060C002D00 80260E0080 83060F000A • Compiler translates from a high-level language to machine language  Directly  Indirectly via assembly language 13 14 A Programmer’s View (cont’d) A Programmer’s View (cont’d) • High-level languages versus low-level languages In C: result = count1 + count2 + count3 + count4 In Pentium assembly language: mov add add add mov 15 AX.count4 result.

AX AX.AX 18 C result++.sum AX.10 A Programmer’s View (cont’d) • Most high-level language instructions need more than one assembly instruction C Assembly Language size = value. size = 45.z sum.value size. mov mov AX.128 marks. marks += 10. mask1 &= 128.45 mask1.y AX.x AX. mov add add add mov 17 A Programmer’s View (cont’d) • Instruction Set Architecture (ISA)  An important level of abstraction  Specifies how a processor functions » Defines a logical processor Advantages of High-Level Languages • Program development is faster » High-level instructions – Fewer instructions to code • Various physical implementations are possible  All logically look the same  Different implementations may differ in » Performance » Price • Program maintenance is easier » For the same reasons as above • Programs are portable » Contain few machine-dependent details – Can be used with little or no modifications on different types of machines » Compiler translates to the target machine language » Assembly language programs are not portable • Two popular examples of ISA specifications  SPARC and JVM 19 20 . sum += x + y + z.A Programmer’s View (cont’d) • Some simple high-level language instructions can be expressed by a single assembly instruction Assembly Language inc mov and add result size.

Why Program in Assembly Language? • Two main reasons:  Efficiency » Space-efficiency » Time-efficiency Architect’s View • Looks at the design aspect from a high level  Much like a building architect  Does not focus on low level details  Uses higher-level building blocks » Ex: Arithmetic and logical unit (ALU)  Accessibility to system hardware • Space-efficiency  Assembly code tends to be compact • Consists of three main components  Processor  Memory  I/O devices • Time-efficiency  Assembly language programs tend to run faster » Only a well-written assembly language program runs faster – Easy to write an assembly program that runs slower than its high-level language equivalent 21 • Glued together by an interconnect 22 Architect’s View (cont’d) Architect’s View (cont’d) Page 24 23 24 .

Implementer’s View • Implements the designs generated by architects  Uses digital logic gates and other hardware circuits Implementer’s View (cont’d) • Example  Processor consists of » Control unit » Datapath – ALU – Registers • Implementers are concerned with design of these components 25 26 Implementer’s View (cont’d) Implementer’s View (cont’d) 27 28 .

Historical Perspective 29 30 Microprocessor Based System: Collection of Addressable Registers  We Microprocessor Busses  Address can view the entire system –microprocessor.A Processor Based System 1. Introduction 2. and I/O ports are external registers. RWM. Processor Based System 4. RWM (RAM). Input/Output 7. • and those exist in the ROM. Processor 5. Bus – input bus to memory device specifying location of data to read/write Bus – input/output bus to memory device containing data value being read or written. ROM. Memory 6. • Those registers reside within the microprocessor are internal registers. Interconnection: The Glue 8. Views of Computer Systems 3. Bus – control signals of a processor for memory and I/O devices  Data  Control 31 32 . and I/O ports– as a collection of addressable registers.

Views of Computer Systems 3. Processor 5. Input/Output 7. Processor Based System 4. Memory 6. Interconnection: The Glue 8. Introduction 2. Historical Perspective 33 34 Processor Integration Processor • Execution cycle – Fetch – Decode – Execute  Early computers had many separate chips for the different portions of a computer system • von Neumann architecture » Stored program model – No distinction between data and instructions – Instructions are executed sequentially 35 36 .Address. Data and Control Buses 1.

Modern microprocessors (general purpose Processors) also integrate memory onchip for faster access. memory.  Microcontrollers are intended to be single chip solutions for systems requiring low to moderate processing power. 37 38 Microcontrollers Microcontrollers integrate all of the components (control. I/O) of a computer system into one integrated circuit. and arithmetic logic unit (ALU) in one integrated circuit (one chip). External memory and I/O components are still required. Memory integrated on the microprocessor is called cache memory.Microprocessors  Modern Processors    First microprocessors placed control.  Pipelining: Overlapping Processor Operations • Pipelining  Overlapped execution  Increases throughput 39 40 . registers.

Pipelining (cont’d) • Another way of looking at pipelined execution RISC and CISC Processors • RISC and CISC designs  Reduced Instruction Set Computer » Uses simple instructions » Operands are assumed to be in processor registers – Not in memory – Simplifies design Example: Fixed instruction size  Complex Instruction Set Computer » Uses complex instructions » Operands can be in registers or memory – Instruction size varies » Typically uses a microprogram 41 42 CISC and RISC Implementations Microprogramming • Variations of the ISA-level can be implemented by changing the microprogram 43 44 .

Input/Output 7. Introduction 2. Interconnection: The Glue 8. Memory 6. Processor Based System 4.1. Processor Memory • Ordered sequence of bytes  The sequence number is called the memory address  Byte addressable memory » Each byte has a unique address » Almost all processors support this 5. Historical Perspective • Memory address space  Determined by the address bus width  Pentium has a 32-bit address bus » address space = 4GB (232)  Itanium with 64-bit address bus supports » 264 bytes of address space 45 46 4 Memory (cont’d) • Memory unit  Address  Data  Control signals » Read » Write Memory (cont’d) 47 48 . Views of Computer Systems 3.

3. Read the data from the data bus 5. Drop the memory write signal • In Pentium. 2. Place address on the address bus 2. Drop the memory read signal 5. a simple write also takes three clocks » » » Clock 1: steps 1 and 3 Clock 2: step 2 Clock 3 : steps 4 and 5 49 50 Byte Ordering Byte Ordering (cont’d) • Multibyte data address pointer is independent of the endianness  100 in our example • Little-endian  Used by Pentium • Big-endian  Default in MIPS and PowerPC • On modern processors  Configurable 51 52 .Memory (cont’d) • Read cycle 1. 4. Wait for the memory to retrieve the data » Introduce wait states if using a slow memory Memory (cont’d) • Write cycle 1. a simple read takes three clocks cycles » Clock 1: steps 1 and 2 » Clock 2: step 3 » Clock 3 : steps 4 and 5 • In Pentium. Place address on the address bus Place data on the data bus Assert memory write signal Wait for the memory to retrieve the data » Introduce wait states if necessary 4. Assert memory read control signal 3.

Processor 5. Memory 6. Historical Perspective 55 56 . Input/Output 7. Interconnection: The Glue 8. Introduction 2. Processor Based System 4. Views of Computer Systems 3.Design Issues • Slower memories Problem: Speed gap between processor and memory Solution: Cache memory – Use small amount of fast memory – Make the slow memory appear faster – Works due to “reference locality” Design Issues (cont’d) • Size limitations  Limited amount of physical memory » Overlay technique – Programmer managed  Virtual memory » Automates overlay management » Some additional benefits 53 54 Design Issues (cont’d) 1.

Historical Perspective 59 60 . Views of Computer Systems 3.Input/Output • I/O devices are interfaced via an I/O controller  Takes care of low-level operations details Input/Output (cont’d) • Several ways of mapping I/O  Memory-mapped I/O » Reading and writing similar to memory read/write » Uses same memory read and write signals » Most processors use this I/O mapping  Isolated I/O » Separate I/O address space » Separate I/O read and write signals are needed » Pentium supports isolated I/O – Also supports memory-mapped I/O 57 58 Input/Output (cont’d) • Several ways of transferring data  Programmed I/O » Program uses a busy-wait loop – Anticipated transfer 1. Introduction 2. Memory 6. Input/Output  Direct memory access (DMA) » Special controller (DMA controller) handles data transfers » Typically used for bulk data transfer  Interrupt-driven I/O » Interrupts are used to initiate and/or terminate data transfers – Powerful technique – Handles unanticipated transfers 7. Processor Based System 4. Interconnection: The Glue 8. Processor 5.

Introduction 2. Views of Computer Systems 3. Memory 6. IEEE 1394 (FireWire) 61  Bus arbitration 62 1. Input/Output 7. Interconnection: The Glue Historical Perspective • The early generations  Difference engine of Charles Babbage • Vacuum tube generation  Around the 1940s and 1950s • Transistor generation  Around the 1950s and 1960s 8. AGP. I/O write • Uses several buses at various levels  On-chip buses » Buses to interconnect ALU and registers – A. PCMCIA  External buses » Serial. B. I/O read. and C buses in our example » Data and address buses to connect on-chip caches  Bus operations » A bus transaction may perform one or more bus operations – Pentium burst read Transfers four memory words Bus transaction consists of four memory read operations  Internal buses » PCI. USB. memory write.Interconnection • System components are interconnected by buses  Bus: a bunch of parallel wires Interconnection (cont’d) • Bus is a shared resource  Bus transactions » Sequence of actions to complete a well-defined activity » Involves a master and a slave – Memory read. Processor 5. Historical Perspective • IC generation  Around the 1960s and 1970s • VLSI generation  Since the mid-1970s 63 64 . parallel. Processor Based System 4.

MMX + Pro teknolojisi 9.2 milyon transistör. IBM PC/AT’nin ilk işlemcisi Intel’in ilk 32-bit işlemcisi. 0. 60 – 200 MHz. 300 – 450 MHz. 1. 108 Khz İlk genel amaçlı CPU.5 mikron. 1 mikron 80286 yoluna sahip 80386 80386 + FPU + cache.8 mikron 3. superscalar mimari 5. 64-bit veri yolu) Pentium Pentium Pentium Pentium Pentium Pentium Pro MMX II III IV (1993) (1995) (1997) (1997) (1999) (2001) Mikroişlemciler Mikrodenetleyiciler 65 66 80x86 Evolution: First Microprocessors 8085.5 milyon transistör.Intel CPU Family 1971-1972 4 ve 8bit Intel CPU Family Processor 4004 Year 1971 1972 1974 1976 1978 1979 1982 1982 1982 1985 1988 1989 1993 1995 1997 1997 1999 2001 Register/ Data Bus Width 4/4 8/8 8/8 8/8 16/16 16/8 16/16 16/8 16/16 32/32 32/16 32/32 32/64 36/64 36/64 36/64 36/64 36/64 Address Space 640 byte 16K 64K 64K 1M 1M 1M 1M 16M/1G* 4G/64T* 4G/64T* 4G/64T* 4G/64T* 64G/64T* 4G/64T* 64G/64T* 64G/64T* … Önemli Özellikler İlk mikroişlemci. 6 mikron. 8-bit veri yollu 8086 8086 + I/O 8088 + I/O 134000 transistör. P6 mimarisi: çoklu dallanma tahmini.5 milyon transistör. 450– 500 MHz.8 mikron.5 milyon transistör. 5 – 10MHz. 0.25 mikron.5 milyon transistör.18 mikron. 6200 transistör İlk 16-bit CPU. 3 mikron 1981’de üretilen IBM PC deki ilk işlemci. 3D grafikler ve daha fazla multimedya desteği … 8008 8080 8085 4004 8008 1974-76 8-bit 8080 8085 1978-1979 16-bit 8086 8088 1976 8-bit 8048 8051 8086 8088 80186 1982 16-bit 80286 1982 16-bit 80186 80188 8-bit 80251 80151 16-bit 8096 80196 80188 80286 80386DX 1985-1988 32-bit 80386DX 80386SX 1985 32-bit 80386 80386SX 80486DX 1989 32-bit 80486DX Pentium Pentium Pro Pentium MMX Pentium II Pentium III Pentium IV Pentium Mikroişlemcileri (32-bit iç mimari.1 milyon transistör. 0. tümdevre üzeri L2 cache. 10 mikron İlk 8-bit işlemci.32 mikron. 275000 transistör. and 80286 67 68 . 1. veri akışı analizi ve tahmini yürütme 4. 2300 transistör. 0. 0. 29000 transistör. multi-medya ekleri 7. 8086. 6000 transistör Gelişmiş 8080.

80386 and 80486 Pentium I 69 70 Pentium Pro Pentium II 71 72 .

Springer. Dandamudi.  Mikroişlemciler ve Bilgisayarlar. Basım. S. 2011. 75 . 2003. P. 1060 pages.Pentium III Pentium IV 73 74 Acknowledgement The slides have been based in-part upon original slides of a number of books including:  Fundamentals of Computer Organization and Design. H. Gümüşkaya. ALFA. 6.

Sign up to vote on this title
UsefulNot useful