You are on page 1of 59

Lecture 9

Today: Basics of A/D and D/A. Spartan-3 analog I/O and DDS. Digilent family boards. Printed copy of today’s lecture slides. VHDL materials on handouts web page Pedroni, data sheets, etc. Please keep the lab clean and organized. Last one out should close the lab door!!!!

Handouts: Read: References:

Nothing is more difficult, and therefore more precious, than to be able to decide. — Napoleon I.
EECS 452 – Fall 2009 Lecture 9 – Page 1/59 Mon 9/28/2009

This week’s reminders

◮ ◮ ◮

HW 3b due this Wednesday. HWs 2 and 3 due this Friday. Project team formation and topic selection next Wed night.

EECS 452 – Fall 2009

Lecture 9 – Page 2/59

Mon 9/28/2009

ADC and DAC
ADC (analog to digital converter) and DAC (digital to analog converter) are two critical elements in most digital systems.
◮ ◮ ◮

We will take a look at the basic idea behind these. We will introduce the A/D and D/A on S3-SB and other related IO. You will get to practice these in Lab 4. Discretize it in time: sampling or time quantization. Discretize it in value/amplitude: quantization or amplitude quantization. Reverse quantization: assign real value to each quantile Reverse sampling: interpolation (reconstruction)

What do you do when you have an analog waveform?
◮ ◮

What do you do when you have a sequence of discrete numbers?
◮ ◮

EECS 452 – Fall 2009

Lecture 9 – Page 3/59

Mon 9/28/2009

Visualize sampling & reconstruction
Analog waveform 1 amplitude 0.5 0 −0.5 −1 0 1 amplitude 0.5 0 −0.5 −1 0 1 amplitude 0.5 0 −0.5 −1 0

0.2

0.4

0.6

0.8 x 10

1
−3

Analog waveform.

Time quantized waveform

0.2 0.4 0.6 0.8 1 −3 x 10 Reconstructed time quantized waveform

Discretize in time: sampling using ADC.

0.2

0.4 0.6 time in seconds

0.8 x 10

1
−3

Reconstruct: order hold.

zero-

EECS 452 – Fall 2009

Lecture 9 – Page 4/59

Mon 9/28/2009

Comments on sampling

Given a real valued lowpass spectrum with bandwidth BW (zero to null), the sampling frequency 2BW is often called the Nyquist sampling rate/frequency.

There is good reason behind this. You may recall from 216 and/or 451. We will take another more realistic look at this in another two lectures.

In practice one often should sample at a rate of at least two or three times the Nyquist sampling rate. It is also common practice to take the analog signal through an anti-alias filter before sampling.

We will see more details on this later, but this is basically a low pass filter to get rid of high frequency components in the analog signal. The AIC23 used on the C5510 DSK has built in anti-alias filters. The cutoff frequencies change with the selected sampling rate.
Lecture 9 – Page 5/59 Mon 9/28/2009

EECS 452 – Fall 2009

bass low E is 82. Telephone nominally passes range 300 Hz to 3200 Hz. Voice: fundamental around 150 Hz. female fundamental about 200 Hz. Piano: Normal young adult hearing range is 20 Hz to 20. 27.000 Hz. EECS 452 – Fall 2009 Lecture 9 – Page 6/59 Mon 9/28/2009 .Interesting audio frequencies Many waveforms can have energy beyond a band of interest. male fundamental about 120 Hz.5 Hz.046. overtones to about 5 kHz.5 Hz (A0) to 4816 Hz (C8). soprano high C is 1.4 Hz.

Common sampling rates Common sampling rates: standard telephone system wideband telecommunications home music CDs professional audio DVD-Audio instrumentation.1 kHz 48 kHz 192 kHz extremely fast EECS 452 – Fall 2009 Lecture 9 – Page 7/59 Mon 9/28/2009 . RF. video 8 kHz 16 kHz 44.

Dual slope integration. Pencil and paper.Most common A/D techniques There are several additional ways in which the conversion of an analog waveform into a series of numbers can be implemented. R-2R resistive ladders. Successive approximation. EECS 452 – Fall 2009 Lecture 9 – Page 8/59 Mon 9/28/2009 . Delta-sigma (DSP systems in their own right). charge redistribution. Flash.

Figure from Atmel AD023 data sheet. they are successively switched so as to match the D/A output to the captured voltage. EECS 452 – Fall 2009 Lecture 9 – Page 9/59 Mon 9/28/2009 . high MHz is possible. Successive approximation converters can also be pipelined to develop a few bits at a time as values pass through the pipeline. Quantization: uses a local voltage reference bits of a D/A converter. Common accuracies range from 8 to 16 bits.Successive approximation A/D Sampling: uses a track and hold to capture a voltage on a capacitor. This provides high speed at the cost of a small of delay. High speed.

but the comparators are controlled by clock tics.Flash A/D (1/2) Multiple comparators: determine all bits at the same time. What is the output for reference 4V and input 2.5? How many possible output values? EECS 452 – Fall 2009 Lecture 9 – Page 10/59 Mon 9/28/2009 . Note that there is no explicit sampling. VERY fast.

Flash A/D (2/2) CLK CLK ° ° VRT Analog Input Preamp Comparator 256 CLOCK BUFFER DEMUX CLOCK BUFFER 255 DRB (DATA READY) D8 (OVR) D7 (MSB) D6 D8B D7B DRB (DATA READY) D8B (OVR) D7B (MSB) 152 D6B D5B D4B 256 TO 8 Bit Decoder With Metastable Error Correction D5B ECL Output Buffers And Latches 151 D3B D2B D4B D3B D2B D1B D0B (LSB) DRA (DATA READY) DRA (DATA READY) D8A (OVR) D7A (MSB) 128 1:2 DEMULTIPLEXER D5 D1B D0B VRM 127 D4 D8A D7A D6A D5A D4A D3A 64 D3 63 D2 D5A D4A D3A D2A D1A D0A (LSB) 2 D1 D2A D1A 1 D0 (LSB) D0A VRB Figure from Fairchild Semiconductor SPT7750 data sheet. EECS 452 – Fall 2009 Lecture 9 – Page 11/59 BANK A D6A BANK B D6B Mon 9/28/2009 .

Delta-sigma A/D ¢.

§    Σ  ¡¢£¤¥¦§¨ ¤¨¢£ .

¥ ¥ £ ¥£ ¥£¤§©¨¢¤ ¨  ¥£¤§©¨¢¤ ¨ Basic idea is to save bandwidth by sending the changes (often encoded using a single bit) in a waveform rather than the full waveform. EECS 452 – Fall 2009 Lecture 9 – Page 12/59 Mon 9/28/2009 . Samples very fast. Exploits the cheap availability and small size of today’s digital logic. More details to come in a later lecture.

invert the most significant bit. Most positive value is 2B − 1. Two’s Complement. Most negative value is −2B −1 . EECS 452 – Fall 2009 Lecture 9 – Page 13/59 Mon 9/28/2009 . Two common mappings from voltages to numbers are: Offset Binary. Most positive value is 2B −1 − 1. Most negative value is 0. To convert between the two formats.Going from voltages to numbers Consider a B -bit A/D converter.

Often write ∆V simply as ∆ and refer to it as a quanta. EECS 452 – Fall 2009 Lecture 9 – Page 14/59 Mon 9/28/2009 .Two’s complement scaling Given a B -bit A/D output value: most positive value is 2B −1 − 1. Assume a maximum input voltage excursion of ±Vp Assign voltage −Vp to −2B −1 . This will be seen to give zero DC offset with a zero DC input. Note that these limits are slightly asymmetric. That is. Usually place zero volts mid input step. Voltage step size per count change is ∆V = Vp /2B −1 for uniform quantization. the voltage change required for a increment of one in the A/D converter output value. most negative value is −2B −1 .

75 −0.5 −0. One quanta change ↔ one ∆ voltage change.5 0.25 0. Change in number by 1 is one quanta.75 Quantizer analog input level 1 . ∆ = Vp /2B −1 Usually place A/D bits into computer word most significant bits. Note the placement of the zero input relative to the output count. EECS 452 – Fall 2009 Lecture 9 – Page 15/59 Mon 9/28/2009 4−bit linear quantizer input to output transfer function 8 6 Quanizer integer output 4 2 0 −2 −4 −6 −8 −1 −0. Plot’s x-axis is normalized.25 0 0.Uniform quantization Converts analog voltages into B-bit numbers.

Why? What if you have a weak signal? ◮ Idea: progressive taxation ◮ ◮ EECS 452 – Fall 2009 Lecture 9 – Page 16/59 Mon 9/28/2009 . ◮ International Telecommunication Union ITU-T Recommendation G.711. use smaller steps for small input values. Instead of using equal step sizes. ◮ Originally developed for use in digital parts of the telephone system.Non-uniform quantization: mu-law companding COMpression and exPANDing of digitized waveforms (companding).

This has an equivalent effect of assigning small steps when input is small. µ = 255. Lecture 9 – Page 17/59 Mon 9/28/2009 EECS 452 – Fall 2009 . and large steps when input is large. Now apply a uniform quantizer. 3-bit. y = Qµ sgn(x) ln(1 + µ |x |/V ) ln(1 + µ) . ◮ ◮ ◮ “stretch” the small values and “compress” the large values. ◮ ◮ ◮ Implemented as logarithmic fixed-point number sign. Performance roughly equivalent to 14-bit uniform (linear) encoding.µ -law transfer function How to implement? ◮ ◮ Idea one: come up with unequal step sizes for the entire range. characteristic and 4-bit mantissa (8-bit code word). idea two: let’s skew the signal instead. V normalizes the input signal.

Offset Error Gain Error Differential Nonlinearity (DNL) Error Integral Nonlinearity (INL) Error Absolute Accuracy (Total) Error Aperture Error A good reference is TI’s Understanding Data Converters. SLAA013.A/D converter worries The real world seems to always get in the way. EECS 452 – Fall 2009 Lecture 9 – Page 18/59 Mon 9/28/2009 . July 1995.

10. 14. 16 and 24 bits. Information is lost. ◮ We know if we don’t sample fast enough we get into trouble. A word having B bits can represent 2B numeric values. ◮ ◮ ◮ ◮ ◮ Digital values are most often represented using binary words. Common A/D word sizes are 8.Errors introduced in A/D Now let’s take a look at the amount of error we introduce in the process of A/D. The more A/D bits the greater the quality of the sampled data. analog values (uncountably infinite) are converted into a finite number of values. EECS 452 – Fall 2009 Lecture 9 – Page 19/59 Mon 9/28/2009 . In quantization and encoding. details to come later. 12.

A wide sense stationary random process is one whose first and second moments are time invariant and whose autocorrelation function is invariant to time shift. Quantization error values are independent of each other. This leads to the concept of a white spectrum. The statistics of the quantization errors are wide sense stationary.Quantizer model and assumptions ◮ The quantization errors are uniformly distributed over the range from −∆/2 to ∆/2. The quantization errors are independent of the waveform being quantized. Mon 9/28/2009 ◮ ñxåz nì~åíáòÉê nE=F ñxåz=Z nEñxåzF ◮ ◮ ñxåz ñxåz=Z ñxåz=H Éxåz Éxåz EECS 452 – Fall 2009 Lecture 9 – Page 20/59 .

6 Sinewave period 0.7 0.4 0.8 0.7 0.5 −1 0 0.5 0.3 0.2 0.5 0.8 0.9 1 Sinewave quantization error using 4−bit quantizer 1 0.5 Quanta 0 −0.1 0.4 0.5 Amplitude 0 −0.1 0.2 0.Uniformly quantized sinewave and error Sinewave quantized using 4−bits 1 0.9 1 EECS 452 – Fall 2009 Lecture 9 – Page 21/59 Mon 9/28/2009 .6 Sinewave period 0.5 −1 0 0.3 0.

In actual practice these assumptions have proven to give surprisingly good results. Don’t forget this! EECS 452 – Fall 2009 Lecture 9 – Page 22/59 Mon 9/28/2009 . They forget that the theory is only an approximation to reality.Really? Do You Really Expect Me to Believe Those Assumptions? No. But you do have to start somewhere and these provide a relatively simple starting point. Systems designed based on them often work as expected. when designers run into problems they often think it is because of something they did. On occasion.

Quantization noise model Éxåz ñxåz H H ñxåz=Z ñxåz=H Éxåz The noise mean and variance are: µe 2 σe = = 0. 2 Vp ∆2 = 12 12 · 22B −2 Signal-to-noise ratio: SQNR SQNR(dB) = = = EECS 452 – Fall 2009 12 · 22B Px Px = Px = 3 2 2 2B 2 Pe 3Vp Vp 10 log10 SQNR = 10 log10 constant given Px + 6B Lecture 9 – Page 23/59 Mon 9/28/2009 3Px 2B 2 + 10 log10 2 Vp .

Peak to RMS worries Most signals are much more unstructured than is a sinusoid and one has to worry about the peak-to-rms ratio in order to minimize clipping. OFDM (orthogonal frequency division multiplexed) communication systems generally have a significant peak-to-rms dynamic range problem. This means using an rms level somewhat reduced from the maximum safe sine wave value. Basically one need to set the “normal” level and allocate some “head room” for when the signal is large. Choosing a maximum safe level is often done in a somewhat hand wavy manner. EECS 452 – Fall 2009 Lecture 9 – Page 24/59 Mon 9/28/2009 . For example working with a music selection with soft passages and loud passages.

Reversing the quantization is easy.Now onto D/A . . What’s the input-output mapping? Is there anything wrong with this scheme? EECS 452 – Fall 2009 Lecture 9 – Page 25/59 Mon 9/28/2009 . . One of many ways: voltage divider.

EECS 452 – Fall 2009 Lecture 9 – Page 26/59 Mon 9/28/2009 .1 0 −3 −2 −1 0 1 Frequency (Hz) 2 3 x 10 4 ◮ ◮ Theoretically we can perfectly reconstruct if we sample fast enough. .5 Magnitude 0.2 0. In practice sampling itself is imperfect. Spectrum of the reconstructed waveform 0.Reversing the sampling process .3 0. The dashed line shows the effects of the zero-hold on the spectrum magnitude. and 3500 Hz. . It possesses images of the baseband spectrum. Using a zero-order hold D/A converter. fs = 8000 Hz. 1000 Hz. Example D/A output: ◮ ◮ ◮ Three tones: 200 Hz.4 0.

Anti-image filter Zero-order hold has weighted (shaded) the spectrum. Filter may be solely analog or switched capacitor analog cascade. Low pass cutoff will nominally be somewhat below fs /2. Might correct for the zero-order hold amplitude shading. Low pass filter needed to attenuate/remove the images. May have concerns about phase distortion. EECS 452 – Fall 2009 Lecture 9 – Page 27/59 Mon 9/28/2009 .

EECS 452 – Fall 2009 Lecture 9 – Page 28/59 Mon 9/28/2009 . D/A: the reverse of the above processes. Next: the ADC and DAC on Spartan-3 and their use in Lab 4. A/D: sampling and quantization.Quick summary of A/D and D/A ◮ ◮ ◮ ◮ Basics of converting an analog signal to digital form.

S3. Connectors used to connect off board devices to the FPGA. Four push buttons. A special board (MIB) is needed for the S3SB in order to add these. The type of external memory.Digilent Spartan-3 family boards Digilent sells a variety of design platforms based on Spartan-3 variants. These differ in terms of ◮ ◮ ◮ ◮ ◮ ◮ Spartan-3 sub-family. Size of the FPGA used. DRR2. S3E. At least four 6-pin PMod connectors. Eight slide switches. static RAM. The over voltage protection included on the FPGA lines. Lecture 9 – Page 29/59 Mon 9/28/2009 These boards have in common ◮ ◮ ◮ ◮ EECS 452 – Fall 2009 . paged and so on. Four digit seven segment display. extra and/or different off board connectors.

Regulated voltage : 3.3 Volts. Connector A2 cabled to C5510 External Peripheral Interface connector. Module Interface Board on B1 is used to convert 40-pin connector to 8 6-pin PMod connection positions. Supplied with Parallel Port JTAG programming cable. Lecture 9 – Page 30/59 Mon 9/28/2009 ◮ ◮ EECS 452 – Fall 2009 . Signal lines are NOT 5 Volt tolerant!!!! Three 40-pin connectors. A2 and B1.Spartan-3 Starter Board used by EECS 452 ◮ ◮ ◮ ◮ ◮ ◮ ◮ ◮ ◮ FPGA : XC3S1000 (106 gates) Package : FT256 (a ball grid package) Speed: -4 (not the fast part) EPROM : XCF04S (larger than on base board) Board powered by 5 Volt supply. Cable supported by IMPACT and ExPort. A1.

CON2. DIN1. ENC.Some available PMod boards ◮ ◮ ◮ ◮ ◮ ◮ ◮ ◮ Dual 12-bit A/D converter. Given sufficient lead time we can create our own project specific boards. AD1. and many more. SWITCH. Dual BNC. AMP1. Four slide switches. EECS 452 – Fall 2009 Lecture 9 – Page 31/59 Mon 9/28/2009 . Speaker/headphone amplifier. DA2. Digital input. Rotary encoder. Dual 12-bit D/A converter.

J5.Digilent D/A. J5→pmod_c and J7→pmod_d. We have modified our MIB boards to have sockets in positions J1. A/D and MIB P1: CS P2: Data1 J1 Connector ADC 1 Filter P1 J2 Connector P2 P3: Data 2 P4: Clk P5: GND P6: Vcc AD1 Circuit Diagram ADC 2 P3 P4 P5 P6 Filter From Digilent data sheets. J7 and pins in the other positions. The UCF naming is J1→pmod_a. J3→pmod_b. J3. EECS 452 – Fall 2009 Lecture 9 – Page 32/59 Mon 9/28/2009 .

We have installed sockets on alternate positions. Lecture 9 – Page 33/59 Mon 9/28/2009 On the S3SB: ◮ ◮ ◮ ◮ EECS 452 – Fall 2009 . B1 is left for use by other devices. Make sure VB on MIB connects to VCC on PMod! Make connections with power OFF! For now connector A1 is “not” being used. MIB goes here ! The Spartan-3 Starter Boards has provision for lots of connections.Pmod.) A2 is reserved for connecting to DSK peripheral interface bus to the Spartan-3 Starter Board. This is the primary reason we chose it. Use socket-socket cables to connect pins. (Actually is connected to memory bus which is used by the XVGA entity. MIB and other connectors ◮ ◮ ◮ ◮ ◮ Pins on MIB connect to pins on PMod modules.

◮ ◮ ◮ ◮ ◮ ◮ IO1 IO2 IO3 IO4 V — — — — — general I/O general I/O general I/O general I/O power ground. never use any voltage other than 3. EECS 452 – Fall 2009 Lecture 9 – Page 34/59 Mon 9/28/2009 . GND — Names used on individual boards vary with the board.PMod pins PMod pin names used on the MIB. Please try very hard to connect V to the V pin on the PMod being plugged in.3 volts. Things will often work better that way.

J5 (PMod C). ◮ ◮ ◮ ◮ Four slide switch PMod goes J1 (PMod A). the switch. EECS 452 – Fall 2009 Lecture 9 – Page 35/59 Mon 9/28/2009 . A/D PMod goes J3 (PMod B). It makes life a bit simpler having some predictability. A/D and D/A PMod boards as follows.EECS 452 “standard” PMod placement Our goal is to always place. one to all. D/A PMod goes J7 (PMod D). available.

S3SB/C5510 link. S3SB/C5510 link. EECS 452 – Fall 2009 Lecture 9 – Page 36/59 Mon 9/28/2009 .Lab exercise 4 ◮ Demonstrates: ◮ ◮ ◮ ◮ ◮ ◮ ◮ ◮ ◮ interfacing the PMod DA2 D/A converter. The exercise introduces the dual-channel A/D and D/A PMod modules. simple A/D in. interfacing the PMod AD1 A/D converter. single supply level shifting. S3SB electret microphone interface. S3SB master. C5510 master. DDS using the S3SB. metastability demonstration. D/A out loop.

sync.! 16-bit data frames are used. ◮ ◮ ◮ ◮ ◮ Two chips mounted per PMod board. bottom-up design The only real design effort was implementing the bit serial interfaces for the D/A and A/D devices. Max clock rates of 30 (D/A) and 20 (A/D) MHz. Four lines: data 1. These might be considered device drivers written in VHDL. EECS 452 – Fall 2009 Lecture 9 – Page 37/59 Mon 9/28/2009 . Low level entities were created first. clock. data 2.Combined top-down. Attention was given on these would be used by higher levels. One converter per chip. Tested using test VHDL.

find the PMod pin signal assignments. EECS 452 – Fall 2009 Lecture 9 – Page 38/59 Mon 9/28/2009 . Actually. the mapping from digital input values to output voltages. the signal timings.Starting with the D/A A simple test is to run a counter and send the count values to the D/A and observe the waveform. Check the schematic and data sheet to ◮ ◮ ◮ determine the part number. to learn how to make it work. About as basic test you can do. see how the part is designed into the board. Check the D/A data manual to determine ◮ ◮ ◮ how it works.

Figure from the PMod Digilent data sheet. Operates using supply voltages in the range 2.The Digilent PMod-DA2 module Analog Outputs D1 DAC121S101 D/A Converter J2 Connector Sync.7V to 5. Uses a bit-serial interface. EECS 452 – Fall 2009 Lecture 9 – Page 39/59 Mon 9/28/2009 .5V. Clock DAC121S101 D/A Converter J1 Connector 2 D2 GND VCC The PMod-DA2 uses two National Semiconductor DAC121S101 12-bit digital-to-analog converters with rail-to-rail output. Maximum serial clock rate is 30 MHz.

20114906 EECS 452 – Fall 2009 Lecture 9 – Page 40/59 Mon 9/28/2009 . Analog output updates on 16th shift clock falling edge.The DAC121S101 D/A Max serial clock : 30 MHz Data uses offset binary. From the National Semiconductor data sheet.

The start of a serial transfer is detected by sampling sync_n using the rising edges of sclk. Use of a state machine in the D/A control logic is assumed. These are based on the timing diagram and written signal descriptions contained in the data sheet. ◮ sync_n can remain high between updates going low when a serial transfer is to start. Data bits are sampled on the falling edges of sclk. After loading the DAC register the state machine waits for the next high to low transition on sync_n ◮ ◮ ◮ ◮ EECS 452 – Fall 2009 Lecture 9 – Page 41/59 Mon 9/28/2009 . Possibly on the 16th falling edge of sclk.How to make the D/A work Here are some observations/guesses about the control of the D/A. There is a counter in the D/A that loads D/A holding register from the input shift register.

end if. ------------------------------------------------------------------------------------------------------counter <= counter+1. What happens when entering this code segment with counter containing 14? Does whatever happen or not? EECS 452 – Fall 2009 Lecture 9 – Page 42/59 Mon 9/28/2009 . if counter = 15 then whatever end if.Going from now to next if rising_edge(clk) then what shall be <= depends upon what now is.

s_run). signal counter : std_logic_vector(3 downto 0). type t_state is (s_idle. clear_goo : std_logic := ’0’. sr_b : std_logic_vector(15 downto 0). signal sr_a. da_b : in STD_LOGIC_VECTOR (11 downto 0). elsif rising_edge(go) then d_a <= da_a. pmod(2) <= sr_b(15). d_b <= da_b. clk : in STD_LOGIC). end pmod_dac0. signal goo. sclk : std_logic := ’1’.D/A driver body entity pmod_dac0 is Port ( go : in STD_LOGIC. EECS 452 – Fall 2009 Lecture 9 – Page 43/59 Mon 9/28/2009 .note go happened end if. begin pmod(0) <= sync_n. signal state : t_state := s_idle. signal d_a. process(go. clear_goo) is begin if clear_goo = ’1’ then goo <= ’0’. signal mygoo : std_logic_vector(1 downto 0). da_a : in STD_LOGIC_VECTOR (11 downto 0). s_wait.copy input values goo <= ’1’. pmod(1) <= sr_a(15). architecture Behavioral of pmod_dac0 is signal sync_n. pmod : out STD_LOGIC_VECTOR (3 downto 0). -. d_b : std_logic_vector(11 downto 0).main process goes here end Behavioral. end process. -. pmod(3) <= sclk. -.

state <= s_wait. -. sclk <= ’0’. sr_b <= sr_b(14 downto 0) & ’0’. da_b) is begin if rising_edge(clk) then sclk <= not sclk. state <= s_idle. clear_goo <= ’1’.sample go signal case state is when s_idle => sclk <= ’1’. end if. EECS 452 – Fall 2009 Lecture 9 – Page 44/59 Mon 9/28/2009 . da_a. -. end case. counter <= (others => ’0’). when s_wait => clear_goo <= ’0’. sync_n <= ’0’. sr_b <= "0000" & not d_b(11) & d_b(10 downto 0).generate clk/2 shift clock mygoo <= mygoo(0) & goo. counter <= counter+1.rising edge test sr_a <= "0000" & not d_a(11) & d_a(10 downto 0). end if.hold DA clock high if mygoo = "01" then -. end if. if counter = 15 then sync_n <= ’1’. -. when s_run => if sclk = ’0’ then sr_a <= sr_a(14 downto 0) & ’0’. end if. end process. state <= s_run.D/A driver main process process(clk.

Metastable events cannot be avoided. and a clock in a second domain that samples the event signal. Moving a signal between clock domains usually involves a level in one domain whose change signals an event. If the setup time on the register being used to latch the event is smaller than required. the register can enter a metastable state. In theory this can take forever. but it can’t decide.Initiating a conversion ◮ This entity is designed so that the go and the clk signal can exist in different clock domains. A metastable state is one where the latch knows that a decision is needed about whether or not the event occurred. However there are things that one can do to minimize the probability of a metastable state becoming a problem. ◮ ◮ ◮ ◮ EECS 452 – Fall 2009 Lecture 9 – Page 45/59 Mon 9/28/2009 .

Loop changing state only when SCLK is low. EECS 452 – Fall 2009 Lecture 9 – Page 46/59 Mon 9/28/2009 . Send sync_m and SCLK low. 25 MHz is within the the D/A 30 MHz limit. 25 MHz SCLK is generated unless explicitly held high. increment the counter. When GO is ’1’ then set four-bit counter to 0. However. Skip the low part of SCLK. ◮ ◮ ◮ ◮ Recall that the values to be updated are updated on the NEXT rising edge of the clk. if the counter is 15 then also set sync_m high and go back to idling state. Only needs to be one 50 MHz clock period long. shift data.Walk through ◮ ◮ 50 MHz clock is assumed. At the low to high transition. copy 12-bit a and b values into 16-bit shift registers with “normal” flag bits. GO pulses are assumed to be spaced at least 1 µ s apart.

D/A timing diagram êáëáåÖ=ÉÇÖÉë ëÅäâ ëóåÅ|ã ëÉêá~ä=Ç~í~ NR NQ NP NO NN NM Öç EECS 452 – Fall 2009 Lecture 9 – Page 47/59 Mon 9/28/2009 .

architecture Behavioral of rampgen is signal a_ramp. led : out STD_LOGIC_VECTOR(7 downto 0).Simple test using ramps entity rampgen is Port ( go : out STD_LOGIC. end process. ramp_b <= b_ramp. b_ramp : std_logic_vector(11 downto 0). ramp_a : out STD_LOGIC_VECTOR (11 downto 0). process(clk) is begin if rising_edge(clk) then counter <= counter+1. go <= ’0’. signal counter : std_logic_vector(5 downto 0). end if. b_ramp <= b_ramp+3. a_ramp <= a_ramp+1. ramp_b : out STD_LOGIC_VECTOR (11 downto 0). clk : in STD_LOGIC). EECS 452 – Fall 2009 Lecture 9 – Page 48/59 Mon 9/28/2009 . end Behavioral. end rampgen. begin ramp_a <= a_ramp. if counter = 0 then go <= ’1’. end if.

end process. -. led : out STD_LOGIC_VECTOR (7 downto 0). end if. clk. ramp_b => ramp_b. -. da_b => ramp_b.D/A test top entity DACtest0top is Port ( pmod_d : out STD_LOGIC_VECTOR (3 downto 0). ramp_a. ramp_b : std_logic_vector(11 downto 0).normally a big no-no! led <= ramp_b(11 downto 4). clk => clk). process(mclk) is begin if rising_edge(mclk) then dclk <= dclk+1. go : std_logic. da_a => ramp_a. dclk : std_logic_vector(3 downto 0). end Behavioral.reduce the clock when generating scope display ---clk <= dclk(3). pmod : std_logic_vector(3 downto 0). end DACtest0top. ramper : entity work.pmod_dac0 port map(go => go. mclk : in STD_LOGIC). clk => clk). ramp_a => ramp_a.rampgen port map(go => go. EECS 452 – Fall 2009 Lecture 9 – Page 49/59 Mon 9/28/2009 . dac : entity work. pmod => pmod. clk <= mclk. architecture Behavioral of DACtest0top is signal signal signal signal begin pmod_d <= pmod.

To create a DDS we need a ROM and we need to program the ROM. EECS 452 – Fall 2009 Lecture 9 – Page 50/59 Mon 9/28/2009 .Using the D/A to create a sine wave DDS Now that we have a D/A driver and know how to make a counter let’s make a sine wave direct digital synthesizer! The Xilinx CORE Generator provides modules for a sine/cosine lookup table and for a DDS. For now we will go DIY (using the DDS VHDL code we showed in the previous lecture). Some other day. We could use these.

so one need to think a bit about what happens when. Word size is independently configurable for each port. Not very difficult to work with. EECS 452 – Fall 2009 Lecture 9 – Page 51/59 Mon 9/28/2009 . Initialized using 256 bit vectors. RAM blocks are clocked. Can share a block RAM between ROM for a DDS and a delay memory used by a FIR filter.Working with block RAM Something like 24 18K bit blocks of dual port memory on the S-3/1000 boards. Divided into parity and data sections. Are initialized upon the FPGA is programmed. Use instantiation templates found in ISE. Becomes a ROM if one does not write to it.

begin AC0 <= ACC0(31 downto 24). FTV1R <= FTV1R_next. reset) begin if reset = ’1’ then elsif rising_edge(clk) then counter <= counter_next. DAC_load <= DAC_load_next. AC1 <= ACC1(31 downto 24). ACC0 <= ACC0_next. end process. end if. process(clk. EECS 452 – Fall 2009 Lecture 9 – Page 52/59 Mon 9/28/2009 . ACC1 <= ACC1_next.A simple DDS entity (1/2) Uses two processes. FTV0R <= FTV0R_next.

if FTV0_load = ’1’ then FTV0R_next <= FTV0. DAC_load_next <= ’0’. if counter = 49 then ACC0_next <= ACC0+FTV0R. end if. DAC_load_next <= ’1’. ACC1_next <= ACC1. if FTV1_load = ’1’ then FTV1R_next <= FTV1. FTV1R_next <= FTV1R. EECS 452 – Fall 2009 Lecture 9 – Page 53/59 Mon 9/28/2009 . ACC1_next <= ACC1+FTV1R.A simple DDS entity (2/2) process(FTV0_load. FTV0R_next <= FTV0R. end if. end Behavioral. else counter_next <= counter+1. end if. end process. FTV1_load) begin ACC0_next <= ACC0. counter_next <= "000000".

X"A7BEAA0BAC65AECDB141B3C1B64CB8E4BB86BE32C0E9C3AAC674C946CC21CF05". X"03240648096A0C8C0FAB12C815E218F91C0B1F1A2223252828262B1F2E1130FB". X"D1EFD4E1D7DADAD8DDDDE0E6E3F5E707EA1EED38F055F374F696F9B8FCDC0000". X"8895877C8677858484A483D7831D827781E3816480F7809F805A8028800B8001". X"7FF57FD87FA67F617F097E9C7E1D7D897CE37C297B5C7A7C79897884776B7641". X"A34DA1299F159D0F9B189931975A959393DD923790A28F1E8DAC8C4B8AFC89BF".Sine table initialization -. X"FCDCF9B8F696F374F055ED38EA1EE707E3F5E0E6DDDDDAD8D7DAD4E1D1EFCF05". Primary thing to realize is that the least significant bit is on the right and the most significant bit is on the left. X"5CB35ED760EB62F164E866CF68A66A6D6C236DC96F5E70E2725473B575047641". X"584255F5539B51334EBF4C3F49B4471C447A41CE3F173C56398C36BA33DF30FB". X"800B8028805A809F80F7816481E38277831D83D784A485848677877C889589BF". X"33DF36BA398C3C563F1741CE447A471C49B44C3F4EBF5133539B55F558425A82". X"750473B5725470E26F5E6DC96C236A6D68A666CF64E862F160EB5ED75CB35A82".Address INIT_00 => INIT_01 => INIT_02 => INIT_03 => INIT_04 => INIT_05 => INIT_06 => INIT_07 => INIT_08 => INIT_09 => INIT_0A => INIT_0B => INIT_0C => INIT_0D => INIT_0E => INIT_0F => 0 to 255 X"2E112B1F2826252822231F1A1C0B18F915E212C80FAB0C8C096A064803240000". 256 values of 16-bits. X"8AFC8C4B8DAC8F1E90A2923793DD9593975A99319B189D0F9F15A129A34DA57E". Used MATLAB to generate. X"776B788479897A7C7B5C7C297CE37D897E1D7E9C7F097F617FA67FD87FF57FFF". EECS 452 – Fall 2009 Lecture 9 – Page 54/59 Mon 9/28/2009 . X"CC21C946C674C3AAC0E9BE32BB86B8E4B64CB3C1B141AECDAC65AA0BA7BEA57E".

The Digilent PMod-AD1 module P1: CS P2: Data1 J1 Connector ADC 1 Filter P1 J2 Connector P2 P3: Data 2 P4: Clk P5: GND P6: Vcc AD1 Circuit Diagram ADC 2 P3 P4 P5 P6 Filter That was D/A. Figure from the PMod Digilent data sheet. Operates using supply voltages in the range 2.25V. EECS 452 – Fall 2009 Lecture 9 – Page 55/59 Mon 9/28/2009 .7V to 5. Now let’s take a look at the A/D PMod. The PMod-AD1 uses two National Semiconductor ADCS7476 12-bit analog-to-digital converters supporting rail-to-rail input. Uses a bit-serial interface. Maximum serial clock rate is 20 MHz.

The ADCS7476 A/D Max serial clock : 20 MHz Max sample rate: 1 MHz Data uses offset binary. From the National Semiconductor data sheet. EECS 452 – Fall 2009 Lecture 9 – Page 56/59 Mon 9/28/2009 . Input switches from track to hold on falling edge of the sync signal.

Shifting the voltage: A/D input using a single supply oO oP îá oQ oN î~ J H îç oR îë Analysis of this is included in the lab write-up. Most of today’s signal sources are voltage sources and DC coupled sources. The problem is that the ADC expects voltages from 0 to Vcc. So we need to shift the signal voltage. A common problem we’ll encounter is that our signals are “zero referenced”: it is centered on zero and swing between positive and negative voltage levels. EECS 452 – Fall 2009 Lecture 9 – Page 57/59 Mon 9/28/2009 .

main process goes here end Behavioral. ad_a : out STD_LOGIC_VECTOR (11 downto 0). ar_a. EECS 452 – Fall 2009 Lecture 9 – Page 58/59 Mon 9/28/2009 . architecture Behavioral of pmod_adc0 is signal signal signal signal signal signal goo. process(go. pmod(3) <= sclk. begin pmod(0) <= cs_n and (not goo). ad_b : out STD_LOGIC_VECTOR (11 downto 0). signal state : t_state. sclk. pmod : inout STD_LOGIC_VECTOR (3 downto 0). clear_goo) is begin if clear_goo = ’1’ then goo <= ’0’. clk : in STD_LOGIC). ad0 <= pmod(1). ad1 : std_logic. cs_n : std_logic := ’1’. -. end process. s_convert). ad1 <= pmod(2). end if. ad0.A/D driver body entity pmod_adc0 is Port ( go : in STD_LOGIC. clear_goo : std_logic := ’0’. counter : std_logic_vector(3 downto 0). type t_state is (s_idle. elsif rising_edge(go) then goo <= ’1’. ar_b : std_logic_vector(11 downto 0). mygoo : std_logic_vector(1 downto 0). end pmod_adc0.

counter <= (others => ’0’). cs_n <= ’1’. mygoo <= mygoo(0) & goo. end process. ar_b <= ar_b(10 downto 0) & ad1. clear_goo <= ’0’. ad_b <= not ar_b(10) & ar_b(9 downto 0) & ad0. if counter = 15 then ad_a <= not ar_a(10) & ar_a(9 downto 0) & ad0. end if. when s_convert => clear_goo <= ’1’. state <= s_idle. counter <= counter+1. EECS 452 – Fall 2009 Lecture 9 – Page 59/59 Mon 9/28/2009 . end if. end if. if sclk = ’1’ then ar_a <= ar_a(10 downto 0) & ad0.A/D driver main process process(clk) is begin if rising_edge(clk) then sclk <= not sclk. state <= s_convert. end if. end case. case state is when s_idle => sclk <= ’1’. if mygoo = "01" then cs_n <= ’0’.