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Contents Abst !"t 1 Int o#$"t%on 1&1 F%e'# Po ( !))!' G!te ! !* 1&+ V% te,4 FPGA 1&- V./L Int o#$"t%on + COR/IC A'(o %t0) +&1 A11'%"!t%ons - /es%(n A "0%te"t$ e 4 2%)$'!t%on es$'ts 5 .! #3! e I)1'e)ent!t%on 5&1 2*nt0es*s e1o t 5&+ P'!"e !n# Ro$te e1o t 5&- P'!"e !n# o$te# %)!(e 5&4 Po3e e1o t 6 Res$'ts !n# "on"'$s%on A11en#%, A4 V./L "o#e A11en#%, 54 V./L testben"0

FIFO only operation. Register level and functionality compatibility it! "#$%&&'( )*ebug Interface in 32-bit data bus mode) .Abst !"t UART (Universal Asyncchronous Receiver/Transmitter) 16550 Serial Controller core translates data bet een !arallel and serial inter"aces# and adds/removes start#sto! bits# and o!tionally !arity bit$ %t can be used to communicate ith other e&ternal devices usin' a serial cable and RS()( !rotocol$ This core is "ully com!atible ith industry standard *ational Semiconductors 16550+ device$ The 'oal o" this !ro.ect is to rite -erilo' code "or UART 16550# simulate the desi'n# Sythesi.e the desi'n and im!lement the desi'n on &ilin& virte&/ 0ield 1ro'rammable 2ate Array (012A)$ Also to chec3 the o!eratin' "re4uency desi'n and area consum!tion by the core$ Testbench ill be ritten to test the "unctionality o" the core$ This core can be used in System on chi! desi'ns$ System i nterface in 32-bit or 8-bit data bus modes (selectable).

imally compatible it! t!e industry standard "ational #emiconductors0 $%&&'( device) Features: • • • • #ystem interface in 32-bit or 8-bit data bus modes (selectable) FIFO only operation Register level and functionality compatibility it! "#$%&&'() *ebug Interface in 32-bit data bus mode) 1&1 F%e'#-1 o( !))!b'e (!te ! !* 012As has become more and more !re"erred "or desi'nin' a circuit# the reason "or this is clear hen loo3in' at the architectures hich "orms an 012A$ An 012A is com!osed o" semiconductor elements# allo in' "or the !ossibility to 4uic3ly recon"i'ure its "unctionality or !ro'ram# in the "ield or by a customer$ The !ro'rammer has the o!tion o" !er"ormin' a com!lete or !artial recon"i'uration$ The latter case ould allo the user to select a !art o" the !ro'ram loaded on the 012A and modi"y it at run5time# mean hile# leavin' the other !art o" the !ro'ram runnin' ithout interru!tion$ There are many ty!es o" technolo'ies and architectures that clearly di""erentiate one 012A "rom another# ho ever# a static RA6 (SRA6) based 012A is the most recent ty!e$ The 'eneral architecture o" an 012A usually consists o" a !ro'rammable lo'ic element as ell as !ro'rammable interconnections$ As e can see in 0i'$ 1# a lo'ic element# or a con"i'urable lo'ic bloc3 (C78)# is com!osed o" one loo3u! table# a re'ister# and a "ast arithmetic com!onent$ Recently# "our in!ut loo3u! tables (7UT) have become more and more !o!ular$ These 7UTs have the ca!ability o"' any "our variable based 8oolean "unctions$ %t should be noted that these con"i'urable lo'ic bloc3s !rovide combinational as ell as se4uential out!uts$ An interconnect matri& is used to connect lo'ic bloc3s and memory elements all to'ether$ There are also memory elements on an 012A that are used sim!ly to store instructions and/or data# these are 3no n as 8loc3 RA6s (8RA6s)$ 0inally# an 012A has %/9 bloc3s used "or !rimary in!ut or out!ut# to and "rom the circuit# hich are associated ith the !ins "ound at the 012A:s !eri!herals as sho n in 0i'$($ . li/e anot!er computer using a serial cable and R#232 protocol) +!is core is designed to be ma.ternal devices.niversal (sync!ronous Receiver-+ransmitter) core provides serial communication capabilities. !ic! allo communication it! modem or ot!er e.(R+ (.1& Int o#$"t%on +!e .

F%(& 14 Con6%($ !b'e 'o(%" b'o"7 8CL59 F%(& +4 FPGA ! "0%te"t$ e The usual se4uence "ollo ed hen desi'nin' a circuit on an 012A is described in this !art as ell as in "i'$ ) .1<$ The circuit desi'n is normally done usin' Com!uter Aided +esi'n (CA+) tools or im!lemented usin' a hard are descri!tion lan'ua'e such as -=+7 or -erilo'$ F%(& -4 /es%(n F'o3 6o FPGAs The tools or the im!lementation ill usually !rovide a netlist "or the desi'ned circuit$ This netlist ill aid in the ma!!in' o" the circuit to the resources available .

in' +S1 !er"ormance$ Bnhanced su!!ort "or hard are acceleration$ *e lo 5latency lin3 "rom the embedded 1o er1C core to custom hard are accelerators$ . 1o er1C? !rocessor ith the Au&iliary 1rocessor Unit (A1U) controller$ =i'hest %nte'ration (00#000 7o'ic Cells 1lus Bmbedded 0unctionality# %ncrease e""ective lo'ic ca!acity and decrease device costC embedded cores deliver 'uaranteed !er"ormance hile !reservin' lo'ic "abric "or custom "unctions$ Reduced 1o er Consum!tion Save 1 to 5 Datts !er 012A# Achieve !er"ormance 'oals hile stayin' ithin !o er bud'et$ -irte&5/ 012As o""er si'ni"icant advanta'es over com!etin' E0nm 012As$1er"ormance that beats com!etin' 012As in every !er"ormance cate'ory$ 7o 1o er Consum!tion that saves 1 to 5 Datts !er 012A$ Su!erior Si'nal %nte'rity ith F& less SS9 *oise and Crosstal3$ =i'hest 8and idth 6emory %nter"aces 6anu"actured in 1$(-# E0nm tri!le5o&ide technolo'y# -irte&5/ 012As o""er t ice the !er"ormance# t ice the density# and less than one5hal" the !o er consum!tion o" !revious5'eneration devices$ 6ore "le&ible cloc3in'$ U! to G0 inde!endent cloc3s and (0 di'ital cloc3 mana'ers$ +i""erential 'lobal cloc3in' minimi.4 FPGA >ilin& -irte&5/? 012As are ideally suited "or hi'h5!er"ormance si'nal!rocessin' tas3s traditionally serviced by an AS%C or ASS1$ They allo to create hi'h5 !er"ormance +S1 en'ines that can boost the !er"ormance o" !ro'rammable +S1 system by !er"ormin' com!lementary co5!rocessin' "unctions in di'ital communications# video/ima'in'# and other a!!lications$ The -irte&5/ 012A "amily is the ne est and most !o er"ul +S1solution$ The -irte&5/? "amily o" 012As includes three !lat"orms# each ith an o!timi.ed$ 9nce the bitstream is sent to the 012A# the resources selected "or our circuit 'et !ro'rammed ith the a!!ro!riate lo'ic and the interconnect !ro'rammin' bet een these resources is com!leted# 'eneratin' our circuit on the 012A$ 1rior to 'eneratin' our bitstream# e can control the selection o" the resources to be used by our circuit via CA+ tools$ (+5+CT is ritten in -=+7 and is im!lemented on -irte&/ 012A "rom >ilin&$ +etails o" -ire&t/ is 'iven in ne&t section$ 1&+ V% te.ed balance o" ca!abilities and cost$ %t:s a brea3throu'h in technolo'y and value$ 1er"ormance@ 500 6=.itter$ Bnhanced memory$ U! to 10 6bits 8loc3 RA6 ith built5in 0%09 control lo'ic$ 1H 2b!s Select%9? technolo'y$ *e Chi!Sync? technolo'y sim!li"ies board desi'n "or hi'h5band idth memory and other source5synchronous inter"aces$ 500 6=. >treme+S1? slice$ 0le&ible multi!ly5accumulator structure "or s3e and .on the 012A$ The actual im!lementation o" our circuit onto the 012A is done via the bitstream that 'ets 'enerated a"ter the ma!!in' to the resources is "inali. Cloc3in'# Achieve the hi'hest system s!eeds ith "le&ible# !recise cloc3 control$ 6(( 6b!sA6$5 2b!s Serial %/9# Solve your tou'hest serial %/9 challen'es$ (56 26ACS +i'ital Si'nal 1rocessin'# Create ultra5hi'h5!er"ormance +S1 systems$ 1rocessor Acceleration# 8uild hard are accelerators easily "or the /50 6=.

%nte'rated 10/100/1000 6b!s Bthernet 6AC$ U*=5veri"ied com!liance$ 6(( 6b!sI6$5 2b!s Roc3et%9? Transceivers$ 0le&ible SBR+BS broadest o!eratin' ran'e su!!orts multi5rate a!!lications$ 1$) -erilo' ith the .

+ is defined External (off-chip) connections 1ort ST>K1A+K9 #R<41(*4I R+#41(*4O *+R41(*4O 8+#41(*4I *#R41(*4I RI41(*4I *8*41(*4I 2idt! $ $ $ $ $ $ $ $ *irection Output Input Output Output Input Input Input Input *escription +!e serial output signal +!e serial input signal Re=uest +o #end *ata +erminal Ready 8lear +o #end *ata #et Ready Ring Indicator *ata 8arrier *etect .+1.*R(+54O.(#43(.(R+4.+& UART A "0%te"$ e IO 1o ts System interface signals 1ort C7J 234R#+4I 234(**R4I 234#564I 234*(+4I 234*(+4O 234254I 234#+34I 2348984I 234(8:4O 2idt! $ $ & or 3 7 32 or 8 32 or 8 $ $ $ $ *irection Input Input Input Input Input Output Input Input Input Output *escription 3loc/0s cloc/ input (sync!ronous Reset .sed for register selection #elect signal *ata input *ata output 2rite or read cycle selection #pecifies transfer cycle ( bus cycle is in progress (c/no ledge of a transfer Other internal signals 1ort I"+4O 3(. actual baud rate) It is enabled if .*4O 2idt! $ $ *irection *escription Output Interrupt output Output Optional baud rate output signal) +!e signal !ere is t!e $% .

3O"5 bus Rates (?.@) *escription ?a.3O"5 $2'' bps $$&2'' bps cloc/ .C'o"7s 8loc/s table> "ame 8l/ #ource 2I#. ?in Resolution $2&8?!@ for 3)%8%7 for 2I#.

R) Interrupt 5nable (ddress ' . additional read-only registers are available for debug purposes> "ame +ebu' 1 +ebu' ( (ddress 8 $2 2idt! 32 32 (ccess R R *escription First debug register #econd debug register .olding ' $ 2 2 3 7 & % 2idt! 8 8 8 8 8 8 8 8 8 (ccess R 2 R2 R 2 R2 2 R R *escription Receiver FIFO output +ransmit FIFO input 5nable-?as/ interrupts generated by t!e .Re(%ste s Registers list "ame Receiver 8u""er +ransmitter Register (+.(R+ Aet interrupt information 8ontrol FIFO options 8ontrol connection 8ontrols modem #tatus information ?odem #tatus Interrupt Identification FIFO 8ontrol 6ine 8ontrol Register ?odem 8ontrol 6ine #tatus ?odem #tatus In addition. t!ere are 2 8loc/ *ivisor registers t!at toget!er form one $%-bit) +!e registers can be accessed !en t!e Bt! (*6(3) bit of t!e 6ine 8ontrol Register is set to C$0) (t t!is time t!e above registers at addresses '-$ can0t be accessed) "ame +ivisor 7atch 8yte 1 (7S8) (ddress ' $ 2idt! 8 8 (ccess R2 R2 *ivisor 6atc! 3yte 2 *escription +!e 6#3 of t!e divisor latc! +!e ?#3 of t!e divisor latc! 2!en using 32-bit data bus interface.

Overrun or Framing Reading t!e 6ine errors or 3rea/ Interrupt #tatus Register FIFO trigger level reac!ed FIFO drops belo trigger level +!ere0s at least $ c!aracter Reading from t!e in t!e FIFO but no c!aracter FIFO (Receiver 3uffer !as been input to t!e FIFO Register) or read from it for t!e last 7 8!ar times) . and t!eir source and reset control) Bit 3 Bit 2 Bit 1 Priority Interrupt Type Receiver 6ine #tatus Receiver *ata available +imeout Indication Interrupt Source Interrupt Control Reset ' ' $ $ $ $ $ ' ' $st 2nd 2nd 1arity. priority.olding Register empty interrupt C'0 E disabled C$0 E enabled Receiver 6ine #tatus Interrupt C'0 E disabled C$0 E enabled ?odem #tatus Interrupt C'0 E disabled C$0 E enabled Reserved) #!ould be logic C'0) Reset Falue> ''! Interr pt I"entification Register (IIR) +!e IIR enables t!e programmer to retrieve !at is t!e current !ig!est priority pending interrupt) Bit 0 indicates t!at an interrupt is pending !en it0s logic C'0) 2!en it0s C$0 E no interrupt is pending) +!e follo ing table displays t!e list of possible interrupts along it! t!e bits t!ey enable.Interr pt Ena!le Register (IER) +!is register allo s enabling and disabling interrupt generation by t!e .(R+) 3it D 0 (ccess R2 R2 R2 R2 R2 $ 2 3 B-7 *escription Received *ata available interrupt C'0 E disabled C$0 E enabled +ransmitter .

olding 2riting to t!e +ransmitter .sed to enable FIFOs in "#$%&&'*)) #ince t!is .olding Register or reading IIR) 8+#.' ' $ 3rd +ransmitter . t!is bit is ignored) 2riting a C$0 to bit $ clears t!e Receiver FIFO and resets its logic) 3ut it doesn0t clear t!e s!ift register. RI or *8*) Reading t!e ?odem status register) Bits 4 and 5> 6ogic C'0) Bits 6 and > 6ogic C$0 for compatibility reason) Reset Falue> 8$! FIFO Control Register (FCR) +!e F8R allo s selection of t!e FIFO trigger level (t!e number of bytes in FIFO re=uired to enable t!e Received *ata (vailable interrupt)) In addition. *#R. i)e) receiving of t!e current c!aracter continues) 2riting a C$0 to bit 2 clears t!e +ransmitter FIFO and resets its logic) +!e s!ift register is not cleared. t!e FIFOs can be cleared using t!is register) 3it D 0 (ccess 2 2 2 2 2 $ 2 &-3 B-% *escription Ignored (. i)e) transmitting of t!e current c!aracter continues) Ignored *efine t!e Receiver FIFO Interrupt trigger level C''0 E $ byte C'$0 E 7 bytes C$'0 E 8 bytes C$$0 E $7 bytes Reset Falue > $$''''''b #ine Control Register (#CR) +!e line control register allo s t!e specification of t!e format of t!e async!ronous data communication used) ( bit in t!e register also allo s access to t!e *ivisor 6atc!es.(R+ only supports FIFO mode.olding Register empty ?odem #tatus +ransmitter Register 5mpty ' ' ' 7t! . !ic! define t!e baud rate) Reading from t!e register is allo ed to c!ec/ t!e current settings of t!e communication) 3it D (ccess *escription .

t!e parity bit is transmitted and c!ec/ed as logic C'0) If bit 3 is C$0 and bit 7 is C'0 t!en t!e parity bit is transmitted and c!ec/ed as C$0) 3 R2 7 R2 & R2 % 3rea/ 8ontrol bit C$0 E t!e serial out is forced into logic C'0 (brea/ state)) C'0 E brea/ is disabled B R2 *ivisor 6atc! (ccess bit) C$0 E +!e divisor latc!es can be accessed C'0 E +!e normal registers are accessed Reset Falue> ''''''$$b R2 $o"em Control Register ($CR) +!e modem control register allo s transferring control signals to a modem connected to t!e . if t!e data !as an even number of C$0 in it.(R+) 3it D 0 (ccess 2 *escription *ata +erminal Ready (*+R) signal control C'0 E *+R is C$0 C$0 E *+R is C'0 . t!en t!e parity bit is C$0) C$0 E 5ven number of C$0 is transmitted in eac! ord) #tic/ 1arity bit) C'0 E #tic/ 1arity disabled C$0 .150 R2 2 R2 #elect number of bits in eac! c!aracter C''0 E & bits C'$0 E % bits C$'0 E B bits C$$0 E 8 bits #pecify t!e number of generated stop bits C'0 E $ stop bit C$0 E $)& stop bits !en &-bit c!aracter lengt! selected and 2 bits ot!er ise "ote t!at t!e receiver al ays c!ec/s t!e first stop bit only) 1arity 5nable C'0 E "o parity C$0 E 1arity bit is generated on eac! outgoing c!aracter and is c!ec/ed on eac! incoming one) 5ven 1arity select C'0 E Odd number of C$0 is transmitted and c!ec/ed in eac! ord (data and parity combined)) In ot!er ords.If bits 3 and 7 are logic C$0.

connected Ring Indicator (RI) signal input Out2) In loopbac/ mode. connected to *ata 8arrier *etect (*8*) input) 6oopbac/ mode C'0 E normal operation C$0 E loopbac/ mode) 2!en in loopbac/ mode.$ 2 3 7 2 2 2 2 Re=uest +o #end (R+#) signal control C'0 E R+# is C$0 C$0 E R+# is C'0 Out$) In loopbac/ mode. t!e #erial Output #ignal (#+<41(*4O) is set to logic C$0) +!e signal of t!e transmitter s!ift register is internally connected to t!e input of t!e receiver s!ift register) +!e follo ing connections are made> *+R  *#R R+#  8+# Out$  RI Out2  *8* Ignored B-& 2 Reset Falue> ' #ine Stat s Register (#SR) 3it D 0 (ccess R $ R 2 R 3 R *escription *ata Ready (*R) indicator) C'0 E "o c!aracters in t!e FIFO C$0 E (t least one c!aracter !as been received and is in t!e FIFO) Overrun 5rror (O5) indicator C$0 E If t!e FIFO is full and anot!er c!aracter !as been received in t!e receiver s!ift register) If anot!er c!aracter is starting to arrive. it ill over rite t!e data in t!e s!ift register but t!e FIFO ill remain intact) +!e bit is cleared upon reading from t!e register) Aenerates Receiver 6ine #tatus interrupt) C'0 E "o overrun state 1arity 5rror (15) indicator C$0 E +!e c!aracter t!at is currently at t!e top of t!e FIFO !as been received it! parity error) +!e bit is cleared upon reading from t!e register) Aenerates Receiver 6ine #tatus interrupt) C'0 E "o parity error in t!e current c!aracter Framing 5rror (F5) indicator C$0 E +!e received c!aracter at t!e top of t!e FIFO did not !ave a valid stop bit) Of course. it mig!t be t!at all t!e follo ing data is corrupt) +!e bit is cleared upon reading from t!e . generally.

four bits also provide an indication in t!e state of one of t!e modem status lines) +!ese bits are set to C$0 !en a c!ange in corresponding line !as been detected and t!ey are reset !en t!e register is being read) 3it D 0 (ccess R R R R R R $ 2 3 7 & *escription *elta 8lear +o #end (*8+#) indicator C$0 E +!e 8+# line !as c!anged its state) *elta *ata #et Ready (**#R) indicator C$0 E +!e *#R line !as c!anged its state) +railing 5dge of Ring Indicator (+5RI) detector) +!e RI line !as c!anged its state from lo to !ig! state) *elta *ata 8arrier *etect (**8*) indicator C$0 E +!e *8* line !as c!anged its state) 8omplement of t!e 8+# input or e=uals to R+# in loopbac/ mode) 8omplement of t!e *#R input or e=uals to *+R in loopbac/ mode) . framing error or brea/ indications !ave been received and are inside t!e FIFO) +!e bit is cleared upon reading from t!e register) C'0 E Ot!er ise) $o"em Stat s Register ($SR) +!e register displays t!e current state of t!e modem control lines) (lso.(R+ aits for a valid start bit to receive ne.3it D 7 (ccess R & R % R B R *escription register) Aenerates Receiver 6ine #tatus interrupt) C'0 E "o framing error in t!e current c!aracter 3rea/ Interrupt (3I) indicator C$0 E( brea/ condition !as been reac!ed in t!e current c!aracter) +!e brea/ occurs !en t!e line is !eld in logic ' for a time of one c!aracter (start bit G data G parity G stop bit)) In t!at case. one @ero c!aracter enters t!e FIFO and t!e .t c!aracter) +!e bit is cleared upon reading from t!e register) Aenerates Receiver 6ine #tatus interrupt) C'0 E "o brea/ condition in t!e current c!aracter +ransmit FIFO is empty) C$0 E +!e transmitter FIFO is empty) Aenerates +ransmitter .olding Register 5mpty interrupt) +!e bit is cleared !en data is being been ritten to t!e transmitter FIFO) C'0 E Ot!er ise +ransmitter 5mpty indicator) C$0 E 3ot! t!e transmitter FIFO and transmitter s!ift register are empty) +!e bit is cleared !en data is being been ritten to t!e transmitter FIFO) C'0 E Ot!er ise C$0 E (t least one parity error.

(R+$%&&' device specifications) Reading from t!e does not influence core0s ba!aviour) 3it D F50 115G 1551( 23-$% 3$-27 (ccess R R R R R *escription 6ine #tatus Register value) Interrupt 5nable Register value (bits 3-')) Interrupt Identifier Register value (bits 3-')) 6ine 8ontrol Register value) ?odem #tatus Register value) %e! g ( +!is register is only available !en t!e core !as 32-bit data bus and &-bit address bus) It is read only and is provided for debugging purposes of c!ip testing as it is not part of t!e original . !ic! disables all serial I-O operations in order to ensure e. so !en setting t!e divisor. !ic! is internally accessed as a single number) 9ou s!ould t!erefore set all 2 bytes of t!e register to ensure normal operation) +!e register is set to t!e default value of 0 on reset.($% .% B R R 8omplement of t!e RI input or e=uals to Out$ in loopbac/ mode) 8omplement of t!e *8* input or e=uals to Out2 in loopbac/ mode) %i&isor #atches +!e divisor latc!es can be accessed by setting t!e Bt! bit of 68R to C$0) 9ou s!ould restore t!is bit to C'0 after setting t!e divisor latc!es in order to restore access to t!e ot!er registers t!at occupy t!e same addresses) +!e 2 bytes form one $%-bit register. desired baud rate)) +!e internal counter starts to or/ !en t!e 6#3 of *6 is ritten. rite t!e ?#3 first and t!e 6#3 last) %e! g ' +!is register is only available !en t!e core !as 32-bit data bus and &-bit address bus) It is read only and is provided for debugging purposes of c!ip testing as it is not part of t!e original .plicit setup of t!e register in t!e soft are) +!e value set s!ould be e=ual to (system cloc/ speed) .(R+$%&&' device specifications) Reading from t!e does not influence core0s ba!aviour) 3it D (50 F5) 115G 1651( (ccess R R R R *escription +ransmitter F#? state "umber of c!aracters in +ransmitter FIFO (tf4count) Receiver F#? state "umber of c!aracters in Receiver FIFO (rf4count) .

$8-$B 23-$H 3$-27 R R R ?odem 8ontrol Register value (bits 7-') FIFO 8ontrol Register value (bits B-%) Reserved) Returned value is ') .


3O"5 I#564IJ signal to properly receive and return 8-bit data on 32-bit data bus) +!e 8-bit version mig!t !ave problems in various 2I#.#42I*+. as it serves no purpose) +!is core can operate in 8-bit data bus mode or in 32-bit bus mode.and 8-bits data bus modes is performed by defining *(+(43. default mode) !ic! is no t!e +!e 32-bit mode is fully 2I#. depending on t!e register address) (lso.-& O1e !t%on +!is . perform t!e follo ing> • #et t!e 6ine 8ontrol Register to t!e desired line control parameters) #et bit B to C$0 to allo access to t!e *ivisor 6atc!es) • #et t!e *ivisor 6atc!es. $ stop bit) • (ll interrupts are disabled in t!e Interrupt 5nable Register) For proper operation.3O"5 compatible and it uses t!e 2I#.(R+ c!ip it! t!e main e.ception being t!at only t!e FIFO mode is supported) +!e scratc! register is removed.48 in uart4defines)v. ?#3 first. no parity. uart4top)v or on t!e compiler-synt!esi@er tool command line) Initiali)ation .pon reset t!e core performs t!e follo ing tas/s> • • • • +!e receiver and transmitter FIFOs are cleared) +!e receiver and transmitter s!ift registers are cleared +!e *ivisor 6atc! register is set to ') +!e 6ine 8ontrol Register is set to communication of 8 bits of data.t) • #et bit B of 68R to C'0 to disable access to *ivisor 6atc!es) (t t!is time t!e transmission engine starts or/ing and data can be sent and received) . in t!e 32-bit data bus mode a debug interface is present in t!e system) +!is interface !as 2 32-bit registers t!at can be read to provide non-intrusive loo/ into t!e core0s registers and ot!er internal values of importance) +!e selection bet een 32. 6#3 ne.pect data on different bytes of t!e 7-byte ord. t!e I(*R4IJ is & and not 3 bits ide) In addition.3O"5 implementations because a 32-bit master reading from 8-bit bus can e.(R+ core is very similar in operation to t!e standard $%&&' . in 32-bit data bus mode.

t!e communication baud rate) #ince t!e protocol is async!ronous and t!e sampling of t!e bits is performed in t!e perceived middle of t!e bit time.• #et t!e FIFO trigger level) Aenerally. optionally. modem control signals. anot!er si. so setting it to $7 bytes is recommended if t!e system responds fast enoug!) • 5nable desired interrupts by setting appropriate bits in t!e Interrupt 5nable register) Remember t!at (Input 8loc/ #peed)-(*ivisor 6atc! value) K $% . !ic! can ot!er ise be implemented using general purpose I-Os on t!e c!ip) +!e bloc/ diagram of t!e core is on t!e follo ing page) . yet no suc! assumption s!ould be made !en calculating t!e *ivisor 6atc! values) +!e core implements t!e 2I#"3O"5 #o8 bus interface for communication it! t!e system) It !as an 8-bit data bus for compatibility reason) +!e core re=uires one interrupt) It re=uires 2 pads in t!e c!ip (serial in and serial out) and. !ig!er trigger level values produce less interrupt to t!e system. it is !ig!ly immune to small differences in t!e cloc/s of t!e sending and receiving sides.

+ivisor 7atch Re'isters 8aud 2enerator 7o'ic 7ine Status Re'ister D%S=89*B Si'nals 7ine Contrrol Re'ister Receiver 7o'ic Receiver 0%09 Receiver Shi"t Re'ister SR>K% D%S=89*B bus %nter"ace 0%09 Contrrol Re'ister Transmitter 7o'ic Trasmitter 0%09 Trasmitter Shi"t Re'ister ST>K9 %nterru!t %+ Re'ister %nterru!t 7o'ic %nterru!t Bnable Re'ister %*TK9 RTSK9 6odem Sattus Re'ister 6odem Si'nals 7o'ic 6odem control re'ister CTSK% +TRK9 +SRK% +C+K% R%K% .


-& 2%)$'!t%ons4 .


5& Res$'ts !n# Con"'$s%ons .

A4 V.A11en#%./L "o#e .