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Code No: RR410506

RR
(COMPUTER SCIENCE ENGINEERING)

SET-1

B.Tech IV Year I Semester Examinations, December-2011 FAULT TOLERANT SYSTEMS Time: 3 hours Answer any five questions All questions carry equal marks --Max. Marks: 80

1. Explain different faults with an examples.

[16]

2. Explain Random, transition and signature Analysis testing methods with examples. [16] 3. Explain with an example Practical fault tolerant system. [16]

4. Explain self Checking sequential machine and partially self checking circuit. [16] 5. Explain fail safe design of a sequential circuit using partition Theory and Berger codes. [16] 6. Explain totally self-check PLA design. 7. Explain testability, controllability and observability. [16] [16]

8. Explain Scan Path technique and level sensitive scan design, built in self test. [16]

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Tech IV Year I Semester Examinations. Explain totally self-check PLA design. Explain Random. [16] 3. 5. Explain testability. [16] ****** . Explain with an example Practical fault tolerant system. built in self test. [16] 7.Code No: RR410506 RR (COMPUTER SCIENCE ENGINEERING) SET-2 B. transition and signature Analysis testing methods with examples. Marks: 80 1. [16] [16] 6. [16] 2. Explain fail safe design of a sequential circuit using partition Theory and Berger codes. [16] 4. [16] 8. December-2011 FAULT TOLERANT SYSTEMS Time: 3 hours Answer any five questions All questions carry equal marks --Max. Explain Scan Path technique and level sensitive scan design. controllability and observability. Explain self Checking sequential machine and partially self checking circuit. Explain different faults with an examples.

Explain totally self-check PLA design. [16] [16] 4. [16] ****** .Tech IV Year I Semester Examinations. Marks: 80 1. Explain Random. Explain different faults with an examples. Explain testability. [16] 2. transition and signature Analysis testing methods with examples. December-2011 FAULT TOLERANT SYSTEMS Time: 3 hours Answer any five questions All questions carry equal marks --Max. built in self test. [16] 7. [16] 5.Code No: RR410506 RR (COMPUTER SCIENCE ENGINEERING) SET-3 B. Explain self Checking sequential machine and partially self checking circuit. 3. [16] 6. Explain Scan Path technique and level sensitive scan design. controllability and observability. Explain fail safe design of a sequential circuit using partition Theory and Berger codes. [16] 8. Explain with an example Practical fault tolerant system.

transition and signature Analysis testing methods with examples.Code No: RR410506 RR (COMPUTER SCIENCE ENGINEERING) SET-4 B. [16] 8. Explain Scan Path technique and level sensitive scan design. Explain testability. controllability and observability. [16] 7. [16] 5. [16] 4. Explain self Checking sequential machine and partially self checking circuit. [16] 2. December-2011 FAULT TOLERANT SYSTEMS Time: 3 hours Answer any five questions All questions carry equal marks --Max. [16] ****** . [16] 3. Explain with an example Practical fault tolerant system. Explain Random. Marks: 80 1. Explain different faults with an examples. [16] 6. Explain fail safe design of a sequential circuit using partition Theory and Berger codes. built in self test. Explain totally self-check PLA design.Tech IV Year I Semester Examinations.