You are on page 1of 8

ARTICLE IN PRESS

Microelectronics Journal 41 (2010) 403410

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Variable-amplitude dither-based digital background calibration algorithm for linear and high-order nonlinear error in pipelined ADCs
Shuo Yang a, Jun Cheng b,n, Pei Wang b
a b

Xian Jiaotong University, Mailbox 1723, no.28, Xianning West Road, Xian, Shaanxi 710049, PR China Xian Jiaotong University, School of Electronics and Information Engineering, no. 28, Xianning West Road, Xian, Shaanxi 710049, PR China

a r t i c l e in fo
Article history: Received 9 October 2009 Received in revised form 12 April 2010 Accepted 26 April 2010 Available online 13 May 2010 Keywords: Pipelined ADC Digital background calibration Variable-amplitude Dither-based Correlation-based

abstract
Dither-based digital background calibration algorithm has been used to eliminate the inuence of linear and nonlinear errors in pipelined ADC. However, this algorithm suffers from two disadvantages: too slow convergent speed and deduction of transmitting signals amplitude in analog circuits due to dither injection. Input-dependent variable-amplitude dither-based algorithm is used in this paper to conquer both disadvantages. This proposed algorithm is implemented in a 14-bit, 100 MHz sample-rate pipelined ADC. The simulation results illustrate signal-to-noise and distortion (SINAD) of 76.56 dB after calibration of linear and nonlinear errors. Furthermore, the convergent speed is improved much more. & 2010 Elsevier Ltd. All rights reserved.

1. Introduction Pipelined ADC (pADC) is mainstream architecture of highspeed and high-resolution ADC. The linear error due to capacitor mismatch, nite gain of op-amp, comparator offset and nonlinear error caused by op-amps nonlinearity of every stage are both critical factors to restrict resolution of pADCs. By improving analog circuit design, the effective number of bit (ENOB) only reaches 810 bit. Fortunately, after introducing digital background calibration algorithm, it rises to more than 12 bit. Furthermore, comparing to its analog counterpart, digital circuit obtains higher speed and less power cost. Therefore with assist of advanced backend digital calibration, the pADCs manage to be higher in speed and resolution while lower in power-consuming. Till now, background calibration algorithms of linear error are mature enough to assist pADCs reach resolution of 12 bit [13]. However, after linear error being calibrated, odd-order nonlinear error in differential circuit becomes major factor that affects further development of resolution [4]. Nowadays, there are three major kinds of background algorithms to calibrate linear and nonlinear errors simultaneously: the rst scheme introduces a high-resolution but low-speed ADC to calibrate errors of highspeed ADC[5,6]; the second scheme is known as statistic-based algorithm [4] and the third is dither-based (or correlation-based)

Corresponding author. Tel.: + 86 13152019368. E-mail addresses: nelsyang84@gmail.com (S. Yang), jcheng@mail.xjtu.edu.cn (J. Cheng). 0026-2692/$ - see front matter & 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2010.04.012

calibration algorithm [79]. The rst scheme needs an extra ADC which denitely cost more power and area. Statistic-based algorithm suffers from unacceptably long converge time and large memory for statistic data in digital circuit. Dither-based algorithm, also called as correlation-based algorithm, is widely studied and applied. The earliest technology that improves dither-based algorithm to calibrate nonlinear errors is reported in [7]. Single dither with Pseudo-Noise sequence (PN sequence) is injected to stage which needs calibration. Due to correlation character of PN sequence, all linear and nonlinear errors in analog circuit are abstracted and calibrated in digital circuit. However, in traditional pADCs architecture, injection of dither with comparators offset makes residue voltage exceed input range of next stage, introducing miss code to nal digital code. Therefore, less-than-full-scale architecture of pipeline stage is reported to ensure certain redundancy for dither and offset, which leads reduction of analog transmitting signals amplitude and worsens signal-to-noise ratio (SNR). Furthermore, this single dither method requires unpleasantly complex backend digital calibrating circuit. Later, single dither is replaced by multiple dithers to effectively reduce complexity of digital circuit [8,9]. However, the amplitude of every dither must be reduced to avoid missing code, which unexpectedly slows down convergent speed of algorithm. These multiple-dither-based calibration costs several seconds, even several minutes to converge[8,9], which severely limits its practical application. To sum up, resent dither-based algorithm improves complexity of backend digital circuit by compromising convergent speed.

ARTICLE IN PRESS
404 S. Yang et al. / Microelectronics Journal 41 (2010) 403410

What is more, the SNR of transmitting signal in analog circuit is harmed by traditional less-than-full-scale architecture. To conquer this conicting issues, an input-signal-dependent variable-amplitude multiple-dither-based algorithm is introduced in this paper to calibrate linear and 3rd-order nonlinear errors. The proposed algorithm ensures to inject multiple dithers with higher average amplitude, in the other words, higher convergent speed. A similar scheme is used in 1.5bit/stage pipelined ADC with single dither to calibrate error in reference voltage [10]. What is more, an advanced less-than-full-scale architecture, Quasi-2bit/ stage architecture, is raised for cooperating with this new calibration algorithm to improve SND of analog transmitting signal. In Section 2 of this paper, how linear and nonlinear errors inuence resolution of pADCs is analyzed. Primary ideal of ditherbased algorithm and relationship between dithers amplitude and convergent speed is also introduced. In Section 3, quasi-2bit/stage pADCs stage architecture and input-signal-dependent variableamplitude dither-based algorithm which is used for calibrating all linear and nonlinear errors are proposed. Through theoretical deduction, improving performance of this proposed calibration method is illustrated. A system simulation platform accomplished by Simulink/Modelsim is introduced in Section 4. And simulation result is also given out to validate effectiveness of proposed algorithm. Conclusion is delivered in Section 5.

input, while Fi is effective input gain [7]. gi and Di are real interstage gain and output code, respectively. In ideal condition, open-loop gain, A, is innite. The parasitic capacitor, Cp, equals to 0. Cin/Cf N means capacitors perfectly matches. So, there is gi gi_ideal N in Eq. (1). However, when nonideal factors are taken into consideration, the gi gi_real a N conveys that nite open-loop gain, parasitic parameter and capacitor mismatch are all included in inter-stage gain error, which is so-called linear error. Nonlinear errors are caused by nonlinearity of operational amplier in MDAC. In differential analog circuit, while even-order nonlinearities are restricted, the odd-order harmonic components become major inuential factor [4]. However the harmonic components are ignored in low-resolution ADCs since it is much smaller than quantitative errors. Unfortunately, with development of ADCs resolution, the impact of these odd-order components become obvious and sharp [8]. At present, in 1416 bit pipelined ADCs, 3rd-order components are necessary to be taken into account. As the result, transfer function becomes Eq. (2) where a3_i refers to the 3rd-order nonlinear error coefcient in stage_i. vi 1 gi vin_i Di a3_i vin_i Di 3 2.2. Multiple-dither-based digital background algorithm One principal of background dither-based calibration algorithm is to allocate an emulation block in backend digit circuit, which executes some e, also called emulation calculation,eto calibrate errors. Considering both linear and 3rd-order nonlinear error, the emulation calculation can be expressed by Eq. (3). 3 D_codei_emul D_codei 1 A3i D_codei 1 3 =Gi_real Di where Gi_real and A3i are emulation parameters, referring to linear and 3rd-order nonlinear error coefcients in analog circuit respectively. The principal about how emulation calculation eliminates inuence of analog error on nal digital code is shown as follows Substitute Eq. (2) into (3) gives Eq. (4).
h i D_codei_emul gi vin_i Di a3_i vin_i Di 3 A3i D_codei 1 3 Gi_real Di

2. Issues in current dither-based algorithm 2.1. Linear and nonlinear error in pipelined ADC Nowadays, stages of pipelined ADC usually consist of comparators (sub-ADC) and a multiply-DAC, named MDAC. Fig. 1 illustrates the ith stage (stage_i) in pipelined ADC: j1 and j2 are two non-overlapping clocks to control switches. Cin and Cf are the sample capacitor and the ip-over capacitor, respectively. They are the input capacitor of op-amp. Cp and A are input parasitic capacitor and open-loop gain of the operational amplier (op-amp). The transfer function of stage_i is given as Eq. (1) in [7]: 1=Fi vi vin_i Di 1=gi vi 1 1

4 To perform 3rd power operation on both sides of (2) and ignore higher order terms gives Eq. (5). D_codei 1 3 vi 1 3  gi 3 vin_i Di 3 Substituting Eq. (5) into (4) gives Eq. (6). D_codei_emul gi vin_i Di a3_i D_codei 1 3 =gi 3 A3i D_codei 1 3 =Gi_real Di 6 5

where vi and vi + 1 are normalized input and output voltage of stage_i (the normalized factor is Vref). vin_i is normalized effective

In emulation calculation, if these emulation parameters match real error coefcient that Gi_real gi_real , A3i a3_i =gi3 , the Eq. (6) changes into D_codei_emul vin_i, which means even when there are errors existing in the stage_i, the D_codei_emul after emulation
a3_i (.)3 Vi Vin_i Di PN_Sum *Vcal
Fig. 1. The stage_i with capacitor ip-over MDAC in pipelined ADC. Fig. 2. Diagram of transmitting model with dithers in stage_i.

ri

1/Fi

gi

Vi+1

Back-end ADC

D_codei+1

ARTICLE IN PRESS
S. Yang et al. / Microelectronics Journal 41 (2010) 403410 405

Fig. 3. Deviation value versus number of cumulative sum calculation under various amplitude of dithers.

among 7 1 and 7 3. And Vcal refers to amplitude value of dither. After dither injecting, Eqs. (2) and (5) changes into Eqs. (7) and (8), respectively. vi 1 gi vin_i Di PN_sum Vcal a3_i vin_i Di PN _sum Vcal 3 7 D_codei 1 3  gi3 vin_i Di PN _sum Vcal 3 8

In digital domain, dithers are removed in emulation calculation, Eq. (6) changes into Eq. (9).
D_codei_emul gi vin_i Di PN_sum Vcal a3_i =gi 3 A3i D_codei 1 3 =Gi_real PN _sum Vcal Di

From Eq. (7), only gi is correlated with single PN sequence. Therefore, in backend digital circuit, single PN sequence (for example PN1) is used to multiply (D_codeiDi), shown as Eq. (10). D_codei Di PN1 1gi =Gi_real PN1 2 Vcal f. . .gUPN1 10

In Eq. (10), {y} includes terms that are not correlated with PN1. According to nature of PN sequence, after innite number of cumulative sum and then average calculation (represented by symbol E[.]), Eq. (11) is given out. 11 E D_codei Di PN1 Gi_real gi =Gi_real Vcal eG Vcal The error coefcient of analog circuit is abstracted in digital domain from Eq. (11). At this point, two methods were reported to reach nal emulation parameter: one is to use complex digital calculation with help of DSP to nd emulation parameter Gi_real [8]; another is to apply least mean square (LMS) iterative calculation, renewing Gi_real to approach real gi_real [7,9] as described in Eq. (12). Gi_real_new Gi_real_old mG UED_codei Di UPN1 12

Fig. 4. (a) Ideal voltage transmitting curve of less-than-full-scale architecture with 3 dithers injected and (b) Voltage transmitting curve when amplitude of dithers doubled.

calculation could represent input voltage precisely. So the issue becomes how to obtain emulation parameter in digital domain. To abstract emulation parameters, dithers are rstly injected into analog circuit to correlate these error terms which are then demodulated in digital domain. Fig. 2 shows block diagram of transmitting model with injecting dithers where D_codei + 1 refers to quantitative code of output voltage vi + 1 of stage_i through backend stages. The so-called dither is actually a product of PN_sum and Vcal. PN_sum refers to sum of 3 terms binary pseudorandom noise sequence, PN1, PN2 and PN3. So the PN_sum values

where mG is step size of LSM iteration. The closer between Gi_real and gi_real are, the smaller eG is. The iteration nishes till eG E 0. This LSM scheme is also used in this paper. Similar process is designed for obtaining 3rd-order emulation parameter, eA3. However, It is PN1 PN2 PN3 that multiply (D_codeiDi) in digital domain, which gives Eq. (13) that only one term is correlated with PN1 PN2 PN3. D_codei Di PN1 PN2 PN3 6a3_i =gi 3 A3i PN1 2 PN2 2 PN3 2 Vcal 3 f:::gUPN1 PN2 PN3 13

ARTICLE IN PRESS
406
1 0.8 0.6 0.4 0.2 Vres 0 -0.2 -0.4 -0.6 -0.8 -1 -1 -0.8 -0.6 -0.4 -0.2 0 Vin 0.2 0.4 0.6 0.8 1

S. Yang et al. / Microelectronics Journal 41 (2010) 403410

2.3. Relationship between dithers amplitude and algorithms convergent speed From theoretic deduction, Eqs. (11) and (14) could abstract error factors after innite number calculation. However, nite number of calculation is applied in real circuit implement so that uncorrelated terms cannot be eliminated completely and the calculating result deviates from its ideal value [8]. This deviation value is recorded as esum. Mathematical simulation of abstracting process is initially realized by Matlab in this paper. Fig. 3 illustrates the deviation value esum for linear error calculation versus number of cumulative sum at different amplitude value of dithers. On the one hand, the number of cumulative sum increases to reduce esum, which ensures error coefcient can be abstracted correctly. It also means single convergent iteration become longer and whole calibration process costs more time. Nevertheless, if the number of cumulative sum is not large enough, esum makes the calculating result is far from ideal value, which makes the algorithm never converge. On the other hand, to reach the certain esum, number of cumulative sum and amplitude of dither are inverse proportion, which is square inverse proportion for linear error calibration. When amplitude of dither, Vcal, increases to 9 times of its original value, the number of calculation decreases from 105 to 103 to reach the same esum value. Whats more, it becomes 6th power inverse proportion for 3rd-order nonlinear error [8], which suggests increasing amplitude of dither promises an effective and feasible scheme to accelerate convergent speed. At present, less-than-full-scale architecture is widely used to guarantee redundancy for multiple dithers. Fig. 4(a) shows an ideal voltage transfer curve of less-than-full-scale architecture described in [9]. The solid curve in Fig. 4(a) refers to original output signal without adding any dither, while the dashed curves refer to real output voltage with 3 dithers added. The normalized output range is 1  1 in traditional stage architecture, while it decreases to 0.5  0.5 (refer to original output signal) in lessthan-full-scale architecture. It leads decline of SNR in analog circuit. What is more, if doubling amplitude value of dither is committed in this traditional scheme to accelerate convergent speed, the voltage transfer curve changes into Fig. 4(b) and the real output voltage obviously exceeds input range of next stage, which lead to miss code on nal output. It means the scheme that improving convergent speed by increasing value of dithers is infeasible in traditional scheme, since the amplitude of dither are xed and increase of amplitudes requires larger redundancy in less-than-full-scale architecture which makes SNR even worse. Fortunately, these bottlenecks will both be conquered by using advanced algorithm proposed later.

Fig. 5. Residue voltage versus input voltage of quasi-2bit/stage architecture of pADCs stage.

Fig. 6. Transmitting curve by using of input-dependent variable-amplitude ditherbased algorithm in quasi-2bit/stage architecture (a) under ideal circumstances and (b) under non-ideal circumstances with linear, nonlinear errors and comparator offset.

3. Quasi-2bit/stage architecture and variable-amplitude dither-based algorithm 3.1. Quasi-2bit/stage architecture of pADCs stage This quasi-2bit/stage architecture forms between 2bit/stage and 2.5bit/stage architecture. These 3 kinds of architectures all have ideal inter-stage gain of 4. But quasi-2bit/stage architecture obtains 4 comparators to separate 5 input levels, while 2bit/stage and 2.5bit/stage ones have 3 and 6 comparators, respectively. When 4 comparators reference voltages are 7 0.2 Vref and 7 0.6 Vref, the transmitting curve is illustrated in Fig. 5. Comparing to former less-than-full-scale architecture in [8,9], this quasi-2bit/stage architecture could improve original output signal from 7 0.5 Vref to 7 0.8 Vref , enhancing SNR by 2.56 times. However, this new architecture only accommodates 7 0.2 Vref

where {y} refer to terms are not correlated by PN1 PN2 PN3. After the same innite number of cumulative sum and averaging calculation, the correlated term is emerged as shown in Eq. (14). E D_codei Di Gi_real PN1 PN2 PN3 6a3_i =gi 3 A3i Vcal 3 6eA3 Vcal 3 14

The same iteration algorithm is applied to obtain 3rd-order emulation parameter A3i.

ARTICLE IN PRESS
S. Yang et al. / Microelectronics Journal 41 (2010) 403410 407

redundancy. If traditional xed-amplitude dithers are injected, the amplitude must be much smaller so that convergent speed will be even slower. Therefore, an advanced dither injecting scheme is demanded. 3.2. Proposed background calibration algorithm This advanced variable-amplitude dither-based algorithm provides to inject multiple dithers with large average amplitude without occupying any redundancy voltage space. In the traditional dither-based algorithm, due to 4 values of PN_sum, as 7 1 and 7 3, the original output curve separates into 4 real transmitting curves in every input level after injecting 3 xedamplitude dithers. However, in input-dependent variable-amplitude dither-based algorithm, two extra sub-comparators are inserted between initially adjacent main-comparators, which are used to divide original single main-input-level into 3 sub-levels. Shown as solid curve in Fig. 6(a), in quasi-2bit/stage architecture the initial main-comparators normalized references are

0.6, 0.2, 0.2, 0.6. And two sub-comparators introduces subcomparator levels in every main-level, shown as vertical dashed lines in Fig. 6(a). In distinct sub-levels, total amplitude of dithers changes with various PN_sum values, which are illustrated in Table 1. The dashed curves in Fig. 6(a) exhibit real transmitting voltage with 3 dithers added under ideal circumstances when PN_sum equals 7 3. To verify feasibility of new algorithm, transmitting curve of non-ideal circumstances, where linear and nonlinear errors are 5% and comparators offset is 50 mV, is also simulated and depicted in this paper by Matlab. The simulation result is shown as Fig. 6 (b), which proves the real output voltage will not exceed input range of 7 Vref even with pessimistic-estimating errors. Comparing to traditional xed-amplitude dither-based algorithm [8,9], the new algorithm could raise average amplitude of dithers more than 2 times and still ensure the same redundancy of 0.2 Vref after 3 dithers injected as that of [8,9]. Since convergent speed improves with 6th power of dithers amplitude in abstracting 3rd-order nonlinear error[8], the convergent speed

Table 1 Amplitude value of dithers in every sub-level in quasi-2bit/stage architecture. Comparators level (normalized by Vref) Main levels 1  0.6 Sub-levels 1.0  0.9 0.9  0.7 0.7  0.6 0.6  0.5 0.5  0.3 0.3  0.2 0.2  0.1 0.1  + 0.1 + 0.1  + 0.2 + 0.2  + 0.3 + 0.3  + 0.5 + 0.5  + 0.6 + 0.6  + 0.7 + 0.7  + 0.9 + 0.9  + 1.0 Amplitudes of dithers under various PN_sum (normalized by Vref) PN_sum 3 0 1/10 3/10 0 1/10 3/10 0 1/10 3/10 0 1/10 3/10 0 1/10 3/10 PN_sum 1 0 1/30 1/10 0 1/30 1/10 0 1/30 1/10 0 1/30 1/10 0 1/30 1/10 PN_sum 1 1/10 1/30 0 1/10 1/30 0 1/10 1/30 0 1/10 1/30 0 1/10 1/30 0 PN_sum 3 3/10 1/10 0 3/10 1/10 0 3/10 1/10 0 3/10 1/10 0 3/10 1/10 0

0.6  0.2

0.2  + 0.2

+ 0.2  + 0.6

+ 0.6  + 1

Fig. 7. Diagram of pipelined ADC with proposed digital calibration algorithm.

ARTICLE IN PRESS
408 S. Yang et al. / Microelectronics Journal 41 (2010) 403410

of calibrating 3rd-order nonlinear error will increase more than 26 E 64 times of that in [8,9]. Whats more, it will grow to 210 E 1024 times for 5th-order errors abstracting. To sum up, the advantage of proposed algorithm is: A amplitude of original output voltage as well as SNR of the stage of pipelined ADC are improved with quasi-2bit/stage architecture; B the proposed input-dependent variable-amplitude multiple dithers provide higher amplitude of the dither while ensure the same redundancy. Generally speaking, the proposed algorithm surpasses xed-amplitude dither-based algorithm in aspects of convergent speed and SNR. On the other hand, the disadvantage is that 10 extra sub-comparators are required. However, these comparators performance, resolution and offset, only affects choice of dithers amplitude but have little inuence on nal resolution. After optimizing their design, 10 sub-comparators merely cost less than 1 mW additional power.

4. Simulation result A system simulation platform is built up by inter-simulation of Matlab/Simulink model and RTL code of Verilog HDL in this paper. The block diagram of whole pipelined ADC is illustrated in Fig. 7. Quasi-2bit/stage architecture is applied in front 3 stages

with proposed digital background calibration, while backend 7 stages are common 1.5bit/stage without calibration. A 3-bit ash ADC is added at the end to ensure a higher calculating resolution in digit circuit. First three stages are modeled with linear error of 5% and nonlinear error of 5%. Backend seven 1.5 b stages are built up with linear errors randomly chosen in the 24%. These error characters are similar as [7,9] for comparison. Digital circuit is realized by RTL code to implement backend digital function and proposed background algorithms for rst 3 stages. Cooperation of Simulink and Modelsim achieves reliable system-level verication. Calibration process is executed from 3rd-stage to 1st-stage with sample frequency of 100 MHz. Ramp-signal-input simulation is used for testing ADCs steadystate performance. Figs. 8 and 9 exhibit DNL and INL of pADC before and after the proposed calibration respectively. Assisted by proposed algorithm, DNL is between 0.35 and 0.2 LSB and INL is between 0.5 and 0.6, which fullls a 14 bit performance. Full scale sinusoidal input of 4.7851563 MHz is used for dynamic performance test. Spectrum before and after calibration are given by Fig. 10. When calibration accomplished, 3rd-order harmonic component disappears and amplitude of noise becomes weak. Steady and dynamic performance characters of before and after calibration are shown in Table 2.

Fig. 8. (a) DNL before calibration and (b) DNL after calibrating linear and nonlinear errors.

Fig. 9. (a) INL before calibration and (b) INL after calibrating linear and nonlinear errors.

ARTICLE IN PRESS
S. Yang et al. / Microelectronics Journal 41 (2010) 403410 409

Fig. 10. (a) Frequency-spectrum before calibration and (b) frequency-spectrum after calibrating linear and nonlinear errors.

Table 2 Performance of 14-bit, 100 MHz pADC before and after proposed algorithm. Before calibration DNL (LSB) INL (LSB) SINAD (dB) ENOB (bit) THD (dB) SFDR (dB) 1  0.2 40  140 42.17 6.71 46.26 48.19 After calibration 0.35  0.2 0.5  0.6 76.56 12.46 95.93 99.05

analysis in Section 3.2 of this paper. What is more, the SINAD is better than former works after calibration since the SNR of the rst three pipelined stages improves in analog circuits.

5. Conclusion Traditional multiple-dither-based digital background calibration algorithm in pADC suffers from two primary shortcomings: slow convergent speed and small amplitude of transfer voltage in analog circuit. An input-dependent variableamplitude multiple-dither-based algorithm with quasi-2bit/stage architecture is introduced in this paper to conquer these aws simultaneously and improve calibration efciency. Based on a conrmed theory that convergent speed can be accelerated by increasing amplitude of dither [8], the proposed algorithm with higher average dithers amplitude is feasible to achieve faster converge with improved resolution performance. A reliable simulation is conducted to verify the quality of proposed calibration method, which shows convergent speed is enhanced more than 60 times than former works while nal resolution is also improved. Furthermore, this proposed calibration algorithm is proved theoretically to be more benecial in future higher order nonlinear error calibration.

Method of Convergent speed testing is same as [7,9] that only rst stage is applied with errors. Fig. 11 shows signal-to-noise and distortion ratio (SINAD) versus time of simulation result and former papers [7,9]. Drawn from Fig. 11, single dither scheme is used in [7] with disastrously complex backend digital calculation, while multiple xed-amplitude dithers scheme is applied in [9] to effectively simplify calculation with slow convergent speed due to its smaller dithers amplitude. The proposed algorithm not only preserves simple backend calculation with multiple dithers but also increases amplitude of dithers to ensure effective promotion of convergent speed. Quantitative analysis shows: the proposed calibration method nishes after 3 106 samples period to promise 60 times faster than calibration period of 2 108 in [9], which is coincided with theoretic

ARTICLE IN PRESS
410 S. Yang et al. / Microelectronics Journal 41 (2010) 403410

Fig. 11. SINAD versus convergent time of pADC during converging period.

References
[1] L. Jipeng, M. Un-Ku, Background calibration techniques for multistage pipelined ADCs with digital redundancy, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 50 (2003) 531538. [2] A. Delic-Ibukic, D.M. Hummels, Continuous digital calibration of pipeline A/D converters, IEEE Transactions on Instrumentation and Measurement 55 (2006) 11751185. [3] C.R. Grace, P.J. Hurst, S.H. Lewis, A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration, IEEE Journal of Solid-State Circuits 40 (2005) 10381046. [4] B. Murmann, B.E. Boser, A 12-bit 75-MS/s pipelined ADC using open-loop residue amplication, IEEE Journal of Solid-State Circuits 38 (2003) 20402050. [5] C. Tsang, Y. Chiu, J. Vanderhaegen, S. Hoyos, C. Chen, R. Brodersen, and B. Nikolic, Background ADC calibration in digital domain, in Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE, 2008, pp. 301304.

[6] X. Wang, P.J. Hurst, and S.H. Lewis, A 12-bit 20-MS/s pipelined ADC with nested digital background calibration, in: Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003, pp. 409412. [7] J.P. Keane, P.J. Hurst, S.H. Lewis, Background interstage gain calibration technique for pipelined ADCs, IEEE Transactions on Circuits and Systems I: Regular Papers 52 (2005) 3243. [8] A. Panigada, I. Galton, Digital Background Correction of Harmonic Distortion in Pipelined ADCs, IEEE Transactions on Circuits and Systems I: Regular Papers 53 (2006) 18851895. [9] A. Meruva and B. Jalali, Digital Background Calibration of Higher Order Nonlinearities in Pipelined ADCs, in: IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, pp. 12331236. [10] S. Yun-Shiang, S. Bang-Sup, A 15-bit Linear 20-MS/s pipelined ADC digitally calibrated with signal-dependent dithering, IEEE Journal of Solid-State Circuits 43 (2008) 342350.