Design Considerations for Asymmetric Half-Bridge (AHB) Converters

Hangseok Choi

www.fairchildsemi.com

Agenda

Introduction
Idealized Operation of AHB Converters Steady state Analysis of an Actual AHB Converter Design Procedure with Example Design Tips Experimental Verification Conclusion
2

Introduction: Why Soft-Switching?

Ever increasing demand for higher power densities in power converters has forced engineers to increase switching frequencies. Switching Losses, however, have hindered high frequency operation
Overlap of voltage and current Capacitive loss Reverse recovery loss

Soft-switching technique can reduce switching losses

Basic Features of an AHB Converter

Inherent zero voltage switching (ZVS) capability since parasitic components can be incorporated to achieve ZVS High efficiency and low EMI through ZVS Simple topology and simple control MOSFET voltage is clamped to the input voltage Fixed switching frequency operation Smaller inductor can be used compared to forward converter topologies (less than half)

Idealized Operation of an AHB Converter Basic Concept

What if an asymmetric square wave is introduced to the transformer?

Transformer will be saturated

What if an asymmetric square wave is introduced to the transformer in series with a DC blocking capacitor?
Not saturated thanks to the voltage of blocking capacitor
+ VCB + Vd 0 + CB V p 1:1
5

+ Vp -

Same area 0
VCB

Idealized Operation of an AHB Converter Voltage Gain

Io + Vo

Ip
Q2
Vin

+ CB + Lm Vd Vp - VCB +
IM

+ Vrec
n:1

ILO

1-D Q1 D Vd Vp Vin
Vin-VCB VCB

Vrec Vo

(Vin VCB ) D = VCB (1 D ) (Vin VCB )

VCB = Vin D Vo 2 D (1 D ) = Vin n

D (1 D ) + VCB = Vo n n
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Idealized Operation of an AHB Converter Magnetizing Current

Ip
Q2
Vin

+ CB Vd Vp -

+ Lm

+ Vrec

ILO + Vo

Io

1-D
IM

Q1 D Vd Vin

- VCB +

n:1

Vp
VCB

Vrec Vo

In steady state, the mean value of the transformer magnetizing current, IM.avg is obtained from the condition for zero net current through the DC blocking capacitor (CB) as

( I M .avg + I M .avg

IO I ) D = ( I M .avg + O )(1 D) n n IO = (1 2 D) n
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Steady State Analysis of an AHB Converter Effect of Series Inductor

Ideal model without series inductance Ip is in phase with Vp Duty loss is not observed in Vrec
Vi n

+ VCB + Vd + CB V p -

Ip + Vrec n:1 + Vo

VCB

Vp Vin D Ip

0 Vrec Vo 0 0

Actual model with series inductance Series inductor causes Ip to lag Vp Duty loss is observed in Vrec
Vp Vin Ip D
Vin

+ VCB + Vd + CB V p Lr

Ip + Vrec n:1 + Vo

VCB

0 Vrec Vo 0 0

Steady State Analysis of an AHB Converter Basic Structure

Ip 1-D Q2 Vin Ids2
+ Vd + Llkp Vpr Im CB VCB Lm

n:1
+ Vrec -

ILO

Io

+ VO

C2 -

Ro -

D Q1 Ids1 C1

Energy transfer network

Rectifier network

Square wave generator

Square wave generator produces a square wave voltage (Vd) by driving switches Q1 and Q2 complementarily Energy transfer network removes the DC offset of the square wave voltage (Vd) using the DC blocking capacitor (CB) transfers the pure AC square wave voltage to the secondary side through the transformer Causes Ip to lag Vpr to provide ZVS condition for Q1 and Q2 Rectifier network produces a DC voltage by rectifying the AC voltage with rectifier diodes and a low-pass LC filter
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Steady State Analysis of an AHB Converter Basic assumptions for steady state analysis:
The dead time is negligible since it is very small compared to the switching cycle The leakage inductance is much smaller than the magnetizing inductance The DC blocking capacitor CB is large enough to neglect the voltage ripple across CB The output filter inductor operates in continuous conduction mode All circuit elements are ideal and lossless The duty cycle for lower MOSFET, D, is less than 50% The capacitors C1 and C2 include not only the internal output capacitance of the MOSFETs, but also the external parasitic capacitance
10

Steady State Analysis of an AHB Converter Mode I

The lower switch Q1 is conducting and a voltage of (Vin-VCB) is applied to the transformer primary side (Vpr) The transformer primary side current (Ip) is the sum of the output inductor current referred to as the primary side (ILO/n) and magnetizing current (IM)

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Steady State Analysis of an AHB Converter Mode II

The lower switch Q1 is turned off at t1 and the primary side current, Ip charges C1 and discharges C2 This mode continues until the primary side voltage drops to zero (in order words, until C2 is discharged to VCB) at t2

12

Steady State Analysis of an AHB Converter Mode III

At t2, the transformer primary side and secondary side voltages become zero and the secondary side is decoupled from the primary side Then, the output inductor current, ILO begins to freewheel in the secondary side through the rectifiers and C2 continues to be discharged

13

Steady State Analysis of an AHB Converter Mode IV

The body diode of Q2 is conducting and the voltage across the switch Q2 is clamped at zero; By turning on Q2 while the body diode is conducting, zero voltage switching (ZVS) is achieved. A voltage of -VCB is applied across the leakage inductance and the primary side current (Ip) decreases During this mode, energy is not transferred to the secondary side (duty losses)

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Steady State Analysis of an AHB Converter Mode V

The upper switch Q2 is conducting and VCB is applied to the transformer primary side (Vpr) The transformer primary side current (Ip) is the sum of output inductor current referred to as the primary side (-ILO/n) and the magnetizing current (IM)

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Steady State Analysis of an AHB Converter Mode VI

The upper switch Q2 is turned off at t5 and the primary side current Ip charges C2 and discharges C1 This mode continues until the primary side voltage becomes zero (in other words, until C1 is discharged to Vin-VCB) at t6

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Steady State Analysis of an AHB Converter Mode VII

At t6, the transformer primary side and secondary side voltages become zero and the secondary side is decoupled from the primary side Then, the output inductor current, ILO begins to freewheel in the secondary side and C1 continues to be discharged

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Steady State Analysis of an AHB Converter Mode VIII

The body diode of Q1 is conducting and the voltage across the switch Q1 is clamped at zero voltage. By turning on Q1 while the body diode is conducting, zero voltage switching (ZVS) is achieved. During this mode, a voltage of (Vin-VCB) is applied across the leakage inductance and the primary side current (Ip) increases During this mode, energy is not transferred to the secondary side (duty losses)
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Steady State Analysis of an AHB Converter ZVS Condition

D 1-D Vgs2 Vgs1

ZVS turn-on condition for Q2:

Vgs1

Llk [ I p (t2 )] > (C1 + C2 )[ DVin ]

2

Vds1 Vds2
Vin

Vin

I V (1 D ) DTS I p (t2 ) = o + I M .avg + in n 2 Lm

ZVS turn-on condition for Q1:

Vpr

Vin-VCB

VCB

Llk [ I p (t6 )]2 > (C1 + C2 )[(1 D )Vin ]2 I p (t6 ) = Io V (1 D ) DTS + I M .avg in n 2 Lm
IP

Vgs1

Vgs2

Vgs2

Vgs1

Vpr
Vin-VCB

VCB

Vds2
Vin-VCB VCB VCB t1 t2 t3

Vds1
Vin-VCB t5 t6 t7

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mode II and III

mode VI and VII

Steady State Analysis of an Actual AHB Converter

What happens as duty cycle approaches 50%? Voltage stresses of the rectifier diodes are balanced

VD1 =

Vin VCB Vin (1 D ) = n n

VD 2 =

VCB Vin D = n n

Current stresses of the rectifier diodes are balanced Current stresses of the primary side MOSFETs are unbalanced Magnetizing current DC offset decreases

I M .avg =

Io (1 2 D) n

20

10

Steady State Analysis of an Actual AHB Converter

What happens as duty cycle decreases from 50%? Voltage stresses of the rectifier diode are unbalanced

VD1 = VD 2 =

Vin VCB Vin (1 D ) = n n VCB Vin D = n n

Current stresses of the rectifier diodes are unbalanced Current stresses of the primary side MOSFETs are unbalanced Magnetizing current DC offset increases

I M .avg =

Io (1 2 D) n

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Design Procedure with Example

Application Switching frequency Input voltage Rated output power Output voltage (Rated current) Holdup time DC link capacitor

LCD TV

fs=100kHz

400Vdc

192W

24V-8A

20ms

330uF

[STEP-1] Define the system specifications Estimated efficiency (Eff) =92% Input voltage range: hold up time should be considered for minimum input voltage

Pin =

Po 192 = = 209W E ff 0.92

Vin max = 400V

Vin min = VO. PFC 2 2 PinTHU 2 209 20 103 = 4002 = 367V Cin 330 106

22

11

Design Procedure with Example

[STEP-2] Determine the transformer turns ratio (n=Np/NS1, NS1=NS2)
It is typical to set duty cycle losses as 5~10%
DLoss = DL1 + DL 2 16 Pin Llk = 0.09 (Vin max ) 2 TS

Llk =

DLoss (Vin max ) 2 TS 0.09 4002 10 106 = = 43 H 16 Pin 16 209

Considering margin on the maximum duty cycle of the PWM controller (50%), the worst-case maximum duty cycle to calculate the transformer turns ratio is chosen as 42%.

n= =

(Vin min Dmax (1 Dmax )) 2 4(Vo + VF ) I o Llk f s Vin min Dmax (1 Dmax ) + (Vo + VF ) (Vo + VF ) (367 0.42 (1 0.42)) 2 4(24 + 1.2) 8 43 10 6 100 103 367 0.42 (1 0.42) + (24 + 1.2) (Vo + VF )

= 6.2
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Design Procedure with Example

[STEP-3] Calculate the nominal duty cycle ratio for maximum input voltage and full load condition
2 2 I L Vo + VF = Vin D(1 D)( ) ( ) 2 o lk n n TS
1 1 4[ Dnom = n(Vo + VF ) 2 I o Llk + ] 2Vin max nVin maxTS 2 1 1 4[ = 6.2 25.2 2 8 43 106 + ] 2 400 6.2 400 10 106 = 0.34 2

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12

Design Procedure with Example

[STEP-4] Output Inductor design Vin (1 D) Vo VF ) 2 I O Llk n ] I L = [ DTS Lo n Vin (1 D) ( Setting 20% of output current as current ripple,
( Lo = ( = Vin (1 D) Vo VF ) 2 IO Llk n [ DTS ] I L n Vin (1 D ) 400 (1 0.34) 25.2) 2 8 43 10 6 6.2 [0.34 10 106 ] = 32.3 H 8 0.2 6.2 400 (1 0.34)

I L pk = I o +

I L 8.8 A 2

25

Design Procedure with Example

[STEP-5] Determine the magnetizing inductance considering ZVS condition for maximum input voltage condition (Coss=150pF) To guarantee ZVS from full load to 20% load
1 1 4[ D@ 20% =
Llk [
6 n(Vo + VF ) 2 I o Llk + ] 1 1 4[ 6.2 25.2 + 2 (8 0.2) 43 10 ] max max 6 2Vin nVin TS 2 400 6.2 400 10 10 = = 0.28 2 2

Io V (1 D) DTS 2 < I M > + in ] > 2Coss [(1 D)Vin ]2 n 2 Lm Vin max (1 D) DTS 2Coss I 2[ (1 D)Vin o 2 D ] Llk n = 400 (1 0.28) 0.28 10 106 2 150 1012 8 0.2 2[ (1 0.28) 400 2 0.28] 43 10 6 6.2 = 654 H

Lm <

determine Lm=630H

26

13

Design Procedure with Example

[STEP-6] Design the transformer
I M . pk = Vin max D (1 D )TS I o 8 + (1 2 D) = (1 2 0) = 1.29 A 2 Lm n 6.2

Magnetizing current can reach pulse-by-pulse current limit during the transient. Thus, Bmax=0.15T is used to guarantee non-saturation of the transformer during transient (EER3542, Ae=109mm2).
N p min = Lm I M max 630 106 1.29 = = 49.7turns Ae Bmax 109 106 0.15

Then, Np=50 turns and Ns=8 turns The maximum flux density in the worst case scenario will be checked in STEP-8 after the current limit level is determined.
Pin Inductance Leakage 18 18 Spec. 630H 5% 45H 10% Test Condictions 100kHz, 1V Short one of the secondary windings
27

Design Procedure with Example

[STEP-7] DC blocking capacitor selection
Voltage ripple of the DC blocking capacitor should be 20~30V (10~20% of VCB) Too large a capacitor results in slow dynamic response
VCB
1 CB
DTS

1 CB
p

DTS

i dt = C
p 0

1 I o Io [ + (1 2 D )] n B n

i dt = C
0

1 Io I o [ + (1 2 Dnom )] < 30V n B n

1 I o Io [ + (1 2 Dnom )]DnomTS 30V n n 1 8 8 CB > [ + (1 2 0.34)] 0.34 10 106 = 193nF 30V 6.2 6.2 CB >

: Select CB=220nF

Voltage rating: more than 400V Current rating: 1.27A

I p rms = ( I P 0 2 + I P 0 I P 3 + I P32 ) (I 2 + I P 4 I P7 + I P7 2 ) D + P4 (1 D) 3 3

28

14

Design Procedure with Example

[STEP-8] Current sensing resistor selection
I p pk = = Io V D (1 Dnom )TS (2 2 Dnom ) + in nom n 2 Lm 8 400 0.34 (1 0.34) 10 106 = 2.41A (2 2 0.34) + 6.2 2 630 106

Since Vth=0.6V, Select Rsense=0.2 ohms Then, the pulse-by-pulse current limit =3A

The transformer maximum flux density in the worst case scenario is

Bmax worst =

Lm I LIM 630 106 3 = = 0.35T min Ae N p 109 106 50

29

Design Procedure with Example

[STEP-9] Choose the rectifier diode

VD1 = Vin D

2 n

Considering the worst case of D=50%, VD1 = 400 0.5

2 = 64V 6.2
2 = 128V 6.2

VD 2 = Vin (1 D)

2 n

Considering the worst case of D=0%,

VD 2 = 400 1

Considering the voltage spike, 100V and 200V diodes are selected for D1 and D2, respectively
30

15

Design Tips
A. Unbalanced secondary winding approach (center tap winding)
I LO NS1 Np

Ids1 IP
D < 0.5

Ids1
NS 2 Np

N S1 > N S 2

I LO

Voltage stress of the diode is not changed

Vo + VF = Vin D (1 D )( NS1 + NS 2 N + N S 2 2 I o LLK ) ( S1 ) NP NP TS

The magnetizing current DC offset for some operating point can be reduced using unbalanced turns
I M .avg = I o NS 2 N (1 D) I o S1 D Np Np

N N VD1 = Vin D ( S 1 + S 2 ) Np Np N S1 NS 2 VD 2 = Vin (1 D ) ( + ) Np Np

I M .avg = 0 when D =

NS2 N S1 + N S 2

But, this increases current ripple in the output inductor Requires larger inductor

31

Design Tips
B. External Soft-start
Only with duty cycle soft-start can there be a current overshoot during startup when the leakage inductance is very small

PWM soft-start only Vgs

Vgs1 Vgs2 Vgs1 LEB+turn-off delay current limit level Vgs2

PWM + PFM soft-start

Vgs2 Vgs2 Vgs1 Vgs2 Vgs1

Vgs

current limit level

IP
di Vin (1 D ) = dt Llk

IP
di Vin (1 D ) = dt Llk

32

16

Experimental Verification

33

Experimental Verification

34

17

Experimental Verification

95 94 93 92

E ff (% )

91 90 89 88 87 86 85

25

50

75

100 Po (W)

125

150

175

200

35

Conclusion
The operation principle of an asymmetric PWM halfbridge converter has been investigated

The design procedure of an asymmetric PWM halfbridge converter has been presented

The design procedure has been verified with a 192W prototype converter

36

18

Appendix
Two switch forward Active clamp forward
Lo
S2 Lo D1 Vs S1 D2 Vo

Asymmetric Half-bridge

C Vs

Vc

Im L m Ilk Ids S1 Llk + Vds -

D1 D2

Vo

S2

Practically input voltage range Primary side MOSFET voltage

Vmax/Vmin=1.6~2.0 Clamped to the input voltage

Vmax/Vmin=1.6~2.0 Not clamped to the input voltage and usually goes up to twice that of the input voltage. Limiting function is definitely required. Usually 2~3 and 4~6 times of the output voltage for powering diode (D1) and freewheeling diode (D2), respectively ZVS is very difficult to achieve at full load condition. (Design for ZVS at full load condition is not practical) ZVS at full light condition is relatively easy Tight tolerance is not required for the resonant components (L,C)

Vmax/Vmin=1.2~1.3 Clamped to the input voltage

Secondary side rectifier voltage stress ZVS condition

Usually 2~3 to 4~6 times of the output voltage for powering (D1) and freewheeling diode (D2), respectively No soft-switching

Usually about 3 to 6 times the output voltage for powering (D1) diode and freewheeling diode (D2), respectively (for center tapped transformer) ZVS is difficult to achieve at light load condition ZVS at full load condition is relatively easy Tight tolerance is not required for the resonant components (L,C) Much smaller output inductor

Other features

37

Appendix
LLC resonant converter
Io Ro Lm Cr + VO -

Asymmetric Half-bridge

Q1

Lr

Vin
Q2

Control method Practically input voltage range Primary side MOSFET voltage Secondary side rectifier voltage stress Output capacitor current ripple ZVS condition

Variable frequency with fixed duty cycle (50%) Vmax/Vmin=1.2~1.4 Clamped to the input voltage 2 times the output voltage (for center tapped transformer) Almost twice the output current (peak-to-peak)

PWM with fixed frequency Vmax/Vmin=1.2~1.3 Clamped to the input voltage Usually about 3 to 6 times the output voltage for powering and freewheeling diodes, respectively (for center tapped transformer) Several tens % of output current (peak-to-peak)

ZVS is easily achieved from full load to no load condition using the energy in the magnetizing inductance No simple power limit capability such as pulseby-pulse current limit in PWM operation Requires tight tolerance of resonant components (L,C) Relatively large circulating current 38

ZVS is difficult to achieve at light load condition ZVS at full load condition is relatively easy Tight tolerance is not required for the resonant components (L,C)

Other features

19