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FPGA BASED BLDC MOTOR CONTROL

AN INDUSTRIAL INTERNSHIP REPORT submitted by

PREETI MISHRA (10BEE1068) S VIDHYAALAKSHMI (10BEE1075)


in partial fulfillment for the award of the degree of

BACHELOR OF TECHNOLOGY
in

ELECTRICAL AND ELECTRONICS ENGINEERING

APRIL 2013
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TABLE OF CONTENTS
CHAPTER NO. 1. 2. 3. TITLE ABSTRACT INTRODUCTION BLDC MOTOR 1.PRINCIPLE OF OPERATION 2. PROPOSED TOPOLOGY 3.SYSTEM DESCRIPTION 4.FPGA 5.PWM GENERATION 6.PROPOSED TECHNIQUE 4. 5. 6. VERILOG CODING DESIGN FLOW SIMULATION RESULT 1.MATLAB OUTPUT 2.XILINX SYSTEM GENERATOR OUTPUT 7. 8. CONCLUSION REFERENCE 17 18 19 20 5 6 7 8 9 10 11 16 PAGE NO. 3 4

ABSTRACT
Advance in Power Electronics has led to an increased interest in three-phase inverters with PWM control of ac drives. Most of the AC drives and Universal PWM inverters in use today are adapting micro-processor based digital control strategy. Field Programmable Gate Arrays (FPGA) is increasingly being used in motor control applications due to their robustness and customizability. FPGA implementation has the capability of executing several processes in parallel. Hence, the total control of the inverter together with the motor can be implemented in a single FPGA chip. The use of Pulse Width modulation (PWM) in power electronics to control high energy with maximum efficiency and power saving is not new but, interesting is to generate PWM signals using Hardware Descriptive Language (HDL) and implementing it in FPGA .FPGA implementation of PWM is selected because it has provided an economic solution & fast circuit response due to its simultaneous instead of sequential execution. In this report the FPGA based controller for BLDC motor is an experimental model implementation of Sinusoidal PWM strategy (SPWM) control scheme. The proposed control scheme can be realized and the Simulation results are verified using FPGA SPARTAN-3A from Xilinx with the help of VHDL programming algorithm of digital PWM Generator topology.

INTRODUCTION
Now-a-Days, Brushless DC (BLDC) motors are one of the electrical drives that are rapidly gaining popularity, due to their high efficiency, good dynamic response and low maintenance and are widely used in many motor applications developing high torque with good speed response. They are robust and economic. The speed of the motor is directly proportional to the applied voltage. By varying the average voltage across the windings, the speed can be altered. This is achieved by altering the duty cycle of the base PWM signal.PWM Inverters are mostly used for industrial applications because of their superior performance. The use of PWM in power electronics to control high energy with maximum efficiency and power saving is not new but, interesting is to generate PWM signals using HDL and implementing it in FPGA. The report presents the simulation of the speed control of BLDC motor, which can be done using the software XILINX with the help of VHDL programming. An FPGA based speed controller is designed for closed loop operation of the BLDC motor so that the motor runs much close to the reference speed. In a market driven by profit margins, the appliance industry is reluctant to replace the conventional motor drives with the advanced motor drives (BLDC) due to their higher cost. Hence a novel approach to control the speed of BLDC using SPWM generated using low cost Spartan-3E device, produced by Xilinx, Inc.

PRINCIPLE OPERATION OF BLDC Brushless DC Motors are a type of Synchronous motor. This means that the magnetic field generated by the stator & the rotor rotate at the same frequency. Brushless DC motors usually consist of two main parts: Stator, Rotor 1. Stator which consists of three coils each including three elements in series, an inductance, a resistance and one back electromotive force. In many motors the number of coils is replicated to have a smaller torque ripple. 2. A Rotor which consists of an even number of permanent magnets. The number of magnetic poles in the rotor also affects the step size and torque ripple of the motor. More poles give smaller steps and less torque ripple. They can be sensor equipped or sensor less. Brushless DC motors are used in a growing number of motor applications as they have many advantages: 1. They have no brushes so they require little or no maintenance. 2. They generate less acoustic and electrical noise than universal brushed DC motors. 3. They can be used in hazardous operation environments (with flammable products).

The method for energizing the motor windings in the sensor method is by six-step commutation. For three-phase BLDC motor, typically, it is driven with six-step 120 degree conducting mode. At one time instant, only two out of three phases are conducting current. For example, when phase A and phase B conduct current, phase C is floating. This conducting interval lasts 60 electrical degrees, which is called one step. A transition from one step to another different step is called commutation. So totally, There are 6 steps in one cycle. Usually, the current is commutated in such way that the current is in phase with the phase backing EMF to get the optimal control and maximum torque/ampere. The commutation time is determined by the rotor position. Since the shape of back EMF indicates the rotor position, it is possible to determine the commutation timing if the back EMF is known.

PROPOSED TOPOLOGY OF BLDC MOTOR


The standard AC power supply is converted to a DC by using a 3-phase diode bridge rectifier. A voltage source Inverter is used to convert the DC voltage to the controlled AC voltage. The output of Inverter is fed to Brushless DC motor. VHDL program is used in Xilinx software to generate the controlled PWM pulses at different duty ratio for Inverter to drive the Brushless DC Motor at different speed

3-phase AC supply

Diode Bridge Rectifier

3-phase Inverter

Brushless DC Motor

Driver Circuit

PWM pulses from FPGA

SYSTEM DESCRIPTION

A complete overview of the system can be seen in the above figure, which includes the FPGA, a three phase inverter, a Brushless DC motor, and a linear encoder attached to the motor [2]. The entire System is interfaced through a PC. PC acts a Man-Machine Interface in which the user can set the reference speed of the motor, and read the actual speed.

FUNCTIONS OF FPGA FPGAs are increasingly being used in motor control applications due to their robustness and customizability. Microcontrollers have typically been used to implement motor controls, with computation algorithms executed by software. Some of the challenges in this implementation are response time, a fixed number of PWM channels, limited communication interfaces and predetermined analog triggering. The solution is to use an FPGA. Since, the performance of the FPGA has not been fully utilized, the combination of FPGA & DSP is the conventional control scheme used for the motor control. The FPGA acts as a buffer for PWM generation unit of the DSP. The tasks taken by FPGA & DSP were divided according 7

to the functions needed in motor control.The functions taken by FPGA include- generating the PWM signals, calculating of motor rotational speed, generating the phase conversion control signals, data exchanging between FPGA & DSP and calculation of current loop where as the function taken by DSP include calculation of rotational speed loop and receiving speed instruction.

PWM GENERATION USING FPGA


PWM signals are generated from the Spartan-3A processor by writing VHDL program to control the inverter switches. The switching signal parameters namely switching frequency, the duty ratio and the number of pulses are easily controlled via VHDL programming language.

Principle of generating PWM


The principle of generating PWM waveform is shown in Fig.3.Bidirectional counter is used to generate triangular wave. The value of compare register is compared with triangular wave .If the value of compare register is less than the value of triangular wave, then PWM is 1, else PWM is 0. FPGA implementation of PWM is selected because FPGA has provided an economic solution & fast circuit response due to its simultaneous instead of sequential execution.

Proposed Technique
Sinusoidal PWM (SPWM) technique is the proposed technique used to generate the PWM signals to the VSI in this paper. SPWM is based on the comparison of a sinusoidal control signal with a triangular carrier. The switches on a single branch are turned on or off depending on whether the control signal is greater or smaller than the carrier. Working with three phase loads, the control signals must be standard three phase sine waves.

Algorithm for Generating PWM Pulses


The algorithm for generating PWM pulses by using SPWM technique is given in following steps: 1. Initializing the inputs and the outputs. i. Inputs- Clock, Frequency and Amplitude ii. Output-Pulses 2. Declaring Capturing Signals a, b, c. 3. Interrupt is given based on Capture Values. 4. Declaring the array of 256 Sine values. 5. Let xx=Carrier Signal yy=Comparing Value 6. From the Ramp signal, C, triangular wave is generated. 7. Compare Sine values with the Triangular wave 8. Pulses are generated. 9. Now set the Frequency and Amplitude of Carrier and Sine. MATLAB Code:
%generate sine and triangular wave x = 1:2000; sig1(x) = 2.5*sawtooth((20*3.14*x),0.5); sig2(x) = 2*sin(6*3.14*x); fori = 1:2000 if sig1(i)>sig2(i) %(2.5*sawtooth((20*3.14*i),0.5))>(2*sin(2*3.14*i)) y(i) = 1; else y(i) = 0; end

end p1 = plot(x,y,'r');hold on p2 = plot(x,sig1,'g');hold on p3 = plot(x,sig2,'b');hold off legend([p1,p2,p3],'output','sawtooth','sine') axis([0,2000,-3.5,3.5]); %title('SPWM Modulation'); %ylabel('Voltage (V)'); %xlabel('Time (s)');

Xilinx module :

VERILOG CODE for operating BLDC : timescale 1 ns / 10 ps modulexlclockdriver (sysclk, sysclr, sysce, clk, clr, ce, ce_logic); parameter signed [31:0] log_2_period = 1; parameter signed [31:0] period = 2; parameter signed [31:0] use_bufg = 1'b0; parameter signed [31:0] pipeline_regs = 5; inputsysclk; inputsysclr; inputsysce; outputclk; outputclr; 10

outputce; outputce_logic; parameter signed [31:0] max_pipeline_regs = 8; parameter signed [31:0] num_pipeline_regs = (max_pipeline_regs>pipeline_regs)? pipeline_regs : max_pipeline_regs; parameter signed [31:0] factor = num_pipeline_regs/period; parameter signed [31:0] rem_pipeline_regs = num_pipeline_regs - (period * factor) + 1; parameter [log_2_period-1:0] trunc_period = ~period + 1; parameter signed [31:0] period_floor = (period>2)? period : 2; parameter signed [31:0] power_of_2_counter = (trunc_period == period) ? 1 : 0; parameter signed [31:0] cnt_width = (power_of_2_counter & (log_2_period>1)) ? (log_2_period - 1) : log_2_period; parameter [cnt_width-1:0] clk_for_ce_pulse_minus1 = period_floor-2; parameter [cnt_width-1:0] clk_for_ce_pulse_minus2 = (period-3>0)? period-3 : 0; parameter [cnt_width-1:0] clk_for_ce_pulse_minus_regs = ((period-rem_pipeline_regs)>0)? (period-rem_pipeline_regs) : 0; reg [cnt_width-1:0] clk_num; regtemp_ce_vec; (* MAX_FANOUT="REDUCE" *)wire [num_pipeline_regs:0] ce_vec /* synthesis MAX_FANOUT="REDUCE" */ ; (* MAX_FANOUT="REDUCE" *)wire [num_pipeline_regs:0] ce_vec_logic /* synthesis MAX_FANOUT="REDUCE" */; wireinternal_ce; wireinternal_ce_logic; regcnt_clr; wirecnt_clr_dly; genvar index; initial begin clk_num = 'b0; end assignclk = sysclk ; assignclr = sysclr ; always @(posedgesysclk) begin : cntr_gen if (sysce == 1'b1) begin:hc if ((cnt_clr_dly == 1'b1) || (sysclr == 1'b1)) begin:u1 clk_num = {cnt_width{1'b0}}; end else begin:u2 clk_num = clk_num + 1 ; end end 11

end generate if (power_of_2_counter == 1) begin:clr_gen_p2 always @(sysclr) begin:u1 cnt_clr = sysclr; end end endgenerate generate if (power_of_2_counter == 0) begin:clr_gen always @(clk_num or sysclr) begin:u1 if ( (clk_num == clk_for_ce_pulse_minus1) | (sysclr == 1'b1) ) begin:u2 cnt_clr = 1'b1 ; end else begin:u3 cnt_clr = 1'b0 ; end end end endgenerate synth_reg_w_init #(1, 0, 'b0000, 1) clr_reg(.i(cnt_clr), .ce(sysce), .clr(sysclr), .clk(sysclk), .o(cnt_clr_dly)); generate if (period > 1) begin:pipelined_ce always @(clk_num) begin:np_ce_gen if (clk_num == clk_for_ce_pulse_minus_regs) begin temp_ce_vec = 1'b1 ; end else begin temp_ce_vec = 1'b0 ; end 12

end for(index=0; index<num_pipeline_regs; index=index+1) begin:ce_pipeline synth_reg_w_init #(1, ((((index+1)%period)>0)?0:1), 1'b0, 1) ce_reg(.i(ce_vec[index+1]), .ce(sysce), .clr(sysclr), .clk(sysclk), .o(ce_vec[index])); end for(index=0; index<num_pipeline_regs; index=index+1) begin:ce_pipeline_logic synth_reg_w_init #(1, ((((index+1)%period)>0)?0:1), 1'b0, 1) ce_reg_logic(.i(ce_vec_logic[index+1]), .ce(sysce), .clr(sysclr), .clk(sysclk), .o(ce_vec_logic[index])); end assignce_vec_logic[num_pipeline_regs] = temp_ce_vec; assignce_vec[num_pipeline_regs] = temp_ce_vec; assigninternal_ce = ce_vec[0]; assigninternal_ce_logic = ce_vec_logic[0]; end endgenerate generate if (period > 1) begin:period_greater_than_1 if (use_bufg == 1'b1) begin:use_bufg BUFG ce_bufg_inst(.I(internal_ce), .O(ce)); BUFG ce_logic_bufg_inst(.I(internal_ce_logic), .O(ce_logic)); end else begin:no_bufg assignce = internal_ce; assignce_logic = internal_ce_logic; end end endgenerate generate if (period == 1) begin:period_1 assignce = sysce; 13

assignce_logic = sysce; end endgenerate endmodule (* syn_noprune = "true" *) (* optimize_primitives = "false" *) (* dont_touch = "true" *) moduleclock_driver ( ce, clk, sysclk, sysce, sysce_clr ); inputsysclk; inputsysce; inputsysce_clr; outputce; outputclk; wire wire wire wire wire sysce_clr_x0; sysce_x0; sysclk_x0; xlclockdriver_1_ce; xlclockdriver_1_clk;

assignce = xlclockdriver_1_ce; assignclk = xlclockdriver_1_clk; assign sysclk_x0 = sysclk; assign sysce_x0 = sysce; assign sysce_clr_x0 = sysce_clr;

xlclockdriver #( .log_2_period(1), .period(1), .use_bufg(0)) xlclockdriver_1 ( .sysce(sysce_x0), .sysclk(sysclk_x0), .sysclr(sysce_clr_x0), .ce(xlclockdriver_1_ce), .clk(xlclockdriver_1_clk) ); 14

endmodule modulecounterpreeti_cw ( clk,// clock period = 10.0 ns (100.0 Mhz) ce, gateway_in1, gateway_out2 ); inputclk;// clock period = 10.0 ns (100.0 Mhz) inputce; input [7:0] gateway_in1; output [7:0] gateway_out2; wireclkNet; wire [7:0] gateway_in1_net; wire [7:0] gateway_in1_net_x0; (* syn_keep="true" *)(* keep="true" *)(* preserve_signal="true" *) wire persistentdff_inst_q/* synthesis syn_keep=1 keep=1 preserve_signal=1 */; assignclkNet = clk; assign gateway_in1_net = gateway_in1; assign gateway_out2 = gateway_in1_net_x0;

counterpreeti counterpreeti_x0 ( .gateway_in1(gateway_in1_net), .gateway_out2(gateway_in1_net_x0) ); clock_driverdefault_clock_driver_counterpreeti_cw ( .sysce(1'b1), .sysce_clr(1'b0), .sysclk(clkNet) ); xlpersistentdffpersistentdff_inst ( .clk(clkNet), .d(persistentdff_inst_q), .q(persistentdff_inst_q) ); endmodule modulexlpersistentdff ( clk, d, q 15

); inputclk; input d; output q; endmodule

The FPGA design flow comprises the following steps: 1. Design entry it should assign constraints such as timing, pin location, and area constraints, including user constraints (UCF) file. 2. Design synthesis- Synthesize the project design. 3. Design implementation- Implement the design which includes the Translate, Map, Place and Route. 4. Design verification- includes both functional verification (also known as RTL simulation) and timing verification. 5. Xilinx device programming- Create a programming BIT file program debugging or to download to target device of XILINX/SPARTAN-3A processor kit. Once the program is dump to FPGA kit, it acts as a controller and generates gate signal.

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SIMULATIONS AND EXPERIMENTAL RESULTS: 1.MATLAB OUTPUT

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Xilinx System Generator Output:

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CONCLUSION
FPGA based implementation of PWM control of brushless DC motor was carried out in simulation and real time experiment.BLDC have better speed versus torque characteristics, high dynamic response, high efficiency, long operating life, noiseless operation, higher speed ranges, rugged construction and so on. Also, torque delivered to the motor size is higher, making it useful in applications where space and weight are critical factors.

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REFERENCES: http://www.freescale.com/files/product/doc/AN1914.pdf http://ww1.microchip.com/downloads/en/appnotes/00885a.pdf

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