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Due: January 23rd, 2014

Prob. 1. Use any size technology and generate the equivalent plot (see around page 20 Lect. #1) of various parameters versus the inversion level. i.e. fT vs if, power consumption, (W/L) vs if. also in another graph plot fmax vs if . Also add a trace for Vdsat vs if in the
same plot.

Prob. 2. Extract the parameters of transistors PMOS and NMOS for the ACM model, that is one equation all regions. See Ref. 6 on Lect. #1. Consider the 65nm and 180 nm CMOS technology and if = 7. Discuss how the parameters are extracted. Provide a table summarizing results of the extracted parameters. Discuss the results. Prob. 3. Design a simple amplifier that maximize output voltage swing Vout, with VDD = -VSS = 0.80V for a { 65nm, and 180nm} CMOS technology.
VDD RL=1K Vout Vin -VSS

a) Use conventional quadratic saturation transistor for your design. b) Now design for the same Vout but for if = {0.5,8, 80}. c) Compare results obtained in part a) and b) in terms of frequency response and step response for 1volt input step.

Note that a) refers to the classical transistor equation in saturation and part b) implies the use of the ACM model equation. Prob 4. Design, using conventional quadratic saturation transistor equation, a simple transconductance amplifier with a PMOS differential pair and a current mirror in 0.18um with a tail current of 4mA, Vdd=-Vss= 0.8V and a gain of 1000 v/v. Provide a table summarizing results for a load range of CL={1-50pF}. Reading Assignment.A.I.A. Cunha, Schneider, M.C.; Galup-Montoro C.; “An MOS transistor model for analog circuit design”. IEEE J. of Solid-State Circuits, Vol. 33, Issue 10, pp. 1510-1518, Oct. 1998. S. Yan and E. Sánchez-Sinencio, “Low Voltage Analog Circuit Design Techniques: A Tutorial”, IEICE Trans. Fundamentals, Vol. E82-A, No 2, pp 179-196, February 2000 L.L.Lewyn et all, “ Analog Circuit Design in Nano scale CMOS Technologies” . Proc. of the IEEE, Vol. 97, No. 10, pp. 1687-1714, October 2009