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Unit 5

5.1: CMOS Process Flow: The difference between new and old process flow are as mentioned here. Minimum length of the channel, L min < 0.35 micro m in the case of sub micron CMOS process. The device isolation technique is Shallow Trench Isolation (STI) instead of local oxidation of Silicon (LOCOS). n+ poly is employed for NMOS and p+ poly for PMOS formulation. Drains are lightly doped to reduce short channel effects. Silicided source / drain / gates are used to reduce parasitic resistances. NMOS & PMOS are developed as surface devices and thus PMOS is not a buried channel device. The steps in CMOS Process Flow: Step 1: The Process starts with p type wafer or p+ wafer with p- epitaxial layer. Thin oxide and nitride are deposited. The purpose of deposition is for active areas patterning. Photo resist is deposited and patterned on its top. Exposed area of nitride is then removed. The step is shown in fig. 5.1 (a)

fig. 5.1 (a) Step 2: Silicon areas that are exposed are etched. It is the part not covered by photo resist. Thus, shallow trenches are formed as shown in fig 5.1 (b) Shallow trenches

fig. 5.1 (b)

Step 3: Shallow trenches formed in step 2 are filled with Chemical Vapor Oxide (CVD) (STI). The process is known as Chemical Mechanical Polishing (CMP). Thus, the top is now flat as in fig. 5.1 (c).

fig. 5.1 (c)

Step 4: Implants are used to make body of the PMOS (n well) transistors. Fig. 5.1 (d) shows the wafer after implant.

fig. 5.1 (d)

Step 5: Patterning the polysilicon gates on the top of the wafer is carried out in this step. The effect of it is shown in fig. 5.1 (e).

fig. 5.1 (e)

Step 6: Light and shallow implants are used in lightly doped drain (LDD) MOSFET formulation as in fig. 5.1 (f)

5. It is also observed that short channel effect less severe. conduction between the source and drain is along the oxide / semi conductor interface. In surface device. 5.1 (f) Step 7: in this step. sources and drains are formed. The result of the same is shown in fig. Use of Silicide produces . p+ poly used in PMOS formulation results in surface device. MOSFET can be placed closer together. There is no need to counter dope the channel for the purpose.1 (g) Step 8: in this last step. threshold voltage of the PMOS is easier to set precisely. It is combination of silicon and tungsten metal. Thus.1 (g).fig. p+ poly is used in PMOS formulation. Implants to heavily doped gates.1 h) There are certain advantages of CMOS Process. fig. Now. And not through buried channel. 5. 5. Because of which. This leads to smaller active area windows. lateral oxide spacer adjacent to the gate poly is formed. silicide is deposited. CVD or STI enables to define smaller openings in the top of the wafer. fig. effective encroachment on the device width is reduced.

5. 5. 5.2. 5. Using native MOSFET capacitor: It is formed by laying out poly over n+ active in n well. The capacitor thus formed is a unipolar capacitor.2 fig. However. They are MOSFET as a capacitor. The symbolic representation of it is shown in fig. Using MOSFET as a capacitor: As shown in fig.devices with significantly less parasitic series gate and source / drain resistances.1: Implementation of Capacitors: four types of capacitors will be considered in the discussion to follow. drain and body are connected to ground. 5. It is also unipolar capacitor. Floating capacitor and Metal capacitor. Gate is available as one terminal. . source. If it is not satisfied. Silicide complicates the process.2. Native / natural MOSFET capacitor. capacitor exhibits non linearity.3 As in fig. fig. VGS should be much greater than 400mV for the device to behave as a capacitor.3. Surface device reduces mobility and increase in flicker noise.

two PMOS are laid together. Capacitors are in series as in fig. 5. The capacitance versus voltage in native capacitor is shown in fig.4 fig. poly over n+ active in n well reduces threshold voltage.5 The laying out of native capacitor is shown in fig.7. 5. fig. 5.fig.6. the increase in voltage at A causes accumulation of charges under the left side MOSFET gate oxide. 5. 5.6 The floating Capacitor: here.8 . The threshold voltage is 100mv. adjacent or inter-digitated in the same n well. Equal and opposite charge is stored in B MOSEFT.5. it suits for low voltage applications. Minimum voltage requirement is shown in fig. 5. Thus. 5.

fringe capacitance contribution is small. Capacitor with large bottom plate suffers from parasitic capacitance. It is the capacitance between metal1 and substrate. 5. Thickness of the metal increases if it is away from substrate. 5. .8 fig.7 Vx VDD fig. It requires an area of 100 micro m x 200 micro m for 1pF capacitor. Thus. The typical capacitance per micro m2 area is 25-50aF/micro m2.8 The Metal Capacitor: Metals (copper) have large layout area.fig. The capacitor is also referred to as metal1-metal2 capacitor. The layout is shown in fig.8 The two parallel plates in parallel plate capacitor are metal 1 and metal 2. Its value is significant and 80 % to 100 % of actual capacitance. 5. The presence of parasitic capacitance results in slow response from a circuit and waste of power. The capacitance between the two plates is given by C12=area x capacitance per area. 5.

5. Capacitance between metal 1 and substrate is now less. the total capacitance is given by C=C12 + C23 + C34.The 4 layers Metal Capacitor is shown in fig.11 respectively. It is because of minimum width and distance between two pieces of metal1.9. reduces area by 1/3rd. effect is predominant. in comparison with total capacitance C and hence there is reduction in parasitic capacitance.5 micro meters is the width and distance. fig.9 There is possibility of metal1 only capacitor also. If 0. 50aF/micro m2 requires area of 100 micro m x 200/3 = 66 micro m for 1pF capacitor. There is fringe capacitance. The layout of metal1 only capacitor and fringe effect is shown in fig.10 . fig. Thus. 5. Two metal pieces are placed close to each other in the layer above substrate. 5. in ‘metal1 only’ capacitor. Fringe capacitance is due to electric field terminating on the close adjacent metal. Effect of fringe capacitance is more than parasitic capacitance. 5.10 and 5.

as in metal1. fig. 5. 5. thumb rule for implementation of capacitance in a mixed signal circuit is lateral capacitance with several layers of metal and vias. 5. It is of the order of 200aF/micro m2. Thus. The capacitance per unit area increases. .11 Problem 1: Estimate the area of metal1 only 1 pF capacitor in a layout as shown in fig. Also determine parasitic capacitance. the rules for width and spacing between the metals are different. Thus. though not linearly.12.metal4 is shown in fig.5pF Capacitance With Via is yet another capacitance layout. for 1pF. 5.P1.fig. For higher levels of metal.P1 Solution Capacitance per 1 micro m2 is 25aF is given. The bottom plate capacitance remains at 15aF/micro m2. Lateral capacitance between vias. area = 1pF/25aF = 40000 micro m2 Parasitic capacitance (usually 50%) =1pF/2 = 0.

1 One of the properties of resistor is its Voltage Coefficient of Resistor (VCR). area = 1pF/200aF=5000 micro m2 5. leads to VCR ∆R / R problem. It is due to mismatch in voltages across two equal valued resistors even when same voltage is applied across each resistor. The Mismatch % is the variation in the same valued resistors.fig. 5. . Extension of depletion region into n type material in n well. . For 1pF.12 Example 2: Estimate the area of lateral capacitor for 1 pF capacitor in a layout.2: Properties of Resistors: the typical properties of variety of resistors is listed in table 3. Mismatch = VCR x difference in voltages across two resistors.1 Table 5.2. Solution: Capacitance per 1 micro m2 is 200aF because of lateral capacitance.

n+ poly. Value=2000. Value=500.0001% Minimum mismatch Mismatch error in p+ diff =0. Maximum Resistance per micro m2 is for n well Area = 1k/500=2 micro m2 Thus requires minimum area Example 4 Determine the minimum and maximum mismatch error while two 1Kohm are connected in parallel in the case of n well and p+ diff. Solution Minimum Resistance per micro m2 is for p+ silicide Area = 1k/2=500 micro m2 Thus requires maximum area.0005 ohm Error=0. n+ diffusion are the various types of resistors with and without Silicide.002 For two 1K in parallel.004 ohm . Example 3 Determine the minimum and maximum area required to implement resistor of 1Kohm in a Submicron CMOS process and also name the resistor type. All these errors will lead non linear behavior of resistor. Value=500.0002% For two 1K in series. Solution Mismatch error in n well =0.Temperature Coefficient of Resistor (TCR) is variation of resistance value with temperature. Polysilicon. (b) in series in the case of p+ without silicide.005 Error=0. p+. The error is found to be less in polysilicon. such as DAC. Comment on the results Solution Mismatch error in p+ without silicide =0.01 500.001% Maximum mismatch Example 5 Determine the mismatch error while two 1Kohm are connected (a) in parallel in the case of p+ without silicide. p+. Hence it is used in high precision circuits.001 For two 1K in parallel.001 ohm Error=0.

Each resistor of same value may have different gradient value. This ensures less mismatching and less self heating. This is called process gradient.2. This is referred to as Conductivity modulation. Simplified layout of a resistor is depicted in fig. The larger the area the better is heat dissipation. The minimum width of resistor is 10 times the process feature size (Lmin) and minimum length of resistor is 100 times the process feature size (Lmin). also. fig. Conductivity modulation is because of the difficulty in implementing a metal over resistive material.Error=0.0002% 5. The metal at a potential higher than the resistor attracts more electrons causing non uniform distribution of electrons and spots of lower resistivity in the resistor. Process Gradient is due to fault in manufacturing process. Taking the example of . Sometimes. Multiple connecting leads (contacts) reduce the metalresistive material contact resistance. 5. conductivity modulation is avoided by inserting a conducting shield connected to analog ground and metal1 between resistors and routing wire above the resistive array.13: simplified layout view of resistor The problems encountered in implementing resistor are conductivity modulation and process gradient. 5.3: Implementation of Resistors: There is a limitation on width and length of the resistor which can be implemented in CMOS submicron process. increasing the distance between the resistors and overlaying metal. Modification in conductivity is avoided by avoiding running metal over resistor. Or using high levels of metal to route the resistive signals. it is shown a resistor with large width and length for better matching and power dissipation.13. thus.

process gradient is assumed to be linear and +1 along horizontal dimension and +5 along vertical dimension. can be removed. to form any value resistor. MOSFET Switch employs either NMOS or PMOS.14. The layout of resistors for R-2R DAC with process gradient is shown in fig. 5. Thus. Digital switching resistance is function of width (W) .difficulty in implementing R-2R DAC. bidirectional switch. 5. there are several resistors of either R or 2R value. 8.11 and 13 are to be connected in series as shown in fig. Total process gradient of the series resistor is thus 38 units. 5. the problems associated with process gradient. To get 2R resistor of value 38 (Kohm or any multiple) units of resistor.14 5.3: Digital Circuit Design: Basic Building blocks in a digital circuit are MOSFET switch. delay elements. For the purpose of explanation. resistance with value 6. The binary weights given to different digital inputs vary if resistors are not exactly R and its double. fig. Thus. if linear. the discussion of their elimination is beyond the scope of this chapter. counters and adders. the process gradient also comes out to be same % as the resistor. The remaining errors in resistor are due to temperature and voltage. delta R/R is same for all resistors. The process gradient of resistor 6 and 8 are respectively (1+5) % and (3+5) %. Similarly. whereas process gradient of resistor 11 and 13 are respectively 11% and 13%.14.

digital switching resistance of the switch is. 5. Rn = 10kΩ L W 1 + K n (V DD − VTHN ) L ≈ KPn W fig.1) The circuit arrangement for determination of digital switching resistance is shown in fig.16 .15.16. 5. 5.15 fig. The plot of Rn versus Voltage sweep at drain is shown in fig. It is observed that the resistance increase with increase in VDS and decrease with increase in W/L of the device. Mathematically. For NMOS switch. VDS is varied and ID is noted.and length (L) of the device and also function of submicron CMOS process. digital switching resistance is given by Rn=VDS / ID (5. 5.

Rn=10Kohm(L / W)=10K/10=1Kohm Delay time for a load of 1pF=RnxC=1ns The plot of input and output versus time is shown in fig. 5. 5.5 V at 2ns. 5.20.2). output is 1. fig. determine the effective digital resistance of the MOSFET. .17 Solution The MOSFET has W / L =10/1.17. 5. The resistance of PMOS switch is given by eq (5. 5. When the input makes transition to 1.18 5. the output changes to zero volts by taking a delay time of 1ns. 5. The plot of resistance versus voltage sweep is shown in fig.5V.1: PMOS switch The arrangement for determination of digital switching resistance in the case of PMOS is shown in fig.18.19.Example 1 In the arrangement shown in fig. The resistance is double the resistance of NMOS device. fig.3. When the input is zero. Determine the delay time for a load of 1pF.

PMOS switch can not pass logic low well.2: Comparison of NMOS and PMOS switch In NMOS Rn increases with increase in VDD and in PMOS Rn decreases with increase in VDD. An average estimate of resistance suits for complementary static CMOS logic design. 5.20 5. the expression given holds good for all source to drain voltages. Device size selection is based on drive strength. It is an average estimate. .19 Rp = 20kΩ L W 1 + K p (V DD − VTHP ) L ≈ KPp W fig. NMOS switch can not pass logic high well whereas.fig.3. In NMOS source connected to ground and in PMOS source connected to VDD. In both NMOS and PMOS switches. 5.

C = 1pF • high-to-low and low-to-high delays = RnC= 5Kx1p=5ns Example 3 • Repeat the same for PMOS • Given W / L =40/20 • Digital switching resistance. . 5. The effective switching resistance is too large.3. 5.Example 2: Estimate the high-to-low and low-to-high delays in the circuit shown. Rn=20Kohm(L/W) =10Kohm • • • Capacitive load. 40/20 In Out 1pF fig.22. Assume the device to be of NMOS. The current flow is in bidirectional. It is because NMOS switch can not pass logic high well and PMOS switch can not pass logic low well.21 Solution • Given W / L =40/20 • Digital switching resistance. The circuit arrangement for the pass gate is shown in fig. C = 1pF high-to-low and low-to-high delays =10ns PMOS Device is slower than NMOS device 5.3: Bidirectional Switch: It is also referred to as pass gate. Vin is passed over to the output by increasing the gate voltage. Rn=10Kohm(L/W) =10K(20/40) =5Kohm • Capacitive load.

4: Importance of Delay Element: It is used in implementation of digital averaging or comb filter. 5. 5. Requirements of delay elements are that it should be with low power consumption and should occupy smaller layout area. Delay elements are also used in decimation circuit with factor K and in noise shaping filter. ADC. fig.fig. it is a rising edge triggered D flip-flop.24. clock and output is shown in fig. the output of the master is transferred to the slave. Delay element as a cascade of two pass transistors and inverters is shown in fig. 5. DAC etc.23 Working of Delay Element: Whenever the clock is high.23.22 5. Average of past & present input samples y(n)=(x(n)+x(n-1))/2. the output is unchanged. Number of past inputs referred in moving average filter is of the order of 100s or 1000s. Delay Element is continuously clocked circuit. Whenever the clock is low. 5. Thus. .3. The plot of input. Thus H(z)=(1+z-1 )/2.

it is because of 10 micro A for 100MHz clock speed. 5. it has less power dissipation.25 . It leads to more power dissipation. It requires two clock signals and has true output (no complement output).25.24 It requires two clock signals and has true output (no complement output). Clocked CMOS Logic: It is shown in fig. 5. fig. It has an advantage of ease of implementing RESET. 5. Layout area is larger. Maximum input to the inverters is VDD-VTHN. NMOS switch employed can not pass logic high well. VDD source has to supply excess current. It is also rising edge triggered D flip-flop. 50 micro A for 100MHz clock speed.OUT IN CLK fig.

For Divide-by-2 circuit. Divide-by-2 circuit divides the clock frequency by 2. Layout area is nearly same as Clocked CMOS Logic. 5. output=D input. It is referred to as True Single Phase Clocking (TSPC). fig. less than 10 micro A for 100MHz clock speed.27.No marginal logic levels. That is. output should change at the occurrence of every rising edge.26 . true and complement outputs hence Divide-by-2 circuit is possible. It exhibits less power dissipation. levels are either 0 or VDD. D input can be changed before the occurrence of the rising edge of the clock by connecting it to complement output. 5. 5. fig. The same Input-output relationship with respect to clock is maintained as in simple delay element. The output of Divide-by-2 Circuit using TSPC is shown in fig.26 At the rising edge of the clock.26. Two outputs. Some of the applications are in decimation and interpolation multirate systems and in up / down counter. It is rising edge triggered. 5. A single Clock Delay Element is shown in fig.

5. the complement output of each flip flop is connected to its D input.27 In ripple up counter shown in fig. Output is taken from complement output points of flip flop.28 fig. 5. each D flip-flop is TSPC. Output is taken from true output points of flip flop. 5.fig. fig. The complement output of each flip flop is connected to its D input.29.28. 5. The clock for a flip flop is derived from complement output of lower order bit flip flop. 5. Whereas in ripple Down Counter.29 . as shown in fig. The clock for a flip flop is derived from complement output of lower order bit flip flop.

5.Synchronous Up Counter is designed using ripple up counter. A multiplexer selects data of n .30. the output is taken from complemented output of second stage of flip flop. In a similar way. 5. in this case.30 fig. The output is taken from complemented output of second stage of flip flop. fig. The arrangement is shown in fig. Synchronous down Counter is designed using ripple up counter.31 Synchronous Up / Down Counter: It is designed to count either in up direction or in down direction. 5.31. The direction of count is decided by select line. The arrangement is shown in fig. The output of ripple down counter is fed to a set of D flip flops which are clocked simultaneously. 5. The output of which is fed to a set of D flip flops which are clocked simultaneously.

1) sum = a in . the simplication of truth table for full adder gives the expression for the sum and carry as in eq. The circuit arrangement for the same is shown in fig.bin . This continues and the counter counts down. 5. when all ones are added with all ones.3. 5.1 and 5.33.5: Full Adder: The circuit arrangement for full adder using MOSFET is shown in fig. fig.bits with its LSB as 1 and all other bits as zeros if up counter is selected. fig. The output of counter is fed as one input to the adder and other input is n bit data through multiplexr.2) . Thus the first output from the counter will be all ones.cin + ( a in + bin + cin ) cout (5.32 5. n bit data gets added with the counter output every time and there will be an output counting in up direction. During next cycle. During up counter. during down counter selection.bin + c in ( a in + bin ) (5. The counter output is zero initially. 5. the count reduces by one.2. n bit data is all ones and counter output is initially zero. 5. 5.32.33 cout = a in . In a similar way.

5. VGS=VTHN+ ∆V . VDSsat = ∆V .1: Biasing: For the circuit of OPAMP differential amplifier the biasing is shown in fig. Leads to VDD = VSG8 + VDS2 + VSD3 + VGS5 VDD = ∆V + VTHP + ∆V + ∆V + ∆V + +VTHN Solving for.4-bit Pipelined Adder: Using the circuit arrangement of fig. Gate to source voltage. Through M8. 5. The output of this addition is made available only after the addition of all bits using three bufrers to hold the results.4V for both NMOS & PMOS devices. Selecting excess gate voltage is done as follows. For the circuit of OPAMP differential amplifier shown in fig. Let minimum voltage across drain and source of a MOSFET.15 micro m submicron process. 5. M3.34 5. 5.35. Least significant bits of two data are added and carry is propagated to the next stage. M2. KVL from VDD to ground is applied. . threshold voltage=0.4. fig. In a simlar way other higher significant bits are added. In 0.4: Analog Circuit Design: 5. 5. a 4 bit full adder is implemented as shown in fig.34.33. M5. ∆V it is 175mV.35.

5. Increase in output resistance increases gain. For NMOS the value is 185 micro A/V and for PMOS it is 105 micro A/V. 5. Small signal transconductance: Transconductance of PMOS is less than that of NMOS.37 and fig. The plot of transconductance versus frequency for both NMOS and PMOS are shown in fig. Increase channel length decreases speed.36 for NMOS device. As W/L increase resistance increases. .35 Selecting channel length: Small signal output resistance proportional to channel length in NMOS & PMOS devices.38 respectively for NMOS and PMOS devices. 5.fig. Typical plot of output resistance versus drain-source voltage is shown in fig. 5.

37 . 5.36 fig.fig. 5.

5x10^9 Hz and that for PMOS is slightly more than 10^9 Hz.39 . 5. 5.38 and fig. fig. The plot of ratio of AC gate current to AC drain current versus frequency are shown in fig.38 Transition frequency of PMOS device fig. 5. 5. Transition frequency of NMOS device is around 4.39.MOSFET Transition Frequency: It is the frequency at which AC gate current is equal to AC drain current V id fT = GS = 1 = 0dB L id High speed devices have large transition frequency.