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ECE 510-Digitial Integrated Circuit-I Winter-2011 CMOS Processing Technology

Presented By Sonia Sahu JAN-31-2011

Contents
Introduction Processing Steps
Wafer Formation Photolithography Well & Channel Formation Silicon Dioxide Isolation Gate Oxide Gate & Source/Drain Formation Contacts & Metallization Passivation Metrology

CMOS Process Enhancements


Transistors Interconnect Circuit Elements

INTRODUCTION

Silicon Different CMOS Technologies


P-well process N-well process Twin well process Triple well process

PROCESSING STEPS

WAFER FORMATION

Wafer-disk of Si,75-300 mm, <1mm thick Czochralski Method


High purity SiO2 melted in crucible. Dopant impurity(Boron or P) atoms added. Precisely oriented seed crystal dipped. Graphite radiator maintains temp. above MP of Si. Inert gas atmosphere maintained. Seed pulled upward while rotating. Si attaches to seed and re-crystalizes. Wafers cut from ingot.

PHOTOLITHOGRAPHY
Wafer coated with Photoresist(PR). Subject to selective illumination through Photomask(PM). PM-constructed with Chromium covered Quartz glass. UV light source floods from backside. UV light passes clear sections of Mask to expose the PR coated on Wafer. PR changes property after being exposed on UV.

PHOTOLITHOGRAPHY continued

Developer Solvent used to dissolve soluble unexposed PR, leaving islands of insoluble exposed PR. PM aka Reticle is smaller than Wafer. Stepper/Scanner moves Reticle. Projection Printing-lenses between Reticle & Wafer focus the pattern on Wafer surface.

PHOTOLITHOGRAPHY continued
Resolution Enhancement Techniques
wavelength of UV influences feature size that can be printed. Can cause distortion in the patterns exposed on the PR.

Optical Proximity Correction(OPC) Phase Shift Masks(PSM) Off Axis Illumination(OAI) Most recent one: Immersion lithography technique

WELL & CHANNEL FORMATION


Thermal Diffusion
PR on top removed from well areas Dopant gas placed on Si surface Thermal diffusion

Ion Implantation
Thick PR(3.5-5.5 um) used to block ion implantation Si substrate subjected to highly energized donor or acceptor ions(injected) Hit the surface and travel below forming regions with varying doping concentrations Rapid Thermal Annealing(RTA) step-At T>800C, dopants redistribute uniformly

WELL & CHANNEL FORMATION continued

Advantage of Ion Implantation over Thermal Diffusion-No need to raise wafer Temp. -Improves throughput & reliability

SILICON DIOXIDE FORMATION


Adv. Of Si over others Easily processable oxide. Can be easily grown & etched Thickness of SiO2 Thin oxide layer for transistor gates Thick oxide layer for high V devices Si Oxidation Methods Wet Oxidation While oxidation atmosphere has water vapor T= 900-1000 degree C Pyrogenic Oxidation-2:1 mixture of H & O used Rapid Process. Used to form thick oxide layers Dry Oxidation Atmosphere is pure Oxygen T=1200 degree C Forms better quality oxide Used to form thin oxide layers Used for Pad oxide formation Atomic Layer Deposition(ALD) Thin layer of material A is attached to the Si surface. A chemical(Material B) is introduced to produce a thin layer of the required layer. This process is repeated.

ISOLATION

Shallow Trench Isolation(STI)


Pad Oxide & Si Nitride layer acts as masking layer Trench Etch: Opening in Pad Oxide used to etch into well or substrate region Linear Oxidation: Linear Oxide grown to cover exposed Si Trenches filled with SiO2 using Chemical Vapor Deposition(CVD) Pad Oxide & Nitride removed Chemical Mechanical Polishing(CMP) used to planarize the structure

GATE OXIDE
Gate Oxide grown on top of planarized structure Oxide structure is called Stack Few atomic layers, each 3-4 Angstrom thick of SiO2 overlaid with oxynitrided oxide N increases k, which decreases EOT, thus performs like thin oxide

GATE & SOURCE/DRAIN FORMATION

Gate Oxide grown where ever Transistor is required (A=S+D+G). Elsewhere there will be thick Oxide. Deposit Polysilicon. Pattern Polysilicon(both Gate & Interconnect). Etch Exposed Gate Oxide(area of gate oxide not covered by polysilicon). Implant pMOS & nMOS S/D regions through windows down to well & substrate. Lightly Doped Drain-exhibit low C, high R-reduces device performance

GATE & SOURCE/DRAIN FORMATION continued


Modern Process: Layer of Refractory metal deposited on Si(gate polysilicon &/or S/D region). Refractory metal- high MP-not damaged during processing.egTantalum,Molybedenum,Titanium,Coba lt. Metal & Si react at elevated T to form layer of Silicide. Polycide Process-only gate polysilicon is silicided Silicide Process-both gate polysilicon & S/D regions are silicided. CMP Lowers R of polysilicon interconnect &/or S & D.

CONTACTS & METALLIZATION


Contacts
Holes etched in dielectric Contact cuts made to S/D according to Contact Mask Al used for wires. Tungsten(W) used for plugging

Metallization
Process of building wires to connect the devices. Al used. Al deposited either by Evaporation or Sputtering.

CONTACTS & METALLIZATION continued


Evaporation
High current passed through a thick Al wire in vacuum chamber. Some Al atoms are vaporized and deposited on wafer.

Sputtering
Ionize inert gas using RF or DC field. Gas Plasma produced. Ions are focused on Al target. Plasma dislodges metal atoms which are then deposited on wafer.

Etching : used to remove unwanted metal


Wet Etching: Pirhana solution(3:1 to 5:1 mix of H2SO4 & H2O2) used to clean wafers of organic & metal contamination & PR. Dry Etching: Plasma etching. Plasma charges the etch gas ions(Fl, Cl), which are then attracted to Si.

Metallization Scheme
Uniform layer thickness from 2nd to n-1 layer. Successively thicker & wider metal from lower to upper.

CONTACTS & METALLIZATION continued

CONTACTS & METALLIZATION continued

CONTACTS & METALLIZATION continued

PASSIVATION & METROLOGY


Passivation
Final step. Add protective glass layer called Passivation or Overglass. Prevents ingress of Contamination. Opening in Passivation Layer-connection to I/O pads & test probe points. Bumping-allows the chip to be directly connected to circuit board using plated solder bumps in pad openings.

Metrology
SEM-Scanning Electron Microscope. Raster scans the structure and observes secondary electron emission to produce an image of the surface of the structure.

CMOS PROCESS ENHANCEMENTS-TRANSISTORS Silicon On Insulator(SOI)


Transistor fabricated on Insulators-SiO2 or Sapphire Eliminates C between S/D & B thus higher speed & lower subthreshold leakage SOI Type-Sapphire
Thin layer of Si formed on Sapphire surface Si layer selectively doped to define different threshold transistors Gate oxide grown on top of this Polysilicon gates defined nMOS& pMOS formed by implantation

CMOS PROCESS ENHANCEMENTS-TRANSISTORS Silicon On Insulator(SOI)

SOI Type-SiO2
Si substrate is used Buried Oxide(BOX) grown on top of it Thin Si layer grown on top of it Si layer selectively implanted to form nMOS & pMOS transistor regions Gate, Source & Drain defined

CMOS PROCESS ENHANCEMENTS-TRANSISTORS

High k Gate Dielectrics


MOS Transistors need high gate C to attract charge to channel This needs thin SiO2 gate dielectrics But gate leakage high for thin gates High k material provides for thick dielectric & less leakage Hafnium Oxide (k=20), Zirconium Oxide(k=23), Si Nitride(k=6.5-7.5) Applied using ALD,CVD, sputtering

CMOS PROCESS ENHANCEMENTSTRANSISTORS


Low Leakage Transistors
Problem with transistors: sub-threshold leakage from drain to source New gate structure-gate placed on 2,3 or 4 sides of channel Finfets-S/D regions forms fins on Si surface Gate wraps around 3 sides of the vertical S/D fins Width of device = height of fins Wide devices constructed by paralleling fins

CMOS PROCESS ENHANCEMENTSTRANSISTORS


Higher Mobility
Increase in mobility improves drive current and thus Transistor speed Use of SiGe for bipolar Transistors Good RF performance Used in RF & High Speed switching Strained Si-Ge atoms implanted to Si-streches Si lattice-increased mobility by 70%-30% better performance

CMOS PROCESS ENHANCEMENTSTRANSISTORS


Plastic Transistors
Organic chemicals used to fabricate MOS transistors Built upside down Gold gates & interconnect patterned on substrate Organic insulator or Si Nitride laid down Gold S & D connections made Organic semiconductor (pentacene)is laid

High Voltage Transistors


Switching & High Power applications Tox & channel length large to prevent breakdown

CMOS PROCESS ENHANCEMENTSINTERCONNECT

Cu Damascene Process
Barrier to prevent Cu atoms from diffusing into Si & dielectric. Barrier layer over prior metallization layer. Via dielectric laid down. A further barrier layer patterned. Line dielectric layered on top of structure.

CMOS PROCESS ENHANCEMENTS-INTERCONNECT continued

Antireflective layer added to top(helps in litho) Two dielectrics etched away where lines & vias required. Barrier layer of Ta or TaN film (conductive) deposited to prevent Cu from diffusing into dielectric. Cu seed layer coated over barrier layer. Resulted structure electroplated full of Cu. CMP.

CMOS PROCESS ENHANCEMENTS-CIRCUIT ELEMENTS-CAPACITOR


Poly-Insulator-Poly(PIP) capacitor
Add a second polysilicon layer Thin oxide placed between two polysilicon layers C=1fF/um2 Used in Alalog Circuits(1-10 pF)

Metal-Insulator-Metal(MIM)
Common capacitor used in CMOS process Placed between layer n(top) and n-1 to minimise stray capacitance of bottom plate Insulator-Alumina(Al2O3), Tantalum Pentoxide C=1-4 fF/um2 Area efficient capacitors

Fringe Capacitor
Composed of interdigitated metal fingers Sucessive metal layers can be ganged to get more C

CMOS PROCESS ENHANCEMENTS-CIRCUIT ELEMENTS-RESISTOR


Can be built from any layer Final R depends on resistivity of layer Need undoped high resistivity polysilicon Mask used to block silicide where high value poly resistors are required Meander structure-no. of unit resistors used Dummy resistors/fingers replicate proximity effects such as etch & implant All resistors are matched

CMOS PROCESS ENHANCEMENTS-CIRCUIT ELEMENTS-INDUCTOR


Spiral Inductor-most common-spiral of upper level metal As process is planer, needs an underpass connection In addition to L, has parasitic components
Rs-sereis R of metal & contacts Cp-parallel C to gnd Cs-shunt C of underpass Rp-element that models loss in resistive substrate

CMOS PROCESS ENHANCEMENTS-CIRCUIT ELEMENTS-TRANSMISSION LINES Used on a chip to provide known impedance wire Microstrip TL
Wire of width w placed over ground plane Dielectric of height h and dielectric constant k Wire can be top level of metallization and ground plane next metal down

Coplaner Waveguide
Wire of width w spaced s on each side from coplaner ground wires

CMOS PROCESS ENHANCEMENTS-CIRCUIT ELEMENTS-NON VOLATILE MEMORY


Gate structure has stacked configuration
Thin tunneling oxide Floating polysilicon gate Gate oxide Polysilicon control gate

Normal Operation
Floating gate determines if transistor is conducting To program- source is left floating & control gate is raised to appx. 20 V. e tunnel into floating gate thus conduction. To deprogram- drain & source are left floating & substrate(or well) connected to 20V. E stored on floating gate are attracted away leaving the gate unprogrammed.

CMOS PROCESS ENHANCEMENTS-CIRCUIT ELEMENTSBIPOLAR TRANSISTORS BiCMOS Process-npn & pnp transistors added to CMOS process Used for specialized analog or HV circuits Parasitic pnp Transistor in n well process
P-substrate collector N-well base P-diffusion emitter

Parasitic npn Transistor

CMOS PROCESS ENHANCEMENTS-CIRCUIT ELEMENTS-FUSE & ANTIFUSE


Blown with high current or zapped with laser Antifuse-device that initially has high resistivity but can become low resistance when a programming V is applied. Used in programmable logic devices.

CMOS PROCESS ENHANCEMENTS-CIRCUIT ELEMENTS-MEMS

Micro Electro Mechanical Systems CMOS Process used to make MEMS Air Bag Sensor

References
CMOS VLSI Design- Weste & Harris http://web.cecs.pdx.edu/~chiang/ECE_425_525_Winter_2011/

Questions?