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Master thesis performed in Electronic Devices

**Author: Golnaz Ebrahimi Mehr
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Report number: LiTH-ISY-EX--13/4657--SE Linköping, April 2013

**Design of a ROM-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology
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............................................................................ ............................................................................ Master thesis Performed in Electronic Devices at Linköping Institute of Technology by Golnaz Ebrahimi Mehr

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LiTH-ISY-EX--13/4657--SE

Supervisor: Dr. Behzad Mesgarzadeh Examiner: Professor Atila Alvandpour Linköping, April 2013

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With 3. Sine weighted DAC . Return-to-Zero. Electronic Version http://www. Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.2 GHz sampling frequency. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. With 6. the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3. The power consumption is 80 mW for the designed mixed-signal blocks.Presentation Date 16 April 2013 Publishing Date (Electronic version) 29 April 2013 Department and Division Department of Electrical Engineering Electronic Devices Language × English Other (specify below) 65 Number of Pages Type of Publication Licentiate thesis × Degree thesis Thesis C-level Thesis D-level Report Other (specify below) ISBN (Licentiate thesis) ISRN: LiTH-ISY-EX--13/4657--SE Title of series (Licentiate thesis) Series number/ISSN (Licentiate thesis) URL. Interleaved DACs. Author(s) Golnaz Ebrahimi Mehr Abstract A 4 bit.6 GHz.2 GHz. Keywords Rom-Less DDFS. Current Steering Digital-to-Analog Converter.se Publication Title Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS technology.liu.4 GHz sampling frequency. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool.ep.

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Interleaved DACs.4 GHz sampling frequency. Sine-weighted DAC .2 GHz.Abstract A 4 bit. the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3. With 6. Current Steering Digital-to-Analog Converter. the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.2 GHz sampling frequency.6 GHz. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. Return-to-Zero. Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Key words: Rom-Less DDFS. The power consumption is 80 mW for the designed mixed-signal blocks. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.

for all his insightful discussions and guidance which was given with the most passion and generosity in time and knowledge. and Farrokh Ghani Zadegan. Behzad Mesgarzadeh for his valuable ideas. J Jacob Wikner.D. A big thank you goes to my beloved family. Thank you so much for the experience. I would like to thank my supervisor Dr. Ph. student of Electronic Devices division. 2 . I am also grateful for all the valuable help that I have received from Petter källström.D. student of Electronic Devices division. I am also thankful to all my friends. student of Electronic System division. I am also thankful from all other researchers who have helped me during this project.D. Ph. I also would like to express my gratitude to Associate Professor Dr. guidance and help during this project. Ph. my parents and my dear sister Golpooneh. Ph. His enthusiasm and curiosity is admirable. who have enriched my life with love and joy. for his discussions and technical help throughout this work. My acknowledgments to Linköping University.Acknowledgment I would like to express my deepest appreciation to all the people who have helped me during the conduction of this thesis work. My special thanks to Amin Ojani. for providing all the resources that I needed to learn and grow. for their unconditional love and support.D. student of Embedded Systems Laboratory. Ameya Bhide.

......................... 37 Chapter 4 DAC Interleaving ....................................................................................... 39 4................ 23 2......................................1 3.....................2.................................................................................... 38 4.........................................................................................................4 Anti-aliasing Filter ................................................................................2..........................................................1 The Phase Accumulator .............. 18 2..........................................................................2 The phase to amplitude converter ..............1....................................................................1 4............................................................... 24 Chapter 3 Noise Analysis of DDFS output spectrum ................................................................2 3.....................................................................................................................................1 1................................................................................................................... 39 4............................................ 13 2.................................................................................. 32 3...................................................................2 Direct digital synthesizer using triangle to sine wave converter .....................1..3.............................................................. 11 Chapter 2 DDFS Principles and Architectures ..............................................................................3 Spurious related to the phase truncation error......... 23 2...................................................3.2.................................................................................................. 40 4...............................4 The phase noise of the DDFS ..2 Dynamic performance ............................................................................ 10 List of Acronyms ....................... 26 3................................................................................. 28 Spurious related to the nonlinearities of the DAC .................... 21 2............... 28 3.............................................................................................................................1 Conventional DDFS .......1 Direct digital synthesizer using a sine weighted DAC .......................................................... 14 2.... 26 Spurious related to the DAC’s finite resolution .......................2 Data Interleaving DACs ..... 13 2....................................................................... 41 3 ..................... 1 Acknowledgment ..........................................................................................3 Data and Hold Interleaving DACs ............................................2 ROM-Less Direct Digital Synthesizers........................ 9 1.....................................................................3 Motivation ...............3.................................Contents Abstract ......................2.........2............................. 7 Chapter1 Introduction .............................................................................................. 5 Table of Tables ... 38 Different approaches for DACs interleaving ...................... 9 Thesis Organization ...................................1 Hold Interleaved DACs ....3 Output spectrum of the digital to analog converter ............................1 Static performance ............................ 17 2............................................................................................... 28 3.........................................................3 The Digital to Analog Converter....................................... 35 3..............................................................2 DAC limitations for high frequency performance ...................... 2 Table of Figures .......................................................................1.......................2 1.........................................................................................................1.............................................

...................................... 46 5............................................................................................................................................................................................... 65 Appendix A ............2 5.......................................1 5.................................................................... 64 References ...................3 The Interleaving and Return to Zero approach used in this project .......................................................... 46 High Level Simulation Results ....................................................................................4...................................................................................... 55 Future Work ..................................................................................................................................................... 52 Transistor Level Simulation Results ....................................................................................... 68 4 ......................3 System Overview ....... 42 Chapter 5 Designed Direct digital frequency synthesizer .......

...................................... ............................................................................... Image replicas of the second DAC (b) and Image replicas of the Interleaved DACs (c) [21]............................................................................................ 54 Figure5-10 The SFDR versus FCW ................................................................................. .. 36 Figure 3-7............................................................................................. 20 Figure 2-8 Frequency response of DDFS (a) Ideal anti-aliasing filter (b)............ 35 Figure 3-6 Image replicas and nonlinearities in a DAC [9] ....................................... 54 Figure5-11 The sine wave generated with FCW=2.... 25 Figure3-1 DDFS Spur Sources [1]......................................... 20 Figure 2-7 N bit segmented current steering DAC ...................................................................................................................................................................................................... ................... ................................................................. .................................................................. 56 Figure 5-13 The output spectrum of DDFS MHz output frequency with 3.............................................. TSC transfer function (b) [18]...... 41 Figure4-3 Data and Hold Interleaving [9]............................... 43 Figure4-5 Image replicas of the first DAC (a )...................... 49 Figure 5-5 The Current Cell of Current Steering DAC .................. ............................ 40 Figure4-2 Data Interleaved DAC ............................................... ............... .......................... 22 Figure 2-9 DDFS Block Diagram using sine weighted DAC [2]..................................................... 47 Figure 5-3 The comparator of ADC ...... 44 Figure 4-6 Return-to-Zero Effect[21] ...............................2 GHz sampling frequency........................................................................................................... 47 Figure 5-4 The block diagram of sine weighted DAC......................................... using discharge transistors ...................................................... 55 Figure 5-12 The sine wave generated with FCW=2....................................... 47 Figure 5-2 The Block Diagram of Flash ADC ................................ 32 Figure 3-5 The Current Cell of Current Steering DAC .................................................................... .................... 19 Figure 2-6 N bit thermometer coded current steering DAC........... 52 Figure 5-8 The generated triangle and sine waves with FCW=1....................................................................... MHz and 3..............4 GHz sampling frequency ................................................... 24 Figure 2-10 DDFS Block Diagram using triangle to sine wave converter [3].......... 42 Figure4-4 Interleaved DAC block diagram [9]........................ ............................................... with 6.... ................................Table of Figures Figure2-3 Pipelined Phase Accumulator [18].. 51 Figure 5-7 Return to Zero................................................... 57 Figure 5-14 The spectrum of MHz.......... ........................... 36 Figure 4-1 Hold Interleaving DAC.............................................................................. .....................................75 GHz output frequency.......................................................................................... 16 Figure 2-4 Logic to exploit quarter wave symmetry [1]........................................................................................................ Realistic anti-aliasing filter (c) [5]................................................ ................... 29 Figure 3-3 Thermometer DAC with finite output current source impedance [7]..................................................................................... 18 Figure 2-5 N bit binary weighted current steering DAC........................................................ .................................................................................. MHz and 6............................................................................... ............................................................................................................................................................. ..... 50 Figure 5-6 The implemented System ....................... 25 Figure 2-11 TSC schematic (a).......................... 53 Figure5-9 The output spectrum of 1................ 45 Figure 5-1The block diagram of the designed DDFS................. 58 5 ......... The ZOH and Sinc function of DAC..................................................... .................................................................................... ........................................ 26 Figure 3-2 Transfer Characteristic of a DAC [20].............4 GHz sampling frequency...2 GHz sampling frequency.............................. 32 Figure 3-4 DAC’s full scale transition [20]...........................................

..........6 GHz) with 3...........2 GHz sampling frequency.........4 GHz sampling frequency............................Figure 5-15 The output spectrum of DDFS at Nyquist frequency (1............................................ 60 6 ....................... ...... ........................... 59 Figure 5-16 The Nyquist frequency output spectrum with 6....................

........................................................................................ 63 7 ................................................................................ 62 Table 5-3 The measurement results of previous works..................Table of Tables Table 5-1 The simulation results of this work ............................................... 61 Table 5-2 The simulation results of previous works ......................

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For example. DDFS is only capable of producing the exact integer division of the reference clock frequency when the FCW is 2 to the power of an integer. direct digital phase and frequency modulation in the digital domain and low phase noise. This characteristic is useful for the systems that need multiple clock frequencies with no integer relationship between them and they need to be changed rapidly and frequently [5]. this approach needed a huge number of current cells. The first approach in ROM-Less DDFS architecture was to use all thermometer sine-weighted DAC [4]. some applications use a hybrid frequency synthesizer. Moreover. In order to take advantages of both PLL and DDFS. However.1 Motivation A direct digital frequency synthesizer (DDFS) uses digital signal processing to generate frequency and phase tunable output signals. The second approach in ROM9 . Consequently. The segmentation of nonlinear DAC is more complicated than the linear ones and this architecture suffers from more complexity. The limitation of the tuning speed of the PLL comes from the produced delay due to its internal feedback [1]. However. ROM-Less architectures has been introduced [2] [3]. they can be utilized as a clock generator. DDFS has a variety of applications from instrumentations and measurements to modern digital communication systems. Aside from these advantages. fine frequency resolution. Moreover. PLL is capable of producing higher output frequencies. In modern communication systems. The division factor is set in a binary tuning word [5]. The generated output frequency is a division of the reference clock frequency. which produces output frequencies with N the resolution of its phase accumulator. PLL has the ability to lock its output to the input phase of a reference clock. to decrease the number of current cells segmentation algorithm for nonlinear DAC was proposed [12]. Therefore.Chapter1 Introduction 1. combining PLL and DDFS [5]. Fast switching speed is becoming more and more important in today’s wireless communication systems. The DDFS has the advantages of fast frequency switching. such as in spread spectrum communication systems. conventional direct digital frequency synthesizers are considered power hungry systems due to the use of ROM look up table in their architecture [2]. DDFS seems to be an alternative to phase-locked loops (PLL).

the principles of the DDFS will be discussed through explaining the conventional DDFS architecture and the functionality of each block. However. 10 . Moreover. the results of the previous works with different architectures of DDFS will also be presented. a new figure of merit was introduced in [2] to also take in to account the amplitude resolution information. The Verilog-A codes used for high level blocks including the phase accumulator and complementor can be found in Appendix A. This method uses the parabolic approximation. the phase to amplitude conversion error. In chapter three. the error sources of the DDFS including the phase truncation error. the introduced errors due to the nonlinearities of the DAC and the DDFS phase noise will be discussed. ROM-less architectures including the ones using nonlinear DAC and triangle to sine wave converter will be introduced. the most important performance parameters are sampling rate. the direct digital synthesizers are mostly designed in indium phosphide (InP) HBT. with high spectral purity. Interleaving with return to zero (RTZ) technique has been used to achieve a high bandwidth. In the DDFS design. This method shows a moderate precision in triangle to sine wave conversion [3]. In this chapter DAC interleaving principle and its different approaches will also discussed. 1.2 Thesis Organization The organization of this thesis is as follow. the designed architecture in this project will be discussed and it will be followed by high level and transistor level simulations.Less DDFS design is to use the triangle to sine wave conversion. Chapter four will cover the limitations of DAC for having a wide bandwidth. Moreover. silicon germanium (SiGe) HBT and SiGe BiCMOS technology [3]. In order to achieve high sampling rates and high synthesized frequencies. The effort in this project was to design a DDFS with multi-GHz sampling rate in 65nm CMOS technology. and utilizes the exponential current-voltage relationship of the transistors to implement it electronically. power consumption and spectral purity. In chapter two. In chapter five.

3 ADC List of Acronyms Analog-to-Digital Converter Bipolar complementary metal-oxide-semiconductor Clock Complementary metal-oxide-semiconductor Co-ordinate digital computer Decibel Digital-to-Analog Converter Direct Digital Frequency Synthesizer Delay-flip-flop Differential Nonlinearity Frequency Control Word Frequency-Shift Keying Greatest Common Divisor Third Order Distortion BiCMOS CLK CMOS CORDIC dB DAC DDFS DFF DNL FCW FSK GCD INL LSB LUT MSB MSK PAC Integral Nonlinearity Least Significant Bit Look-up table Most Significant Bit Minimum-Shift Keying Phase to Amplitude Converter 11 .1.

PLL ROM RTZ SNR SFDR TSC ZOH Phase Locked Loops Read-only memory Return-to-Zero Signal to Noise Ratio Spurious Free Dynamic Range Triangle to Sine Converter Zero Order Hold 12 .

13 . In order to change the frequency of the output signal. the most common DDFS architectures will be presented. With each clock cycle. The final block of the system is an ant-aliasing filter. 2. Direct Digital Frequency Synthesizer. FCW Phase Accumulator CLK Phase to Amplitude Converter Digital to Analog Converter Filter Figure 2-1 The Block Diagram of conventional DDS. The discrete-time. discrete-amplitude information of the sine will be converted to analog by passing through a DAC. The register restores the frequency control word (FCW). The result of this counting is the production of the phase information of the sine wave.1 Conventional DDFS The block diagram of a conventional DDFS is shown in figure 2-1. Also. which is the jump size of the counter. uses digital signal processing to generate frequency and phase tunable output signals. The DDFS consists of a phase accumulator. The phase accumulator consists of a counter and a register. The functionality of each block is described in more details in the following sections. The output of the phase accumulator will be fed to PAC. frequency control word (FCW) or the frequency of the reference clock can be changed.Chapter 2 DDFS Principles and Architectures As it was stated earlier. a phase to sinusoid amplitude converter (PAC) and a digital to analog converter (DAC) followed by a filter. the over flow of the counter is added to the FCW. In this chapter the DDFS principles are described through explaining conventional DDFS architecture. which converts the phase information of the sine wave to amplitude. DDFS.

2. In order to understand how the frequency is synthesized using a phase accumulator. 14 .1 The Phase Accumulator The phase accumulator is basically a counter which has the responsibility of generating the phase information of the sine wave. consider the phase wheel in figure 2-2.1. M = Jump Size N 8 12 16 20 24 28 32 Number of points: 256 4096 65535 1046576 16777216 268435456 4294967296 Figure 2-2 Digital phase wheel [5].

the counter completes one rotation around the phase wheel faster. Equation 2-1 = . Consequently. and consequently a higher output frequency will be synthesized. if N is taken to be 32. The resolution of the phase accumulator (N) determines how many phase points the phase wheel contains. consequently. and consequently it determines the resolution of the synthesized output frequency. we need at least two samples per cycle in order to reconstruct the sine wave. The FCW of 0111…1111 will result the counter to overflow after only two reference clock cycles (a complete rotation). 15 . in order to run the DDFS in high speeds. the highest output frequency that we can achieve is equal to The frequency resolution of the synthesizer ( Equation2-2 As the phase accumulator is not able to complete multi bit addition in a short clock period. A pipelined phase accumulator is shown in the figure 2-3 [1]. The relation between the reference clock frequency output frequency the FCW and resolution of the phase accumulator is given in equation 2-1. In every clock cycle. then the FCW of 0000…0001 will result the counter to overflow after reference clock cycles (a complete rotation) and gives the lowest possible output frequency. For example. is found when the FCW is set to one: . the over flow of the counter is added to the FCW which is stored in the phase accumulator register. A complete rotation of the phase wheel with constant speed will generate one complete period of a sine wave. According to Nyquist theorem. pipelined phase accumulator is usually used.Each point on the phase wheel is correspondent to an equivalent phase of the sine wave. FCW determines how fast the counter travels around the phase wheel. As a result of a higher jump size.

all the signal processing operations which are needed for synthesizing and tuning the output frequency of the DDFS. This is why the direct digital synthesizers are so attractive for digital modulation techniques. DFF Adder clk clk Adder clk clk clk DFF clk DFF clk DFF DFF DFF clk clk Adder 1’s Com plime ntor Adder clk Figure2-3 Pipelined Phase Accumulator [18]. 16 .As it can be understood from the above. such as FSK and MSK. is done in digital domain.

Using this algorithm the needed hardware is not growing exponentially when the output word size is increasing. the coefficient of the polynomial is stored in the ROM. In order to avoid a very large look up table. polynomial approximation and CORDIC algorithm. it will be fed to the phase to amplitude converter. In this method the interval of [0. Other ROM compression techniques include the Sunderland architecture. 17 . moreover a high resolution DAC will be needed to design. which will be discussed in the next chapter. The Nicholas architecture has improved the Sunderland architecture and hence has achieved a higher ROM compression. The look up table contains the amplitude information correspondent with each of the phase points of the phase wheel. and the two most significant bits of the phase accumulator output are used to distinguish the quarter of the sine wave. for example from 32 bits to 12 bits. The CORDIC algorithm has its advantage over ROM when the needed accuracy is more than 9 bits. For more information about this methods please refer to [1]. is divided in smaller divisions and the sine/cosine is produced in for each of them. However.2 The phase to amplitude converter After the phase information is generated by the phase accumulator. A large look up table decreases the speed of the synthesizer and increase the power consumption and die area. Nicholas architecture. Therefore. A very basic one is to use the quarter wave symmetry of the sine wave. which is a ROM look up table in the conventional DDFS. In the Polynomial approximations. In this case we say that the DDFS is truncated from k bits to j bits. The most significant bit illustrates the sign of the sine wave amplitude and the second most significant bit is used to determine weather the amplitude is increasing or decreasing. it is common to use only a fraction of the most significant bits of the phase accumulator information In order to produce a sine wave. In this case only the amplitude information of the 0 to π/2 of the sine wave is stored in the ROM. 12 bits still results in a large look up table. a tremendous work has been done to reduce the size of the look up table. The block diagram of this method is shown in the figure 2-4 [1]. The truncation results in spurs in the output spectrum of the DDFS.2. In the Sunderland architecture the large look up table is divided in to two smaller memories.1.

each current source is as twice as much of the previous one.1. However.wave. They can be implemented in binary weighted. The current steering DACs are the best choice for high speed applications because of their fast switching speed. discrete-amplitude information of the sine wave is fed to a digital to analog converter to be converted to a continuous-amplitude. 2. continuous-time sine. the discrete-time.MSB 2 MSB nd Phase Accumulator Complementor π/2 sine look up table Complementor 2π π/2 0 0 Figure 2-4 Logic to exploit quarter wave symmetry [1]. According to the digital input code a combination of the current sources will be switched to the output. The segmented architecture combines the binary weighted and thermometer coded architectures to take advantage of the benefits of both architectures. thermometer coded and segmented architectures are shown in the figures 2-5. It uses thermometer coded for its most significant bits (MSB) and binary weighted for its least significant (LSB) bits. As it can be seen in the figure 2-5. thermometer coded and segmented architectures. The binary weighted.3 The Digital to Analog Converter As it is shown in the figure 2-1. it suffers from differential nonlinearity (DNL) and the presence of 18 . in the binary weighted architecture. 2-6 and 2-7 respectively. This architecture has the advantage of small area and low power consumption.

Definitions and sources of the DAC nonlinearities will be presented in the next chapter. and the thermometer code turns on the switches accordingly.glitches. but it has improved DNL. low glitches and small switching errors. all the current sources are equal. A dummy decoder should be used for the binary weighted part to compensate for the delay of the thermometer decoder of the thermometer decoded part [9]. The digital input code is first fed to a thermometer decoder. In this architecture. It has to be noted that in the DDFS the dynamic performance of the DAC plays a significant role in the spectral purity of the output spectrum. which will be discussed in more details in the next chapter. The segmented architecture uses the thermometer coded for its most significant bits. thermometer coded architecture has more complexity and higher power consumption. which are more responsible for the dynamic performance. degrades its dynamic performance. I 4I 2I I Figure 2-5 N bit binary weighted current steering DAC. 19 . The considerations on how the resolution of each of architectures should be chosen in the segmented current steering DACs can be found in [19]. and binary weighted for its least significant bits. On the other hand.

Thermometer Decoder Switch Driver …………… ... Decoder Dummy Switch Driver Unary Switches Binary Switches Unary Current Sources Binary Current Sources Figure 2-7 N bit segmented current steering DAC 20 .I I I Figure 2-6 N bit thermometer coded current steering DAC. …………… .

consequently. In order to remove these images. 21 . Therefore. designing such a filter is not practical. the synthesized output frequency of DDFS is usually limited to less than 3/8 of sampling frequency [2].1. Ideally. some percentage of available bandwidth will be unusable. As the result of the zero order hold function.4 Anti-aliasing Filter As it will be discussed in more details in the next chapter. taking in to account only the image replicas. the DDFS is a sampling system. functionality of the DAC. Figure 2-8 (b) and (c) show the effect of the ideal and non ideal filter on the output spectrum of the synthesizer. a filter by an inverse function called anti-aliasing filter is used at the end of the system. However. The design of this filter is beyond the scope of this thesis.2. the amplitude of the images are weighted by the For most applications. with the sampling clock. these images are undesirable. Figure 2-8(a) shows the spectrum of the DDFS. Therefore. there will be images at the frequencies of the output frequency and of the output spectrum. this filter should have unity response over the Nyquist bandwidth and zero beyond that.

Realistic anti-aliasing filter (c) [5]. 22 .Amplitude Frequency (a) Amplitude Ideal filter response No aliases Frequency Amplitude No aliases Frequency 𝑜 /2 2 (b) Amplitude Realistic filter response Supressed aliases Frequency Amplitude No aliases Frequency 𝑜 /2 2 (c) Figure 2-8 Frequency response of DDFS (a) Ideal anti-aliasing filter (b).

Segmentation techniques for nonlinear DACs are more complicated than for linear ones.2. The most two significant bits are used to exploit the quarter wave symmetry of the sine wave. power and area bottleneck of direct digital synthesizers. In this architecture the sine/cosine mapping and the digital to analog conversion are performed in a same block. and these architectures suffer from complexity when the resolution is high [3]. In this architecture. the ROM look up table is the speed. segmentation techniques were proposed [12].1 Direct digital synthesizer using a sine weighted DAC In order to reduce the power consumption of direct digital synthesizers. direct digital synthesizers using this method still have high power consumption and limitations in higher frequency operations [3]. for each phase of the sine wave the sine weighted DAC switches the corresponding amount of current to the output. ROM-Less architectures based on sine weighted DACs has been proposed [4].2. Initially. The design challenges of the sine weighted DAC is mostly the same with the linear DAC. The two most common ones are described briefly in the following section. 2. The main difference between the sine weighted DAC and linear DAC is that in the linear DAC the current sources are identical with each other or they are a power of two weighted. these architectures used all thermometer sine weighted DACs.2 ROM-Less Direct Digital Synthesizers As it was stated earlier. in the sine weighted DAC the current sources are weighted according the amplitude of the sine wave [2]. ROM-Less architectures has been introduced. called sine weighted DAC. However. In order to reduce the number of DAC cells. Although a tremendous work has been done to compress the ROM look up table. 23 . Consequently. The block diagram of DDFS using a sine weighted DAC is shown in the figure 2-9.

2. 24 . The triangle wave is then converted to a sine wave using an analog sine-mapping methodology. Figure 2-11 shows the schematic and transfer function of the triangle to sine wave converter [18]. it decreases the truncation error. This architecture uses the most significant bit to exploit the half wave symmetry of the sine wave. The linear DAC produces a triangle wave which contains the analog phase information of the sine wave. which is implemented electronically by using the exponential current-voltage relationship of the transistors [3] [18].MSB 2 FCW nd MSB Phase Accumulator Complementor Nonlinear DAC CLK 2 0 Figure 2-9 DDFS Block Diagram using sine weighted DAC [2]. The output of the complementor will then fed to a linear DAC. consequently. 2.2 Direct digital synthesizer using triangle to sine wave converter The block diagram of a DDFS using triangle to sine wave converter is shown in the figure 2-10. This methodology uses the parabolic approximation. This architecture has a simple and low power structure and shows a moderate precision in triangle to sine wave conversion [3].

-1 Figure 2-11 TSC schematic (a). 25 .MSB FCW Phase Accumulator Complementor Linear DAC Triangle to Sine Converter CLK Figure 2-10 DDFS Block Diagram using triangle to sine wave converter [3]. TSC transfer function (b) [18]. Output signal Transfer function Analog triangle from DAC (a) (b) Equation2-3: Equation2-4: Equation2-5: .

These error sources include the truncation error of the phase accumulator. FCW Phase Accumulator Phase to Amplitude Converter Digital to Analog Converter Reference Clock Reference Clock Spurs Noise Phase Truncation Spurs Angle to Amplitude Error Spurs Nonlinearity of the DAC’s Spurs Figure3-1 DDFS Spur Sources [1]. and the phase that is used by the PAC for amplitude generation. the errors due to the nonlinearity of the DAC and also the phase noise. However.Chapter 3 Noise Analysis of DDFS output spectrum The direct digital frequency synthesizer has four sources of spurs. the output of the phase accumulator is usually truncated from N bits in to P bits. consequently. in order to have fine frequency resolution we would like to increase the resolution of the phase accumulator. this would result in large circuits that are needed to convert the phase data to amplitude data. the phase to amplitude conversion error. This truncation will result in a phase error between the generated phase by the accumulator. This error is periodic 26 . In this chapter these error sources and their effect on the output spectrum of the DDFS are discussed.1 Spurious related to the phase truncation error As it was stated earlier. which is shown in the figure 3-1. 3. Therefore. there will be an error in the generated amplitude.

)= Where. certain frequency control words result in the maximum level of the phase truncation spurs while some result in no error. The control words that yield the maximum spurs level should satisfy the following equation [5]: Equation3-1 (FCW. The generated spurs due to the phase truncation are the most significant spurs. Moreover.in the time domain and hence shows itself as spurs in the frequency domain [5]. Hence. any control word with 1 in the bit position of and 0 in all other least significant bit positions will result in no phase truncation spurs. )= Hence. The periodic nature of the error is due to the fact that after sufficient rotation of the phase wheel the accumulator phase and the truncated phase will coincide and there will be no phase error. the control word that yield to no truncation error should satisfy the following equation [5]: Equation3-2 (FCW. They will be mixed by the DDFS output frequency. which is calculated by the following equation [1] [2]: Equation3-3 27 . if we consider the DAC ideal. However. and will generate spurs at multiples of the output frequency. GCD denotes the greatest common divisor between the two variables in the parentheses. The pattern will continue as the phase accumulator continues to count. any control word with 1 in the bit position of and 0 in all other least significant bit positions will result in the maximum truncation spurs level.

02P Where. gain error. in high sampling rates circuits the dynamic nonlinearities play the significant role and being statically linear is the prerequisite for the DAC to have a good dynamic linearity [6]. integral nonlinearity (INL) and differential nonlinearity (DNL). This error will show itself as spurs in the output spectrum of DDFS. These errors will result a nonlinear 28 .2 Spurious related to the DAC’s finite resolution The finite resolution of the DAC and consequently the finite number of quantization levels of the DAC will result in an error.3 Spurious related to the nonlinearities of the DAC The most dominant spurs in the output spectrum of the DDFS is the spurs related to the nonlinearities of the DAC. and only considers the spurs due to the quantization error. It should be noted that this equation does not provide any information about the total SFDR of the system. P is the number of bits of the DAC and SQR is the ratio of the signal power to quantization noise power.3.3. Both static and dynamic nonlinearities will be discussed in the following section. The quantization error can be decreased by increasing the resolution of the DAC. called the quantization error. which is due to the limited resolution of the.1 Static performance The static specifications of a digital to analog converter include offset error. The relationship between the resolution of the DAC and the amount of quantization distortion can be quantified with the following equation [5]: Equation3-4 1.76 + 6. 3. however. The quantization error is basically the difference between the amplitude of the reconstructed sine wave and the ideal sine wave. 3.

because rather than the absolute accuracy. not equal to zero. Gain error: In the transfer function of the DAC. there will be harmonic distortions at the output spectrum of the digital to analog converter. together with the correspondent static nonlinearities. Offset error: offset error is the shift in the transfer function of the DAC on the vertical axis. The gain error is not of a big concern when a single converter is being used. consequently. the difference between the actual slope and the ideal slop is defined as the gain error.relation between the actual output level produced by the DAC and the ideal output level that the designer expects. which is briefly discussed in the following section. 29 . the DAC will output an analog value. Analog Output Ideal Straight Line Actual transfer function 1 LSB DNL INL Ideal transfer characteristic Offset Digital Input 000 001 010 011 100 101 110 111 Figure 3-2 Transfer Characteristic of a DAC [20]. the relative accuracy is of concern [6]. and it shows that for an input value of zero. Figure 3-2 shows the ideal and actual transfer functions of a three bit DAC.

as these techniques introduce more complicated circuits and consequently more parasitic capacitance. they do more harm than good in high frequencies [7]. Figure 3-3 shows a thermometer coded DAC. Moreover. and are the analog outputs corresponding to two successive codes of the converter. The differential nonlinearity can be given in terms of least significant bit step sizes with the normalized form according to the following equation [20]: Equation3-5 In the above formula. The current sources are considered ideal with current value of and finite output impedance of . The finite output impedance of the DAC current sources will also result in distortion in the output spectrum of the DAC. short distance between the transistors and equal environments by using dummy transistors [7]. N corresponds to total number of current 30 . calibration technique and trimming to overcome the matching problem of the DAC. Care has to be taken when designing the current cells to have as much matching as possible. to meet the static specifications. there have been introduced some techniques. Mostly. However. and = are the actual and ideal analog outputs of the converter. Integral nonlinearity (INL) and differential nonlinearity (DNL): If we consider a line that passes through the end points of the transfer function of the DAC. These errors are shown in the figure 3-2. transistor mismatch in the current source of the DAC cells and the finite output impedance of the current sources are responsible for INL and DNL [6].Monotonicity: The monotonicity of a digital to analog converter is its ability to decrease or increase in the same direction of its input signal. This can be done by using sufficient gate area for current source transistors. such as dynamic element matching. Moreover. the integral nonlinearity can be given as the accumulation of previous differential nonlinearity errors according to the following equation [20]: Equation3-6 In the above formula. the integral nonlinearity (INL) would be the maximum deviation between that line and the actual analog output of the DAC. The differential nonlinearity (DNL) is the difference between the actual step size and the ideal one least significant bit step size in the transfer function of the DAC.

The produced output voltage correspondent to the digital input word (n) in the figure 3-3 is equal to [7]: Equation3-7 } For full swing condition (n=N) the expression for the third order distortion can be written as [7]: Equation3-8 As it can be seen from the above formula. 31 . the output voltage will be signal dependant which will produce distortion in the DAC’s output spectrum.sources and n is equal to the digital input code. the total effective load impedance will be dependent on the input signal [7]. a high output impedance from each current source is needed. In low frequencies this can be achieved by using cascade transistors. for high frequencies this is not a sufficient solution. as will be discussed in the next section. hence. different number of current sources will be connected in parallel with the output load and consequently. however. With different input codes. for having a low third order distortion.

2 Dynamic performance The dynamic errors of the digital to analog converter include glitches. These errors are presented in the following section. These errors are shown in the figure 3-4. Analog Output Glitch Clock Feedthrough Ideal Transition Settling Time Time Figure 3-4 DAC’s full scale transition [20].Figure 3-3 Thermometer DAC with finite output current source impedance [7]. settling time and feed through effects. 32 . 3. Dynamic errors have a significant impact on the performance of the DAC and they even become more critical for higher output frequencies and sampling rates.3.

since it’s a code dependant error. The second one is the feed through of the clock to the analog output. Settling time: is defined as the time which is needed for the analog output to settle between the accepted error band of its final value and is due to the parasitic capacitances of the circuit. finite output impedance of the DAC will also result in dynamic nonlinearities. Feed through effects: feed through effects have two sources in a DAC cells. This error can be minimized by a careful layout and switches sizing. In the previous part it was assumed that the output impedance of the current sources are purely resistive. consequently. which can be due to skew between bits in the digital part or the timing mismatch in the switches of the DAC. All the dynamic nonlinearities associated with the switches can be addressed by using return to zero (RTZ) technique.Glitches: Glitches happen as a result of an unmatched switching time between different bits. a glitch will be occurred in the output. consider the case that the input code is changing from 0111 to 1000. the switching transients do not appear in the DAC’s output. consequently. which also can be reduced by minimizing the size of the switches and hence reducing the capacitive coupling of the switches to the output. which can be implemented both with analog or digital solutions. As it was stated earlier. Careful layout and using thermometer decoding can be used to degrade this effect. A current cell of a current steering DAC is shown in Figure3-5. The result is a signal dependant error from the inputs to the output of the DAC during the code transitions. The settling time should be kept as small as possible to have a low distortion on the analog output signal. Figure2-3 shows this situation. In analog return to zero technique the output of the current cells is forced to zero when the clock is low and their current is switched to the output only when the clock is high. it is possible that we get the analog converted of 111 for a very short period in the output. However. The first one is the feed through of the digital signal through or of the switch transistors. For example. If the switching time of all the current cells do not be synchronized. at higher frequencies this impedance is modeled as the resistor in parallel with the effective output capacitance [7]: 33 . This phenomenon is much severe in high frequencies. which actually results in distortion in the Nyquist bandwidth of the output spectrum.

For current source (M2) the high output impedance and matching is of concern. This is one of the limiting factors for designing high speed DACs.Equation3-9 ) Accordingly. As it can be seen. with both M1 and M2 working in the saturation region. large sized transistors together with cascade transistors (M1). it can be seen in the above equation that the frequency of the DAC is limited due to the minimum achievable amount of . For switches (M) we would like to have small on resistance and minimum feed through effect. the cascade transistors (M1) should be just large enough to be able to support the current. in order to reduce the parasitic capacitances at the sources of the switches. 34 . minimum sized transistors can be chosen for them [7]. the third order distortion can be calculated as [7]: Equation3-10 Where. As the switches work with high gate-source voltage. N is the number of current sources. However. Therefore. sizing the transistor’s properly plays an important role in both static and dynamic performances of current steering DACs. which will be discussed in more details in section the next chapter. is the desirable choice. Moreover. As it can be understood from the above explanations. higher frequencies will result in higher third order harmonics.

with the ) the sampling frequency. the analog output will have a zero order hold function.Digital Circuit s M M 4 Digital Circuit s M1 Biasing Circuits M2 Figure 3-5 The Current Cell of Current Steering DAC 3.3. As the DAC samples the input in every clock cycle. It also should be noted that the the fundamental signal and all the images locating at amplitude of these images are decreasing in time. for integer values of m and n [9]. as it was discussed previously. This is because of the zero order hold (ZOH) behavior of the DAC’s response in the time domain. with the Sinc function as its Fourier transform. Taking in to account the Poisson summation. The time domain ZOH function and frequency domain Sinc function is shown in the figure 3-7. The amplitude of the Sinc function decreases in time. They will be mixed between the clock and the signal and will result in spurious components at the locations of . which leads to the 35 . Harmonics rise from the DAC’s nonlinearities. Image replicas rise from the sampling characteristics of the DAC. As it can be seen. the output spectrum consists of harmonics and image replicas. the output spectrum will be the summation of . the frequency domain of an ideal sampled signal is written as: Equation3-11 . Consequently.3 Output spectrum of the digital to analog converter The output spectrum of a DAC is shown in the figure 3-6.

decrease of the amplitude of the images. Signal Image Replica Nonlinearity Hold Distortion Figure 3-6 Image replicas and nonlinearities in a DAC [9] -2π/ Time Domain 2π/ Frequency Domain Figure 3-7. The ZOH and Sinc function of DAC 36 . in order to reconstruct the desired output waveform. It should be noted that the harmonics do not follow the Sinc function and it is not possible to predict their magnitude [5]. According to the Nyquist theorem at least two samples is required per cycle.

but DDFS is a feed forward system. However.SFDR and SNR are the most common terminologies that are used to describe the performance of the output spectrum of the DAC. where N is the division ratio. the phase noise which presents in the output spectrum of DDFS decreases by 20 log (N). and the jitter of the reference clock will have an important role on the output spectral purity. DDFS has a great advantage over PLL regarding to its phase noise. consequently. 37 .4 The phase noise of the DDFS The dominant contributor to the DDFS phase noise is the phase noise of the reference clock. the lower limit of the SNR is contributed by the quantization noise[20]. 3. because DDFS is a divider of the sampling clock. excluding the harmonics. SFDR stands for spurious free dynamic range and is the ratio between the signal power and the strongest spurious component in the output spectrum. Moreover. This is because PLL multiplies the phase noise of the reference clock in its feedback loop. PH is the power of the strongest distortion component. The SFDR is calculated as: Equation 3-13 SFDR= 10log (PS/PH) Where. which its output is a fractional division of the reference clock. In fact. SNR stands for signal to noise ratio and is the ratio between the signal power and the total power of the summation of all spectral components. as DDFS is a sampling system and the time interval between the samples are important. the purity of its output spectrum is directly affected by the purity of its reference clock. The SNR of an N bit DAC is approximately given by [9]: Equation 3-12 𝑜 Where. PN is the power of the total noise produced by the noise of the circuit (including the thermal noise and flicker noise) and the quantization noise.

2) According to the Nyquist theorem the applicable bandwidth of the digital to analog converters is limited to /2. 4. different methods of interleaving DACs will be briefly described and this will be followed by discussing the interleaving and return to zero technique used in this project and its influence on the output bandwidth. which are sampled at multiple phases of the clock. This will 3) As it was mentioned in the last chapter. the expression for the third order distortion is equal to: Equation4-1 38 . because of the zero order hold response of digital to analog converters.1 DAC limitations for high frequency performance High frequency performance of digital to analog converters is limited for the following three main reasons [9]: 1) As it was stated in the previous chapter.Chapter 4 DAC Interleaving Interleaving has shown promising impacts on expanding the usable bandwidth of analog to digital converters. Consequently. DAC interleaving categorized in two groups. data interleaving and hold interleaving [9]. In this chapter. interleaving the digital to analog converters also became an interesting approach for increasing their high sampling rate performance. after discussing the performance limitations of the digital to analog converters for high sampling rates and wide bandwidth. this approach is not as straight forward as ADCs for them. In interleaved ADCs the same input signal is fed to all sub ADCs. However. DAC has a zero order hold behavior in the time domain and consequently a Sinc frequency response with a null located at result in amplitude distortion for high frequency generated signals.

However.With the output impedance equal to: Equation4-2 ) degredation. In and Consequently. In the following section. the same data is used for all sub DACs.2. 4. 4. 39 .2 Different approaches for DACs interleaving Interleaving of digital to analog converters is categorized in two different groups of hold interleaving and data interleaving. In the hold interleaved DACs. each approach is described briefly. this approach does not give significant advantages for wide band applications. When the frequency increases. each clocked at time shifted version of the sampling clock. the requirement on the consequently on will give us a requirement on the . meaning that each digital data is sampled by each phase of the sampling clock. this gives us different approaches for interleaving the DACs. the required value of will decrease and it will be harder to achieve [7]. It was shown in [13] that this technique will lead to cancelling and lowering the aliases of the DAC by choosing the phase shifts of the sampling clock for each DAC correctly.1 Hold Interleaved DACs The block diagram of hold interleaving DAC is shown in the figure 4-1. it can be seen that increase of the frequency will result in the other words.

3 1 a 2 b 3 c 4 d DAC1 1 3 = a 3 4 DAC2 b 2 1 1 2 3 4 2 1 2 3 4 + DAC3 c DAC4 d Figure 4-1 Hold Interleaving DAC.2. and yet the fundamentals with the same phase. This suppression is done by having the Nyquist images with 180 phase shift. this approach requires the sampling rate of each DAC to be N .2 Data Interleaving DACs Data interleaving approach is shown in the figure 4-2. This approach was developed to suppress the Nyquist images so that the produced frequencies near Nyquist could be used without stringent requirements on the filter [14]. 40 . However. 4.

41 .1 a 2 = DAC1 /4 DAC2 1 3 2 4 1 2 3 4 2 1 2 3 4 3 b DAC3 c + 4 DAC4 d /4 Figure4-2 Data Interleaved DAC 4. the first N-1 image replicas and nonlinearity sours are cancelled. In this approach each DAC is fed with the interleaved samples of the signal and each DAC samples at interleaved time instants. Consequently.2.3 Data and Hold Interleaving DACs The block diagram of data and hold interleaving DACs are shown in the figure 4-3. and the wide band operation will be achieved [9].

if we consider that the second DAC is working on the phase shifted clock of the first DAC. As it can be seen from the figure. each DAC works at interleaved phases of the clock and holds its output for the entire period of the clock. the frequency domain components of the first and second DAC can be written as the following equations with taking in to account the effect of Sinc function on the amplitudes [9]: 42 . Consequently.1 a 2 b 3 c 4 d DAC1 = a 1 a 2 b + b DAC1 = DAC2 DAC2 + DAC3 c DAC3 c DAC4 d 3 4 d DAc4 3 2 1 4 1 2 3 4 2 1 2 3 4 Figure4-3 Data and Hold Interleaving [9] 4.3 The Interleaving and Return to Zero approach used in this project The block diagram of both data and hold interleaving DAC used in this project is shown in the figure 4-4.

Consequently. However. (the analog addition is done by return to zero technique). the resulting spectrum will be like a single DAC running with twice sampling rate and it will be possible to generate output frequencies beyond the Nyquist frequency of the individual DACs. This is shown in figure 4-5. With In order to push this null to 2 return to zero technique. it can be concluded that two interleaved DACs with return to zero technique is equivalent to a single DAC which is running with twice sampling rate [9] [21]. the usable bandwidth will not improve as much. since the zero order hold function of each DAC is not changing with this technique and they will have a null at which is the new Nyquist frequency. Consequently. 43 . As it can be seen from the above formulas. each DAC is only active for the half of the clock cycle. the images with odd values of k cancel each other when the outputs of the two DACs are added. Therefore. . the return to zero technique as an analog switch is used. so the sinc function will have its null at 2 which is shown in the figure 4-6. the images of the two DACs have the same sign for even values of k. while having opposite signs for odd values.Equation 4-3 DAC(I): ) Equation 4-4 DAC(II): ) DAC (I) Digital inputs 2 + DAC (II) Figure4-4 Interleaved DAC block diagram [9].

The cancellation of the images will not happen properly and unwanted spikes within the Nyquist band will occur if there will be any deviation from the ideal half sample time delay. Image replicas of the second DAC (b) and Image replicas of the Interleaved DACs (c) [21]. Correction algorithm for amplitude balance and time alignment might be applied to the system by the use of calibration filters if needed. and aligned input clocks have applied to each block [9]. 44 . The design of this filter is beyond the scope of this thesis. However.f (b) f (a) f (c Figure4-5 Image replicas of the first DAC (a). the two DACs must be balanced in terms of their amplitude. it should be noted that in time interleaved digital to analog converters time alignment plays an important role. Moreover.

2 Figure 4-6 Return-to-Zero Effect[21] 45 .

The Flash ADC converts the analog input to a thermometer code. However. The Verilog-A codes can be found in Appendix A. due to limitations of the filter design in the real implementation [2]. since they will be tolerated by the comparators of the Flash ADC. the sine weighted DAC only needs to produce the corresponding currents for the phases over the range of 0 to π. since the synthesized output frequency of the DDFS is restricted to be less than 3/8 of the sampling clock. The analog phase information of the sine wave will be the input to a flash ADC. Usually the thermometer code is fed to a thermometer to binary decoder to be converted to a digital binary code. so that a decreasing ramp will be achieved. so that the thermometer representation of the phase information is achieved. The Block diagram of the designed DDFS is shown in the figure 5-1. Moreover. The Flash ADC is known to be used in applications with tens of GHz sampling rates since all the conversion is done in one clock cycle. The block diagram of a 2 bit flash ADC is shown in the figure 5-2. this drawback does not show a strong impact in our application. the primarily purpose for choosing this architecture was to reach to a different contribution. will not affect the output spectrum of the synthesizer. When the most significant bit turns to 1.1 System Overview A four bit direct digital frequency synthesizer is designed in 65nm CMOS technology.Chapter 5 Designed Direct digital frequency synthesizer 5. However. This system exploits the half wave symmetry of the sine wave by using the most significant bit of the phase accumulator. The output of the complementor will be the input to a binary weighted DAC. The Phase Accumulator and the Complementor are behaviorally modeled in Verolg-A. consequently. Oversampling is known to put more requirements on the system and also using more power consumption. the complementor inverts its input digital bits. This combination cuts the number of sine weighted current cells in half. In order to increase the bandwidth and sampling rate of the system interleaving with return to zero technique described in the previous chapter is used. which is not the case in 46 . The binary weighted DAC produces the analog information of the phases of the sine wave. with taking advantage of oversampling. a simple combination of a binary weighted DAC and a Flash ADC is used. instead of the conventional digital thermometer decoder. It also should be mentioned that the mismatch and dynamic nonlinearities of the binary weighted DAC such as glitches.

MS B FCW Phase Accumulator Complementor Binary Weighted DAC Flash ADC Sine weighted DAC (thermometer) Filter CLK Figure 5-1The block diagram of the designed DDFS. and turns on the correspondent number of cells. The currents of these cells are added together and a sine wave is produced at the output. Vdd Vdd R R R R Figure 5-2 The Block Diagram of Flash ADC Figure 5-3 The comparator of ADC 47 . The produced thermometer codes will then fed to a sine weighted DAC. The circuit shown in the figure 5-3 followed by buffer is used as the comparator of the ADC. As for the N bit flash ADC comparators are needed.our system. usually their resolutions are restricted to maximum 8 bits.

The currents of the sine weighted DAC is calculated as: Equation 5-3 𝑜 𝑜 𝑜 ] ] 𝑜 ] 48 .The reference voltages of the flash ADC is calculated according to the following formula [11]: Equation 5-1 Equation 5-2 = = + Figure 5-4 shows the block diagram of sine-weighted DAC.

flip flops are used before the switches of the current cells. 49 . long channel transistors have been used. The load resistor is selected 25Ω. In order to decrease the impact of voltage variation of the drain-source of the current sources on the output current.Figure 5-4 The block diagram of sine weighted DAC. as for linear DAC. so that all the currents are switched to the output synchronized. to avoid the problem of the headroom in the interleaved system. In order to achieve high spectral purity it is important that the output current of each of the current cells be as precise as possible. The circuit of one current cell of the sine weighted DAC is shown in the figure 5-5. Moreover.

consequently the resultant spectrum will be like the spectrum of one DAC with twice sampling rate and each DAC can produce output frequencies beyond their Nyquist frequency. consequently. which is shown in the figure 5-7. as the zero order hold function of each DAC will not change with interleaving. 50 . to widening the bandwidth the return to zero should be used. However.Digital Circuits M M Digital Circuits 4 M2 Biasing Circuits M1 Figure 5-5 The Current Cell of Current Steering DAC Figure 5-6 shows the system level implementation using the interleaving approach. when the output spectrum of two interleaved DACs are added with each other. the odd images and harmonics of the spectrums of each DAC cancel each other. With return to zero each DAC is only active for its half clock cycle. the null of the Sinc function will be pushed to the 2 (with the sampling rate of each DAC) from The return to zero can be done by injecting zeros to the input of binary weighted DAC for each half clock cycle of the sampling frequency or by discharging the switch transistor of the current cells. As it was discussed in more details in the previous chapter.

1 3 5 7 1 3 5 7 RTZ Data FCW φ DAC Flash ADC Sine DAC Phase Accumulator Complementor MUX 4 2 6 CLK RTZ Data 1 3 5 7 φ DAC Flash ADC Sine DAC 2 4 6 2 4 6 Figure 5-6 The implemented System 51 .

2 High Level Simulation Results The architecture described in the previous section was first simulated behaviorally in Verilog-A. Equation 5-4 = 250 MHz 52 . the frequency resolution of in the Nyquist bandwidth is achieved. using discharge transistors 5.Biasing Circuits M3 M4 Biasing Circuits CLKB Digital Circuits Digital Circuits CLK M5 M M M6 Biasing Circuits M2 M1 Figure 5-7 Return to Zero. The phase Accumulator was designed for 4 bits. With 3 bit flash ADC and sine weighted DAC and 4 GHz sampling clock frequency. with Cadence Virtuoso design tool.

Figure 5-10 shows the SFDR versus different control words . = = 4GHz. Equation 5-5 The image replica ( ) of Equation 5-6 The SFDR in the Nyquist-Band is equal to: Equation 5-7 75.05 (dB) = 4 GHz= 1.75 GHz is shown in the spectrum.1.Figure 5-8 shows the triangle and sine waves generated with FCW=1. Figure 5-9.25 GHz This design is followed by a simple low pass RC filter. shows the output spectrum of the synthesized frequency for FCW= 7. 53 .9.25 (dB) = 66.75 GHz= 2. the SFDR is highest for the low synthesized frequencies (73 dB) and decreases to (64 dB) for near Nyquist synthesized frequency.As it can be seen from this figure. Figure 5-8 The generated triangle and sine waves with FCW=1.750 GHz output frequency. resulting in 1.3 (dB) .

SFDR= 66 dB (1. -25.39) dB 2.75 GHz output frequency.38 dB) Figure5-9 The output spectrum of 1. Figure5-10 The SFDR versus FCW 54 . -11.25 GHz.75 GHz.

2 GHz sampling frequency. MHz and 3.2 GHz and 6. The DDFS has been sampled with 3.2 GHz and 6. with 3. Figures 5-11 and 5-12 illustrates the generated sine-waveforms for FCW=2.4 GHz sampling frequency the frequency resolution was 400 MHz.2 GHz the synthesizer was able to synthesize outputs in 8 levels with each level 200 MHz. Obviously. With 3.4 GHz clock frequencies. 55 .5.4 GHz sampling frequencies respectively. with 6.3 Transistor Level Simulation Results The described system was designed and implemented in 65 nm CMOS technology. Figure5-11 The sine wave generated with FCW=2. with 4 bit phase accumulator and 3 bit flash ADC and Sine Weighted DAC.

Figure 5-12 The sine wave generated with FCW=2. The first image replica at 2.39(dB)= 60.400 MHz= 2.2 GHz clock frequency.23 (dB) = 3. The DDFS showed the SFDR of 60 dB. In the output spectrum the worst case spurs in the Nyquist Bandwidth is the third harmonic.2GHz.8 GHz 56 .4 GHz sampling frequency. Figure 5-13 shows the output spectrum of DDFS with 400 MHz output frequency and 3.2 GHz= 400 MHz = 3. Equation5-8 Equation 5-9 Equation 5-10 = 85.25.62(dB).8 GHz is also shown in the figure. MHz and 6.

39 dB) SFDR=60dB B) (Image Replica: 2. 57 .8 GHz. -56. -85.62dB) Figure 5-13 The output spectrum of DDFS MHz output frequency with 3.2 GHz sampling frequency.2 GHz.03dBdB) (Third Harmonic: 1.(Synthesized Frequency: 400 MHz. -25.

Equation 5-11 Equation 5-12 75(dB).52dB) SFDR= 45(dB) (Second Harmonic: 1.30(dB)= 45 (dB) = 6. In the output spectrum the worst case spurs in the Nyquist Bandwidth is the second harmonic. with 6.4 GHz sampling frequency 58 . -75 dB) Figure 5-14 The spectrum of MHz.4 GHz= 800 MHz (Synthesized Frequency: 800 MHz.6 GHz.4 GHz clock frequency.Figure 5-14 shows the output spectrum of DDFS with 800 MHz output frequency and 6. -30. The DDFS showed the SFDR of 45 dB.

6 dB) SFDR= 58(dB) Figure 5-15 The output spectrum of DDFS at Nyquist frequency (1. 59 .2 GHz clock frequency. The DDFS showed the SFDR of 58 dB.Figure 5-15 shows the output spectrum of DDFS at Nyquist output frequency and 3.6 GHz.6 GHz) with 3. -34. (Synthesized Frequency: 1.2 GHz sampling frequency.

60 . However. the power consumption without the phase accumulator was 80 mW. (Synthesized Frequency: 3.2 GHz.Figures 5-16 shows the output spectrum of Nyquist output frequency of 3. As the phase accumulator is behaviorally modeled with Verilog-A.36 dB) SFDR= 40(dB) Figure 5-16 The Nyquist frequency output spectrum with 6. the DDFS shows the SFDR of 40 dB. In this synthesized frequency.4 GHz sampling frequency. -39. the power consumption of the system could not be measured precisely.2 GHz with 6.4 GHz clock frequency.

=6. = 400 MHz) = 800 MHz) 3 bits 58 dB 40 dB 60 dB 46 dB 1. Table 5-1 The simulation results of this work Specification Technology Clock Frequency This Work 65 nm CMOS 3.2 GHz =6.4 GHz.4 GHz SFDR ( SFDR ( =3.2 V Power Supply 61 .2 GHz.4 GHz DAC Amplitude Resolution SFDR (Nyquist Frequency) =3.The simulation results of this work can be found in table 5-1.2 GHz 6.

3 V 462mW 0.41 W/GHz 1.8 V 271mW 0. Table 5-2 The simulation results of previous works Specification Technology Maximum Clock Frequency DAC Amplitude Resolution SFDR(Nyquist Range) Power Consumption Power Efficiency Power Supply [15] 350 nm CMOS 2 GHz [16] 180 nm CMOS 1 GHz [17] 90 nm CMOS 4 GHz 7 bits 8 bits 7 bits 35 dBc 20dB 44 dB 820 mW 0. the best achieved SFDR is 44 dB with 4 GHz sampling frequency in 90nm CMOS technology.271 W/GHz 3.2 / 2. As it can be seen.8 V 62 .Table 5-2 shows the published transistor level simulation results for DDFS in different technologies.116 W/GHz 1.

The difference in the power consumption of the nonlinear DAC architecture and the architecture using TSC converter does worth the attention.3 V Nonlinear DAC 50 mW 1.8W 3.7 dB 33 dB 44dB 460 mW 3.Table 5-3 shows the published measurements results for DDFS in different technologies and with different architectures.18 CMOS 1 GHz 8 bits 10 bits 8 its 45.3 V TSC Converter 4.8 V TSC Converter 63 .6GHz [18] 0.13 SiGe BiCMOS 8. Table 5-3 The measurement results of previous works Specification Technology Maximum Clock Frequency DAC Amplitude Resolution SFDR(Nyquist Range) Power Consumption Power Supply DDFS Architecture [3] 350 SiGe BiCMOS 5 GHz [2] 0.

This SFDR decreased to 58 dB for Nyquist synthesized frequency. In order to make it possible to have better comparison with measurement results of the previous works provided in table 5-3. simulation results showed the SFDR of 60 dB for 400 MHz synthesized frequency. with the most important ones the gain mismatch and time mismatch between the channels is another important aspect to be considered in the proposed synthesizer. As it was mentioned in the text. Nonidealities of the time interleaved DACs. limitations of the digital blocks should also be considered. Moreover. In [17] CML logic blocks have been used to make the digital blocks run with 4 GHz sampling frequencies.2 GHz synthesized frequencies respectively. CMOS technology digital blocks also show limitations for working with high frequencies. With 3. As it was stated in the text. The designed synthesizer was simulated using Cadence design tool. However. simulations should be run for taking in to account the process variations. However. Interleaving with return to zero has been used in order to increase the bandwidth and synthesized frequencies of the synthesizer. Therefore. Correction algorithm for amplitude balance and time alignment might be applied to the system by the use of calibration filters if needed. the phase accumulator and the complementor are behaviorally modeled in Verilog. With 6. In our design ideal clocks have applied to the system with 30ps rise time and fall time.4 GHz sampling frequency the synthesizer showed the SFDR of 40 dB for 800 MHz and 3. CML logics increase the power consumption of the system.A in this project. 64 .2 GHz sampling rate. any deviation from the ideal half sample time delay will result in imperfect cancellation of the images and spikes will be occurred in the output spectrum of DDFS. for designing high sampling rate DDFS.Future Work In this project a 4 bit direct digital frequency synthesizer was designed in 65nm CMOS technology. it is likely to increase the amplitude resolution of the nonlinear DAC to at least 7 or 8 bits and run the Monte Carlo simulations.

6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-weighted DAC/ IEEE Journal of Solid-States Circuits/February 2010 [3]. Direct Digital Frequency Synthesis by Analog Interpolation / IEEE Transactions on Circuits and Systems-II/ November 2006 [12]. Jouko Vankka / Nov 2000 [2]. A CMOS 8-Bit 1. Theory. Single Chip Direct Digital Synthesis vs.35-um / IEEE Journal of Solid-States Circuits/September 2011 [4]. Systematic Analysis of Interleaved Digital-to-analog Converters/ IEEE Transactions on Circuits and Systems-II/December 2011 [10]. Design of Low-Power Rom-Less Direct digital Frequency synthesizer using nonlinear Digital-to-Analog Converter/ IEEE Journal of Solid-States Circuits/ October 1999 [5]. A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0. A technical tutorial on Digital Signal Synthesis/ Analog Devices/1999 [6]. A 12 Bit GS/s DAC With IM3 < -60 dBc Beyond 1 GHz in 65nm CMOS / IEEE Journal of Solid-States Circuits/September 2009 [8]. An 11-Bit 8.References [1].6-GS/s DAC With Digital Random Return-to-Zero / IEEE Transactions on Circuits and Systems-II/January 2011 [9]. Direct Digital Synthesizer. the Analog PLL by Jim Surber and Leo McHugh [11]. Design and Applications. Segmented SineWave Digital-to-Analog Converters for Frequency Synthesizer / IEEE ISCAS 2001 65 . Basic Principles of Digital-to-Analog Conversion / Behzad Razavi [7]. Analog Devices/ Analog Dialogue.

com/articles/200912/dac-interleaving-in-ultra-high-speedarbs.php 66 . A High-Speed Rom-Less Direct Digital Frequency Synthesizer realized by a Segmented Nonlinear-DAC / IEEE Region 10 Conference / 2007 [17]. Current Steering Digital to Analog Converters: Functional Specifications. Digital Basics and Behavioral Modeling. Circuits and Systems / 2005 [16].evaluationengineering. [21]. Parallel-path Digital-to-Analog Converters for Nyquist Signal Generation / IEEE Journal of Solid-States Circuits/ July 2004 [15]. A 10-bit 500-Msamples/s CMOS DAC in 65 nm/ IEEE Journal of Solid-States Circuits/September 1998 [20]. A 4 GHz Direct Digital Frequency Synthesizer utilizing a nonlinear sine-weighted DAC in 90 nm CMOS / IEEE Asia Pacific Conference on Circuits and Systems [18]. A Low-Power Direct Digital Frequency Synthesizer Using an Analogue-Sine-Conversion Technique/ IEEE ISLPED /2011 [19].[13]. Symp. On the attenuation of DAC aliases through multiphase clocking / IEEE Transactions on Circuits and Systems-II / March 2009 [14].DAC Interleaving in Ultra-High-Speed Arbs http://www. 2 GHz 8-Bit CMOS Rom-Less Direct Digital Frequency synthesizer / IEEE Int.

67

Appendix A

`include "constants.vams" `include "disciplines.vams" module digital_input_4(out0, out1, out2, out3, , cout, codeout, clk, enable,reset);

output out0; electrical out0; output out1; electrical out1; output out2; electrical out2; output out3; electrical out3; output cout; electrical cout; output codeout; electrical codeout; input clk; electrical clk; input enable; electrical enable; input reset; electrical reset; // parameter description parameter real millivolt = 0.001; parameter real vlogic_high= 1.2; parameter real vlogic_low= 0; parameter real vtrans_clk= 0.6; parameter real vtrans_reset= 0.6; parameter real vtrans_enable= 0.6; parameter real tdel= 0; parameter real trise= 1f; parameter real tfall= 1f; //local integer variables integer reset_flag; integer count; 68

integer code; integer d[0:4]; integer i; parameter integer step= 1; integer decrease; analog begin @ (initial_step) begin for (i=0; i<5; i=i+1)begin d[i]=0; end count=0; end if (V(reset) < vtrans_reset) begin reset_flag =1; count=0; end

@ (cross( V(clk) - vtrans_clk, +1)) begin

if (V(enable) > vtrans_enable) begin reset_flag=0; begin count=count+step; end code=count%16; if(code > (8 + decrease)) begin code = code - decrease; end for (i=4; i>=0;i=i-1) begin if (code>15) begin d[i]=1; code=code-16; end else begin d[i]=0; end 69

trise. V(cout) <+ transition (vlogic_high*d[0]*d[1]*d[2]*d[3]. sigout). input sigin. trise.code= code*2. tfall). trise. sigout. sigref.flow) // sigout: // // INSTANCE parameters // sigout_high = maximum output of the comparator (val) // sigout_low = minimum output of the comparator (val) // sigin_offset = subtracted from 'sigin' before comparason to sigref (val) // comp_slope = determines the sensitivity of the comparator [] comparator output (val. parameter real sigout_low = 0. electrical sigin.tfall). trise.tfall). tfall). include "constants. end endmodule Based on Verilog-A written for comparator in the vhdllib of cadence. end end end V(out0) <+transition (vlogic_high*d[0]*!reset_flag. 70 .2. tdel.flow) module comparator(sigin. tfall). parameter real sigout_high = 1. tdel. tdel.h" // sigin: (val. V(out1) <+transition (vlogic_high*d[1]*!reset_flag. output sigout. V(out2) <+transition (vlogic_high*d[2]*!reset_flag.flow) // sigref: reference to which 'sigin' is compared (val. trise. V(codeout) <+ transition (millivolt*code). tdel. V(out3) <+transition (vlogic_high*d[3]*!reset_flag. tdel. sigref. sigref.

2 * (sigout_high . sigout_high.\n". sigout_high = (%E) less than sigout_low = (%E). end end V(sigout) <+1.sigin_offset)) + (sigout_high + sigout_low)/2. analog begin @ ( initial_step ) begin if (sigout_high <= sigout_low) begin $display("Range specification error. sigref). $finish. sigout_low ).parameter real sigin_offset = 0. end endmodule 71 .sigout_low) * tanh(comp_slope*(V(sigin.

72 .

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