AN1895 Application note

EVAL6562-375W Evaluation Board L6562-based 375W FOT-controlled PFC Pre-regulator
Introduction
This application note describes a 375W evaluation board based on the L6562 Transitionmode Power Factor Correction (PFC) controller (order code: EVAL6562-375W). The board implements a 375W, wide-range mains input, PFC pre-regulator that is suitable for a 300/350W ATX12V power supply unit (PSU). To enable the use of a low-cost device like the L6562 at a power level that is usually prohibitive for this device, the chip operates with a Fixed-Off-Time (FOT) control system. This allows Continuous Conduction Mode operation, normally achievable with more expensive control chips and more complex control architectures.

EVAL6562-375W evaluation board

August 2006

Rev 3

1/16
www.st.com

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Contents AN1895 Contents 1 2 3 4 Board description . . . . 15 2/16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . 9 4. . . . . . . . . . . . . . . 9 5 References . . . . . . 7 Getting started with the evaluation board . 3 Power stage design procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Appendix A Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Setting up FOT control with the L6562 . . . . . . . . . . . . . . . . . . . . . . . .1 Testbench results and significant waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .

with a slightly different usage.) is also adequate to drive the MOSFETs used at higher power levels. The L6562 controller chip is designed for Transition-Mode (TM) operation where the boost inductor works next to the boundary between Continuous (CCM) and Discontinuous Conduction Mode (DCM).AN1895 Board description 1 Board description The EVAL6562-375W evaluation board includes a Power Factor Correction (PFC) preregulator for a 300W ATX 12V power supply unit (PSU). More precisely.8A min. Table 1. which couples the simplicity and cost-effectiveness of TM operation with the high-current capability of CCM operation. The electrical schematic is shown in Figure 1 and the PCB layout in Figure 2. The control modulates the ON-time of the power switch. Table 1 summarizes the electrical specification of the application and Table 3 lists transformer specifications. This rail will be the input for the cascaded isolated DC-DC converter (typically a forward converter) that will provide the output rails of the silver box. typically realized with a fan capable of an airflow in the range of 25-35 CFM. Please refer to [2] for a detailed description of this technique. the evaluation board can easily deliver up to 400-420W. Electrical specifications Parameter Line voltage range Minimum line frequency (fL) Regulated output voltage Rated output power Maximum 2fL output voltage ripple Hold-up time Maximum switching frequency (@ VIN = 90 VAC. This approach. the chip can operate so that the boost inductor works in CCM. However. With an appropriate airflow and without any change in the circuit. hence surpassing the limitations of TM operation in terms of power handling capability. while its OFF-time is kept constant. is the Fixed-Off-Time (FOT) control. It is able to deliver 375W continuous power on a regulated 400V rail from a wide range of mains voltage. POUT = 375 W) Minimum estimated efficiency (@ VIN = 90 VAC. Appendix A lists the bill of materials. this is not allowed for in the design of this evaluation board. Although the ATX specification envisages air cooling. it will be used the Line-Modulated FOT (LM-FOT) where the OFF-time of the power switch is not rigorously constant but is modulated by the instantaneous mains voltage. POUT = 375W) Maximum ambient temperature Value 90 to 265 VAC 47 Hz 400 V 375 W 20V pk-pk 17 ms 100 kHz 90% 50° C 3/16 . Enough heat sinking will be provided to allow full-load operation in still air. The gate-drive capability of the L6562 (±0.

Electrical schematic diagram AN1895 Figure 2.Board description Figure 1. PCB layout. silk + bottom layer (top view) (150 x 81.5 mm) 4/16 .

66A 8 – 3Kr 8 – 3 ⋅ 0.56 = 7. It will be realized with four 0. The required inductance L of the boost inductor is: –6 Vout 400-t L = ( 1 – k min ) ------------= ( 1 – 0. The ripple amplitude on the top of the sinusoid at minimum line voltage. 1. The maximum expected input power Pin0 = Pout0/η and the maximum line peak current.6. The inductor peak current that the inductor must be able to carry without saturating will be: 1.AN1895 Power stage design procedure 2 Power stage design procedure The step-by-step procedure of an LM-FOT controlled PFC pre-regulator outlined in [2] will be followed.⋅ 6. k max = 400 Vin (RMS ) max -= 2 ----------------------------------Vout 265 . 1W-rated paralleled resistors.318 .= ----------------------3 f sw max 100 ⋅ 10 3.17Ω.= 3. table 4. From the formulae in [2]. assuming it is 75% of the maximum specified.17 8.318 ) ⋅ ---------⋅ 3.3 5.3.18 ⋅ 10 = 523 µ H ∆I Lpk OFFmin 1. The maximum inductor peak current.3 ∆I Lpk = -----------------Ipk max = -----------------------⋅ 6. The required tOFFmin is derived from the specification on the maximum switching frequency (on the top of the line voltage sinusoid) fswmax at minimum line voltage: k min 0. but we will go on using the target value. 5/16 .6 .8.6A I Lpksat = ---------0. 2 --------400 2. ILpkmax.18 µ s t OFFmin = -----------------. the MOSFET RMS current is: Pin 0 16k min 417 16 ⋅ 0.56A = ---------------------------Pin 0 = 375 --------.318 ⋅ 400 0.56 = 1. The design will be done on the basis of a ripple factor (the ratio of the maximum current ripple amplitude to the inductor peak current at minimum line voltage) Kr=0.= 3.318 .= 6. The maximum sense resistor Rsensemax is: 1. will be: 6Kr 6 ⋅ 0.216 Ω R sense max = -------------------I Lpkmax 7.= ---------------------------2 – ------------------------. Ipkmax are: 2Pin 0 2 ⋅ 417 . The range of k (kmin ÷ kmax) associated to the line voltage range is: k min = Vin (RMS ) min . 6. 4.= 0.2 – -----------------k min Vout 0.68Ω.39A I Lpkmax = -----------------lpk max = -----------------------8 – 3Kr 8 – 3 ⋅ 0. This provides some extra power capability.3. Ipk max = ------------------------k min Vout 0.= 10. the resulting value of Kr will be slightly smaller than 0.318 ⋅ 400 3⋅π 3⋅π .96A I Q ( rms ) = ------------------------.66 This value will be rounded up to 550 µH.937 . this will give some additional margin.= 2 ---------------------------------Vout 902 --------= 0.6V is the minimum value of the pulse-by-pulse current limiting threshold on the current sense pin of the L6562).39 (1. for a total resistance of 0.3 7.= ---------1. is calculated: 8 8 .= 0.318.9 .= 417W.

92 [cm ] 4 An E42 core (AP = 3.15 cm4) has been chosen. the minimum required AreaProduct is: ⎛ 1 – k min Kr Pin 0 t OFF⎞ . two of them will be paralleled to handle the rated power. housed in a TO220 package.17 = 0. a 0.65 is the minimum slope of the multiplier characteristic associated to the error amplifier saturated high (see Figure 9 in [1]). an 8A/600V Tandem diode.318 ⋅ 400 k min Vout 3 ⋅ π 3⋅π AN1895 The dissipation on the sense resistor will be 0. 6/16 . As for the inductor.Power stage design procedure The diode RMS current is: Pin 0 16k min 417 .= 2.29kΩ.3 ⎠ 0. the high-side resistor must be 1MΩ (see [3] for details.02 1. again from STMicroelectronics.39 ⋅ 0. The peak multiplier bias voltage VMULT @90V mains must meet the condition: I Lpkmax R sense V in ( RMS ) min ---------------------------------------.18 ⋅ 10 -⎞ -----------------------------------. the selected MOSFET is the STP12NM50.31 = 2. The high-side resistor of the output divider that sets the output voltage is chosen on the basis of the maximum allowed overvoltage on the output. a minimum of 180 µF is needed and a 220µF/450V capacitor will be used. The low-side resistor will then be 1MΩ · (400/2. 9. Assuming a minimum voltage of 300V after the line drop.65 V in ( RMS ) max . a compensation network made with an RC series (R = 6. where 1.≤ V MULTpk ≤ 3 ---------------------------------1.962=2. MULT) KP = 8·10-3 lets the peak voltage on the multiplier pin will go from 1V to 3V.65 Choosing the ratio of the resistor divider that biases the multiplier input (pin 3.3T.761 ≤ V ----------------------------------MULTpk ≤ 3 ⋅ 265 = 1.17 Ω): 907.-----------------0.= ---------------------------------------------------. the 6. Considering 40V overvoltage. which justifies the use of four resistors. See table 3 for the complete inductor spec.-----------------------------------------= 186 ⎛ ⎝ 0.31 1 – 0. in this respect the L6561 and the L6562 are exactly equal). All of them must be dissipated to keep their temperature within safe limits. the selected diode is an STTH806DTI. With the selected value for Rsense (0.34kΩ standard value will be used. Assuming a peak flux density Bmax=0.3 – 6 1.318 ⋅ 0.------------------------⎟ AP min ≈ 186 ⎜ --------------------------B max ⎠ ⎝ k min Kr 1.318 .5 . thus meeting the above condition.8 kΩ. C = 1 µF) guarantees a minimum of 25° phase margin (with 9 Hz bandwidth) at minimum line and a bandwidth not exceeding 20 Hz (with 50° phase margin) at maximum line.41A I Q ( rms ) = ------------------------. The output capacitor is determined by the hold-up time requirement.1) = 6.16 ⋅ 0. housed in a TO220 package. the core size will be determined by saturation since the ripple is relatively low.318 ⋅ 0.3 417 ⋅ 3.3Ω/500V MDmesh™ type from STMicroelectronics. Based on the model given in [2].7W.17·3.

Before starting the design.= ----------------------1357 .= 1357 Ω R' = --– 12 C 560 ⋅ 10 –6 . The ordinate of P2 (on the right vertical axis) gives the value K2=4. The required time constant is: –6 t OFFmin –6 3.AN1895 Setting up FOT control with the L6562 3 Setting up FOT control with the L6562 FOT control is implemented with the L6562 using the circuit shown in Figure 3. Following the design procedure given in AN1792. tOFF must be greater than 7µs. then the associated resistance value will be: τ. . 4. which shows some significant waveforms as well. with the aid of the diagram of Figure 4: 1. A capacitor C = 560 pF is selected.= 0. Figure 3. R1 and R2 will be respectively: R' .= 2. the desired value of tOFF at the maximum line voltage must be specified. 5.= 12450 Ω R1 = ---------------1 – K1 1 – 0. From P1 draw a vertical line as long as it intercepts the K2 curve relevant to VMULTpk=1 in P2.891 R'.891 the standard values R1 = 12kΩ and R2 = 1.76 ⋅ 10 .5kΩ will be chosen.52 ρ = --------------------------–6 3.17 3. Application note AN1792 shows that to reduce high-voltage distortion. The ratio of the maximum tOFF value to the minimum tOFF value is: 8 ⋅ 10 . Consider the value of VMULTpk at minimum line voltage (VMULTpk = 1V).17.= 1523 Ω R2 = -----K1 0.891.= -------------1357. hence we choose tOFF = 8µs. 7/16 . 6.= ---------------------------0. Circuit implementing FOT control with the L6562 and relevant timing waveforms. The abscissa of P1 gives the value K1=0. in Figure 4 draw a horizontal line located at ρ = 2.18 ⋅ 10 τ = --------------------= --------------------------.52 (on the left vertical axis) as long as it intercepts the ρ curve relevant to the value VMULTpk=1V in P1.18 ⋅ 10 –6 2.76 ⋅ 10 s K2 4.

Substituting: 15 – 5.= 363pF Cs < C ---------------------------------------------------------------. Cs will be selected according to the relationship: V ZCDclamp – 12 5. Diagrams for the design of the circuit of Figure 3 (valid for wide-range mains operation).7 ---------------------------------. IZCDx = 10mA the maximum ZCD clamp current D and VBE ≈ 0.= 739 Ω Rs > --------------------------------------------------------------------------------------------------------------------------– 3 5. Figure 4. a standard value Cs=330 pF will be used. VF ≈ 0. the limiting resistor Rs can be selected according to: V GDx – V ZCDclamp – V F Rs > ------------------------------------------------------------------------------------------------------------------------------------------------------------------------V ZCDclamp R2 + ( V ZCDclamp – V MULTpkmax – V BE ) R1 I ZCDx + --------------------------------------------------------------------------------------------------------------------------------------------------R1R2 where VGDx = 15V is the maximum clamp value of the gate drive voltage. VZCDclamp ≈ 5.55 ) ⋅ 12000 10 ⋅ 10 + --------------------------------------------------------------------------------------------1500 ⋅ 12000 in this case a 1.5 .7 ⋅ 1500 + ( 5.7 – 3 – 0. 8/16 .Setting up FOT control with the L6562 7.= 560 ⋅ 10 V GDx – V ZCDclamp – V F 15 – 5.5kΩ resistor will be chosen 8.5 .7 – 0.7 – 0.55V the emitterto-base forward drop of T.5V the forward drop on the diode.7V is the clamp value of the ZCD pin voltage. AN1895 Assuming that the VCC voltage never falls below 14-15V.

extreme caution must be used when working with the application board because it contains dangerous and lethal potentials. generated by an AC source ranging from 90 to 265 VAC. 4. If an electronic load is going to be used pay attention to the right polarity: the (+) output terminal is that located closer to the corner.1 Testbench results and significant waveforms The following diagrams summarize the results of certain testbench evaluations. The application must be tested with an isolation transformer connected between the AC mains and the input of the board to avoid any risk of electrical shock. A number of waveforms under different load and line conditions are shown for user's reference. Figure 5.AN1895 Getting started with the evaluation board 4 Getting started with the evaluation board The AC voltage. Evaluation data 9/16 . will be applied to the input connector. located close to the bottom left-hand corner. Warning: Like in any offline circuit. The 400 VDC output is located close to the bottom right-hand corner and will be connected to the load.

Getting started with the evaluation board Figure 6. Line current waveforms @ POUT = 375W 10/16 . Compliance with JEIDA-MITI & EN61000-3-2 standards AN1895 Figure 7. Harmonic emissions at light load (70W) Figure 8.

Line current waveforms @ POUT = 180W Getting started with the evaluation board Figure 10. Load transients from the maximum load to levels below 15W may cause the VCC to be lost as well. with 4W load the system would stop for 600 ms @ VIN = 90VAC).AN1895 Figure 9. Line current waveforms @ POUT = 70W Note: 1 Note that input LC filter is provided only to clean the line current waveform enough to prevent the measurement system from being misled by an excessive noise level. With lower load levels. 2 11/16 . The board. If supplying the L6562 with an external source. is able to handle properly an output load as low as 15 W.g. as is. The filter is not designed nor tested for EMI compliance. the minimum load that can be handled properly drops to virtually zero. the system will not start up correctly at low line because the OVP generated at startup lasts so long that the VCC voltage drops below the UVLO of the L6562 (e.

Enhanced Transition-Mode Power Factor Corrector”. AN1792. [3] “L6561.References AN1895 5 References [1] "L6562 Power Factor Corrector" Datasheet. [2] "Design of Fixed-Off-Time-Controlled PFC Pre-regulators with the L6562". 12/16 . AN966.

34 kΩ 330 Ω 330 nF 1 µF 10 nF 47 µF 1 µF 330 pF 560 pF 470 nF 220 µF TOR73 E4218 KBU8M 1N4148 1N5406 STTH806DTI 1N5248B L6562 BC557 BS237 ----OS512 630V.9 mH / 6A.AN1895 Bill of materials Appendix A Table 2.3 Ω / 500V. The Bridge. M2 and D6 all share the same heat sink.l. Electrolytic Nichicon LS or equivalent 3.5 kΩ 12 kΩ 499 kΩ 6.8 kΩ 6. TO92. ¼ W.1A / 45V. all resistors are 1%. 250V FR-4. all capacitors are ceramic or plastic film.5 Ω. D0201.12 °C/W. ST PNP.8 Ω 0.r. Aavid Thermalloy 25V electrolytic EPCOS B81131 or equivalent 400V. Vishay or equivalent 3A / 600V. Supplied by ITACOIL s.r. TO220. 13/16 . ST Note: If not otherwise specified.3A / 75V. R7B. ST 18V / 500mW Zener. 8A / 1000V. MDmesh TM. R7C and R7D R8 and R12 R9 R10A and R10B R11 R14 CX1 and CX2 C1 C2 and C4 C3 C5 C6 and C10 C7 C8 C9 L1 T1 BRIDGE D1. GI or equivalent 0. ON Semiconductor or equivalent 8A / 600V. DIP8. Boost inductor. 1W Note R1A and R1B R2A and R2B R3 R4 R5 R6 and R13 R7A. D2.68 Ω 1. Tandem Hyperfast. supplied by ITACOIL s. glass case. EPCOS B32653 or equivalent 450V. ON Semiconductor or equivalent TM PFC controller.l. 0. EPCOS B32653 or equivalent Metal film. D3 and D4 D5 D6 DZ1 U1 M1 and M2 TR1 NTC1 F1 PCB Heat sink STP12NM50FP 0. On Semiconductor or equivalent NTC 2. Bill of materials Bill of material for EVAL6562-375W evaluation board Symbol Value 120 kΩ 620 kΩ 10 kΩ 47 Ω 6. See spec on table 3. 150 x 81. M1. Cu single layer 35µm. TO220FP. Extrusion Profile.5 mm 2. EPCOS or equivalent 8A.

9 mm for an inductance 1-10 of 550 µH Pin Start/End 1/10 6/5 Winding Main Aux Wire 20xAWG32 AWG32 Turns Notes Windings Spec & Build 58 (N1) Pins 1 & 2.l.Bill of materials Table 3. N67 Material or equivalent Horizontal mounting.r. Core Bobbin Air gap AN1895 EVAL6562-375W: boost inductor specification (part# E4218. pins 10 & 9 are shorted on the PCB 6 (N2) Evenly spaced 14/16 . 10 pins ≈ 1. made by ITACOIL s.) E42/21/7.

AN1895 Revision history Revision history Table 4. Minor editing changes. Date 20-May-2004 28-Aug-2006 Document revision history Revision 2 3 Initial release. on page 5. Changes 15/16 . Corrected Equation 1.

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