ETUDE D’UNE SOLUTION ÉVOLUTIVE POUR LA LECTURE DES DÉTECTEURS GERMANIUM DE L’ACCÉLÉRATEUR ALTO : DIGITIZATION FROM ALTO TO NARVAL

(DALTON)

Aurore Lermitage/Bernard Genolini Christophe Oziol/Bengyun Ky/Emmanuel Rauly Vincent Lafage/Xavier Grave

1

ETUDE D’UNE SOLUTION ÉVOLUTIVE POUR LA LECTURE DES DÉTECTEURS GERMANIUM DE L’ACCÉLÉRATEUR ALTO : 10 Décembre 2012 DIGITIZATION FROM ALTO TO NARVAL (DALTON) A Solution based on FPGA Xilinx Virtex-6 and Arm

Unité mixte de recherche CNRS-IN2P3 Université Paris-Sud 91406 Orsay cedex Tél. : +33 1 69 15 73 40 Fax : +33 1 69 15 64 70 http://ipnweb.in2p3.fr

1- Alto Physics 2- Present Alto acquisition system 3- Current energy chain 4- Track and hold signals 5- Current digital acquisition versus Dalton digital system 6- First objectives 7- Dalton system possibilities 8- Examples of FMC boards 9- Dalton Structure 10- Evaluation boards system 11- VHDL and language C development 12- First results 13- Cost estimation and tests 14- Current status

2

mercredi 12 décembre 2012 Alto physics Current experiment: Trigger : fast detectors (plastic scintillators) => fast timing (100ps to 1ns) Energy. Si or scintillator) => charge and/or current measurement Energy Time of flight 3 . shape and/or position (HpGe.

4 canal temps mort de codage : 5ms temps : ASIC CTR codeur de temps gamme de temps : 15.6 heures sur 47 bits pas de codage : 400ps non-linéarité différentielle : environ 3% temps mort de codage : 35ns Vitesse d’acquisition 20Mo/s VME TDC (time of flight) 4 .mercredi 12 décembre 2012 Presents Alto acquisition system Charge Preamp Analog Shaper ADC (energy) Comet Board CFD + Logic COMET amplitude : détection de crête gamme d’amplitude : 0 à 10V sur 13 bits (8192 canaux) résolution en énergie : 0.

mercredi 12 décembre 2012 Current energy chain fC V Preamp V Detector Shaper Analog memory V ADC C. De La Taille 5 .

et on s’arrange pour que les signaux en sortie de shaper aient toujours la même forme… mais quand on veut tenir des taux de comptage élevés. ce qui est parfois compliqué dans des expériences complexes à très grand nombre de canaux. ce n’est plus possible Le signal de hold est fourni par un trigger.mercredi 12 décembre 2012 Track an hold signals 3: Signal shaper maintenu (léger décalage) ADC 1: Shaper ? 2: Hold ? • • Le shaper intègre le signal. 6 .

V1724 Ex : VME + CPU Pre Amplifier Anti aliasing Filter Constant fraction discriminator FADC Digital signal processing DATA acquisition TDC VISU (osciloscopy) Dalton acquisition system Pre Amplifier Anti aliasing Filter Constant fraction discriminator FADC Digital signal processing DATA acquisition VISU (osciloscopy) Marvell µP Arm Armada 310 Linux 7 TDC Xilinx FPGA Virtex 6 DALTON .mercredi 12 décembre 2012 Current digital acquisition system Caen : Models V1721.

silicon detectors.mercredi 12 décembre 2012 First objectives Update IPNO Accelerator ALTO acquisition system (Comet boards) Energy measurement for Germanium detectors (From 10keV to 10MeV with a resolution of 2 keV-FWHM). Photomultiplier tubes Time stamping ( Basic time resolution of Germanium detectors is ~10ns) Manage at least 6 analog inputs/board (total = 128 channels) Trigger : continuous data recording and offline building (10kHz max. ~16µs max dead time) Gigabit Ethernet NARVAL link Perform real time high performances digital filtering 8 .

12v 9 .0)  Possibility to record data directly on external hard disk 500W 3. 5v.NARVAL embedded (internal/External hard disk Sata 2.PCI-Express 1x (Gen1 250MB/s) external .mercredi 12 décembre 2012 Dalton system possibilities Measurements made through daughter boards : .Others extensions ( FADC 12bits 1Gs/s.0 .8 analog channels (FADC 14bits 250Ms/s) .USB 2.Gb Ethernet . TDC.3v.16 analog channels (FADC 14bits 125Ms/s) . …) All mezzanines industrial standard FMC HPC LPC VITA 57 standard NARVAL (with Narval Support): .

External (LVTTL or AGATA trigger GTS leaf) Spiral 2 system compatibility Independent 19” Crate / Full independent acquisition system Integrated soft filtering 10 .External trigger via optical links (SFP / AGATA trigger GTS) .mercredi 12 décembre 2012 Dalton system possibilities Trigger management: .Wired input trigger Ganil compatibility or others Clocks synchronization (25MHz/100MHz): .internal distributed trigger .Internal .

resolution : 60ps FWHM FMC-LPC Time-to-Digital Converter Board 11 .mercredi 12 décembre 2012 Examples of FMC boards 12-Channels 125MSPS @ 14-bit FMC-LPC Analog-to-Digital Converter Board 16-Channels 125MSPS @ 14-bit FMC-HPC Analog-to-Digital Converter Board Dual 14-bit 250Msps A/D Dual 16-bit 800Msps D/A FMC-HPC Analog-to-Digital Converter Board 4-Channel 210 MSPS @ 12-bit FMC-LPC Analog-to-Digital Converter Board 18-Channels TDC 2.5ns dead time.

mercredi 12 décembre 2012 Schematics Diagram overview Gb Ethernet Ganil trigger 3x SFP Optical/GTS Leaf option DDR3 socket DDR3 1Go 1066Mhz Micro SD Flash RESET USB 2.0 EndPoint external H-DISK 8 CHANNELS FAST ADC 14b / 250Ms / EXTERNAL TRIGGER MEZZANINE BOARD PCIe 1X 250Mo/s I2C ROOT HPC Gb Ethernet MARVELL ARM V5 µP 88F6282 EndPoint SLOW CTRL DAQ MEZZANINE BOARDS 4 CHANNELS FAST ADC 14b / 250Ms / EXTERNAL TRIGGER MEZZANINE BOARD 18 CHANNELS TDC FPGA VIRTEX-6 PCI-E 1 Lane LPC GPIO 2x SATA 2 Internal /external H-DISK DEBUG RS232 EXT_CLK PLL EEPROM Config JTAG JTAG NAND Flash EEPROM SPI POWER 12 .

Oziol µP reset USB 2.0 Host CLK in LVCMOS Full reset 2 X FPGA 3X Optical User SMA diff in/out SFP Connector CLK Out LVCMOS GTS LEAF /data acq GANIL Trigger LEAF Connector Power on/off 13 .mercredi 12 décembre 2012 Dalton internal view 482mm/19” 220mm µP External PCIex 280mm internal SATA Mezzanine LPC Mezzanine HPC ADC/TDC inputs µP Serial µP Console External RS232 SATA ARM µP Eth Power in 1Gb Select FPGA Eth Optional 1Gb Power in Optional 2.5” SATA HDD Internal PSU 500W 12V 13A ARM µP FPGA V6 DDR3 SODIM 3U/88mm C.

mercredi 12 décembre 2012 Evaluation Board l 14 .

mercredi 12 décembre 2012 Internal FPGA developed structure SYS_CLK_P SYS_CLK_N CPU_RESET DCM IDELAYCTRL LOCAL PLL CONTROLER CLKLOCKED LOCAL CLOCK & RESET MANAGER HW_RESET RESET SOFT_RESET OSCILLOSCOPY FADC INPUT ALIGNEMENT DIGITAL PULSE PROCESSOR IBUFDS GTXE1 DAQ_CLK PCIE_REFCLK_P PCIE_REFCLK_N INPUT TEMPON READ-OUT PCIE MANAGER PCIE ENDPOINT INTEGRATED CORE MEZZANINE BOARD ENERGY & TIME PCIE_RX_P PCIE_RX_N SEQUEN CER PCIE_TX_P PCIE_TX_N DPP_READOUT FMC CONTROLER DALTON MANAGER SYS MONITOR IP PCIE 15 .

language C development and Narval support The full configuration of the FPGA is via PCI Express connection.mercredi 12 décembre 2012 VHDL .MWD “Jordanov” .Graphical linux management of the PCIex evaluation board Narval Support include: .Narval embeded is on test with open RD board . temp.dCFD and oscilloscopy .Readout of I2C memories. Sensors … Language C : .Implementation of PCI express block of the virtex 6 in 1X mode . VHDL code developed: .Management of the daughter board PLL .Web interface is on development 16 .Management and read of the 8 FADC ( 14 bits 250MHz LVDS) .

mercredi 12 décembre 2012 Firsts Results with a signal generator + Preamplifier 803lsb 803 lsb 17 .

mercredi 12 décembre 2012 Firsts Results with a signal generator + Preamplifier 304 lsb 510 lsb 510 lsb 304 lsb 18 .

mercredi 12 décembre 2012 Some signals (Germanium detector) High-rate acquisition (Co source) Low-rate acquisition (Co source) Acquisition over 12 µs MWD + trapezoidal filter parameters to be adjusted (flat-top. base line stability) 19 .

mercredi 12 décembre 2012 Noise measurement Noise RMS histogram (85.000 events) Typical noise: 420 µV RMS Range for noise measurement Base line noise over 85.000 events 20 .

1 keV FWHM Charge calculated offline with a digital filter on the direct output: trapezoïdal filter + base line subtraction Accuracy obtained by the dithering effect of filter 21 .mercredi 12 décembre 2012 Results with a cobalt source Resolution obtained: 3.

mercredi 12 décembre 2012 Dalton preliminary cost evaluation and Test bench Production estimated Cost for one single mother board is ~ 2800€ (with PSU & Crate) + 2500€ for an 8-Ch 250Ms/s FADC daughter board (Techway. 4DSP) Test system needs : 1 PC for Narval management + 8 preamp + 1 pulse generator for a full test of 1 germanium crystal All the boards are manufactured externally (PCB and stuffing) Validation is made at IPNO Testing board needed for production ~ 5000€ 22 .

mercredi 12 décembre 2012 Dalton status Schematics finished (PCB routing begins. trigger implementation to be done Embedded Linux on ARM tested on open RD evaluation Board (NARVAL support) linux drivers for : slow control and visualization for Evaluation board is tested External (off line) advanced Filtering is on development Commissioning on ALTO Orgam detector and source 23 . prototype expected at end of February) Additional mezzanine boards development VHDL codes are well engaged : Digital filtering (MWD) and readout validated but to improve Slow control via PCIex is done Digital CFD validated Read and filtering Test on germanium crystal done TDC.

mercredi 12 décembre 2012 Routing and constraints 24 .

5” SATA HDD Internal PSU 500W 12V 13A ARM µP FPGA V6 DDR3 SODIM 2U/88mm C.0 Host CLK in LVCMOS Full reset 2 X FPGA 3X Optical User SMA diff in/out SFP Connector CLK Out LVCMOS GTS LEAF /data acq GANIL Trigger LEAF Connector Power on/off 25 .mercredi 12 décembre 2012 482mm/19” 220mm µP External PCIex 280mm internal SATA Mezzanine LPC Mezzanine HPC ADC/TDC inputs µP Serial µP Console External RS232 SATA ARM µP Eth Power in 1Gb Select FPGA Eth Optional 1Gb Power in Optional 2. Oziol µP reset USB 2.