Abstract

This project presents the design exploration and applications of a spurious-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. Furthermore, this paper proposes an original glitch-diminishing technique to filter out useless switching power by asserting the data signals after the data transient period. There are different entities that one would like to optimize when designing a VLSI circuit. These entities can often not be optimized simultaneously, only improve one entity at the expense of one or more others The design of an efficient integrated circuit in terms of power, area, and speed simultaneously, has become a very challenging problem. Power dissipation is recognized as a critical parameter in modern the objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power dissipation. In this paper, we propose a high speed low-power multiplier adopting the new SPST implementing approach. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The modified booth encoder will reduce the number of partial products generated by a factor of 2. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation. In this project we used Modelsim for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification on targeted FPGA.

CONTENTS

ABSTRACT CONTENTS LIST OF FIGURES LIST OF TABLES

i ii v vii

CHAPTER -1: INTRODUCTION 1.1 INTRODUCTION 1.2 PROBLEM DEFINITION 1.3 AIM OF THE THESIS

01 01 03 03

CHAPTER-2: LITERATURE SURVEY 2.1 BACK GROUND OF PROJECT 2.2 DIFFERENT TYPES OF MULTIPLIERS 2.2.1 BINARY MULTIPLICATION 2.2.2 HARDWARE MULTIPLIERS 2.2.3ARRAY MULTIPLIERS 2.3 ITERATIVE TECHNIQUES 2.4 MULTIPLICATION OF UNSIGNED AND SIGNED NUMBERS 2.4.1 UNSIGNED ARRAY MULTIPLICATION 2.4.2.TWOS COMPLEMENT ARRAY MULTIPLICATION 2.5 BOOTH ENCODING 2.6 COMPRESSOR TREES 2.7 THREE-DIMENSIONAL METHOD 2.8 HYBRID MULTIPLICATION

05 05 05 05 06 07 08 09 11 14 16 24 27 28

CHAPTER-3: SPST MODIFIED BOOTH ENCODER 3. 1 SPURIOUS POWER SUPPRESSION TECHNIQUE 3.2 MAC 3.2.1 BLOCK DIAGRAM OF MAC 3.2.2 PROPOSED MAC ARCHITECTURE 3. 3 RADIX-4 MODIFIED BOOTH'S ALGORITHM 3.4 SIGN OR ZERO EXTENSION 3.5 CARRY-SAVE ADDER 3.5 CIRCUIT DESIGN FEATURES

29 29 34 34 35 35 35 36 37

CHAPTER-4: IMPLEMENTATION 4.1 BLOCK DIAGRAM OF VMFU 4.2 EXPLANATION 4.2.1 HIGH-SPEED BOOTH ENCODED PARALLEL MULTIPLIER DESIGN 4.2.2 MODIFIED BOOTH ENCODER 4.2.3PARTIAL PRODUCT GENERATOR 4.2.4TRUTH TABLE OF MODIFIED BOOTH ENCODER

39 39 43 43

43 47 48

CHAPTER-5: HARDWARE AND SOFTWARE ANALYSIS 5.1 INTRODUCTION TO FPGA 5.2 BLOCK DIAGRAM OF FPGA 5.3 FPGA DESIGN FLOW 5.4 IMPORTANCE OF COMPUTER AIDED DESIGN

50 50 50 53 58

CHAPTER-6: RESULT ANALYSIS 6.1. SIMULATION RESULTS 6.1.1 PARTIAL PRODUCTS GENERATOR 6.1.2 BOOTH ENCODER 6.1.3 CARRY SAVE ADDER 6.1.4 VERSATILE MULTIMEDIA FUNCTIONAL UNIT 6.2 SYNTHESIS RESULT 6.3 SUMMARY CHAPTER- 7: CONCLUSION &FUTURE SCOPE 7.1 CONCLUSION 7.2 FUTURE SCOPE

63 63 63 64 65 66 67 70 71 71 72

BIBILIOGRAPHY

74

LIST OF FIGURES

Figures 1) Fig 2.1 Basic Multiplication Data flow 2) Fig 2.2 Minimal Iterative Structures 3) Fig 2.3 multiplication of two positive 6-bit binary integers 4) Fig 2.4 generation, shifting, and summing of partial products in a 6 6-bit multiplier 5) Fig 2.5 dot diagram for a simple 16 16 multiplier 6) Fig 2.6 Array Multiplier 7) Fig 2.7 Rectangular Multiplier 8) Fig 2.8 Partial products for twos complement multiplier 9) Fig 2.9 Simplified partial products for twos complement multiplier 10) Fig 2.10 Modified Baugh-Wooley twos complement multiplier 11) Fig 2.11 Radix-4 Booth encoder and selector

Page No 5 8 10 10

11 13 14 15 16 16 18 19 20

12) Fig 2.12 Radix-4 Booth-encoded partial products with sign extension 13) Fig 2.13 Radix-4 Booth-encoded partial products with simplified sign extension 14) Fig 2.14 Radix-4 Booth-encoded partial products for signed multiplication 15) Fig 2.15 Dot diagram for array multiplier 16) Fig 2.16 Dot diagram for Wallace tree multiplier 17) Fig 2.17 Dot diagram for [4:2] tree multiplier 18) Fig 2.18 [4:2] compressor 19) Fig 2.19 Gate-level carry-save adder 20) Fig 2.20 [4:2] compressors 21) Fig 2.21 Transmission gate [4:2] compressor 22) Fig 2.22 16 16 Booth-encoded multiplier floorplans 23) Fig 3.1 16-bit adder/subtractor design example

21

23 23 24 24 25 25 26 27 32

24) Fig 3.2 MAC Operational steps 25) Fig 3.3 basic building blocks for the multiplication circuit 26) Fig 4.1 Versatile Multimedia Functional Unit 27) Fig 4.2 Architecture of MAC 28) Fig 4.3 Radix-4 Booth Encoding 29) Fig.4.4 Grouping of bits from the multiplier term 30) Fig.4.5 Illustration of multiplication using modified Booth encoding 31) Fig.4.6 SPST equipped modified Booth encoder 32) Fig.4.7 Booth partial product selector logic 33) Fig.4.8 Booth partial products Generation 34) Fig.4.9 Booth single partial product selector logic 35) Fig.4.10 Booth Encoder 36) Fig.4.11 Booth Decoder 37) Fig 4.12 Truth table for MBE Scheme 38) Fig.5.1 Internal structure of an FPGA 39) Fig 5.2 4-input LUT based implementation of logic block 40) Fig 5.3 FPGA Design flow 41) Fig 5.4 FPGA Synthesis 42) Fig5.5 FPGA Translate 43) Fig 5.6 FPGA map 44) Fig 5.7 FPGA Place and route 45) Fig. 5.8 A simple digital circuit 46) Fig.5.9 Sequence of steps in conventional electronic circuit design 47) Fig6.1 Simulation result of Partial products Generators 48) Fig 6.2 Simulation result of Booth Encoder 49) Fig 6.3 Simulation result of Carry-Save Adder 50) Fig 6.4 Simulation result of Versatile Multimedia Functional Unit 51) Fig 6.5 Schematic with Basic Inputs and Output 52) Fig 6.6 Schematic of Booth Encoder with SPST Adder

35 38 40 41
44

44 46 46 47 47 48 49 49 49 51 52 53 54 55 56 56 61 62 63 64 65 66 69 69

LIST OF TABLES

Tables
Table2.1 Radix-4 modified Booth encoding values Table 2.2 Radix-8 modified Booth encoding values Table 2.3Radix-8 modified Booth encoding values Table2.4 Comparison of XOR levels in multiplier trees Table 4.1 Each encoded digit in the multiplier performs a certain operation on the multiplicand, X,

Page no
17 22 23 28 45