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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO.

6, JUNE 2013

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A High Step-Up Converter With a Voltage Multiplier Module for a Photovoltaic System
Kuo-Ching Tseng, Chi-Chih Huang, and Wei-Yuan Shih
AbstractA novel high step-up converter is proposed for a frontend photovoltaic system. Through a voltage multiplier module, an asymmetrical interleaved high step-up converter obtains high stepup gain without operating at an extreme duty ratio. The voltage multiplier module is composed of a conventional boost converter and coupled inductors. An extra conventional boost converter is integrated into the rst phase to achieve a considerably higher voltage conversion ratio. The two-phase conguration not only reduces the current stress through each power switch, but also constrains the input current ripple, which decreases the conduction losses of metaloxidesemiconductor eld-effect transistors (MOSFETs). In addition, the proposed converter functions as an active clamp circuit, which alleviates large voltage spikes across the power switches. Thus, the low-voltage-rated MOSFETs can be adopted for reductions of conduction losses and cost. Efciency improves because the energy stored in leakage inductances is recycled to the output terminal. Finally, the prototype circuit with a 40-V input voltage, 380-V output, and 1000- W output power is operated to verify its performance. The highest efciency is 96.8%. Index TermsBoostyback converter, high step-up, photovoltaic system, voltage multiplier module.

Fig. 1.

Typical photovoltaic system.

I. INTRODUCTION

ENEWABLE sources of energy are increasingly valued worldwide because of energy shortage and environmental contamination. Renewable energy systems generate low voltage output; thus, high step-up dc/dc converters are widely employed in many renewable energy applications, including fuel cells, wind power, and photovoltaic systems [1][8]. Among renewable energy systems, photovoltaic systems are expected to play an important role in future energy production [9][17]. Such systems transform light energy into electrical energy, and convert low voltage into high voltage via a step-up converter, which can convert energy into electricity using a grid-by-grid inverter or store energy into a battery set. Fig. 1 shows a typical photovoltaic system that consists of a solar module, a high stepup converter, a charge-discharge controller, a battery set, and an inverter. The high step-up converter performs importantly among the system because the system requires a sufciently high step-up conversion. Theoretically, conventional step-up converters, such as the boost converter and yback converter, cannot achieve a high

Fig. 2. High step-up techniques based on a classical boost converter. (a) Integrated ybackboost converter structure. (b) Interleaved boost converter with a voltage-lift capacitor structure.

Manuscript received May 14, 2012; revised July 30, 2012; accepted August 24, 2012. Date of current version December 7, 2012. Recommended for publication by Associate Editor R. Redl. The authors are with the Department of Electronic Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung 811, Taiwan (e-mail: jerry@nkfust.edu.tw; u0052809@nkfust.edu.tw; bit1417@hotmail.com). Digital Object Identier 10.1109/TPEL.2012.2217157

step-up conversion with high efciency because of the resistances of elements or leakage inductance. Thus, a modied boostyback converter was proposed [18][20], and many converters that use the coupled inductor for a considerably highvoltage conversion ratio were also proposed [21][25]. Despite these advances, conventional step-up converters with a single switch are unsuitable for high-power applications given an input large current ripple, which increases conduction losses. Thus, numerous interleaved structures and some asymmetrical interleaved structures are extensively used [26][33]. The current study also presents an asymmetrical interleaved converter for a high step-up and high-power application. Modifying a boostyback converter, shown in Fig. 2(a), is one of the simple approaches to achieving high step-up gain; this gain is realized via a coupled inductor. The performance of the converter is similar to an active-clamped yback converter; thus, the leakage energy is recovered to the output terminal [20]. An interleaved boost converter with a voltage-lift capacitor shown in Fig. 2(b) is highly similar to the conventional interleaved type.

0885-8993/$31.00 2012 IEEE

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Fig. 3.

(a) Proposed high step-up converter with a voltage multiplier module. (b) Equivalent circuit of the proposed converter.

It obtains extra voltage gain through the voltage-lift capacitor, and reduces the input current ripple, which is suitable for power factor correction (PFC) and high-power applications [34]. In this paper, an asymmetrical interleaved high step-up converter that combines the advantages of the aforementioned converters is proposed, which combined the advantages of both. In the voltage multiplier module of the proposed converter, the turns ratio of coupled inductors can be designed to extend voltage gain, and a voltage-lift capacitor offers an extra voltage conversion ratio. The advantages of the proposed converter are as follows: 1) the converter is characterized by a low input current ripple and low conduction losses, making it suitable for highpower applications; 2) the converter achieves the high step-up voltage gain that renewable energy systems require; 3) leakage energy is recycled and sent to the output terminal, and alleviates large voltage spikes on the main switch; 4) the main switch voltage stress of the converter is substantially lower than that of the output voltage; 5) low cost and high efciency are achieved by the low rD S (on) and low voltage rating of the power switching device. II. OPERATING PRINCIPLE DESCRIPTION The proposed high step-up converter with voltage multiplier module is shown in Fig. 3(a). A conventional boost converter and two coupled inductors are located in the voltage multiplier module, which is stacked on a boost converter to form an asymmetrical interleaved structure. Primary windings of the coupled inductors with Np turns are employed to decrease input current ripple, and secondary windings of the coupled inductors with Ns turns are connected in series to extend voltage gain. The turns ratios of the coupled inductors are the same. The coupling references of the inductors are denoted by . and in Fig. 3.

The equivalent circuit of the proposed converter is shown in Fig. 3(b), where Lm 1 and Lm 2 are the magnetizing inductors, Lk 1 and Lk 2 represent the leakage inductors, S1 and S2 denote the power switches, Cb is the voltage-lift capacitor, and n is dened as a turns ratio Ns /Np . The proposed converter operates in continuous conduction mode (CCM), and the duty cycles of the power switches during steady operation are interleaved with a 180 phase shift; the duty cycles are greater than 0.5. The key steady waveforms in one switching period of the proposed converter contain six modes, which are depicted in Fig. 4, and Fig. 5 shows the topological stages of the circuit. Mode 1 [t0 , t1 ]: At t=t0 , the power switches S1 and S2 are both turned ON. All of the diodes are reversed-biased. Magnetizing inductors Lm 1 and Lm 2 as well as leakage inductors Lk 1 and Lk 2 are linearly charged by the input voltage source Vin . Mode 2 [t1 , t2 ]: At t=t1 , the power switch S2 is switched OFF, thereby turning ON diodes D2 and D4 . The energy that magnetizing inductor Lm 2 has stored is transferred to the secondary side charging the output lter capacitor C3 . The input voltage source, magnetizing inductor Lm 2 , leakage inductor Lk 2 , and voltage-lift capacitor Cb release energy to the output lter capacitor C1 via diode D2 , thereby extending the voltage on C1 . Mode 3 [t2 , t3 ]: At t=t2 , diode D2 automatically switches OFF because the total energy of leakage inductor Lk 2 has been completely released to the output lter capacitor C1 . Magnetizing inductor Lm 2 transfers energy to the secondary side charging the output lter capacitor C3 via diode D4 until t3 . Mode 4 [t3 , t4 ]: At t=t3 , the power switch S2 is switched ON and all the diodes are turned OFF. The operating states of modes 1 and 4 are similar. Mode 5 [t4 , t5 ]: At t=t4 , the power switch S1 is switched OFF, which turns ON diodes D1 and D3 . The energy stored in magnetizing inductor Lm 1 is transferred to the secondary side charging the output lter capacitor C2 . The input voltage source

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3) voltage VC b , VC 1 , VC 2 , and VC 3 are considered to be constant because of innitely large capacitance. A. Voltage Gain The rst-phase converter can be regarded as a conventional boost converter; thus, voltage VC b can be derived from VC b = 1 Vin . 1D (1)

When switch S1 is turned ON and switch S2 is turned OFF, voltage VC 1 can be derived from VC 1 = 1 2 Vin + VC b = Vin . 1D 1D (2)

The output lter capacitors C2 and C3 are charged by energy transformation from the primary side. When S2 is in turn-on state and S1 is in turn-off state, VC 2 is equal to induced voltage of Ns 1 plus induced voltage of Ns 2 , and when S1 is in turn-on state and S2 is in turn-off state, VC 3 is also equal to induced voltage of Ns 1 plus induced voltage of Ns 2 . Thus, voltages Vc 2 and Vc 3 can be derived from VC 2 = VC 3 = n Vin 1+ D 1D = n Vin . 1D (3)

The output voltage can be derived from Vo = VC 1 + VC 2 + VC 3 = 2n + 2 Vin . 1D (4)

The voltage gain of the proposed converter is 2n + 2 Vo . = Vin 1D (5)

Equation (5) conrms that the proposed converter has a high step-up voltage gain without an extreme duty cycle. The curve of the voltage gain related to turns ratio n and duty cycle is shown in Fig. 6. When the duty cycle is merely 0.6, the voltage gain reaches 10 at a turns ratio n of 1; the voltage gain reaches 30 at a turns ratio n of 5.
Fig. 4. Steady waveforms of the proposed converter at CCM.

B. Voltage Stresses on Semiconductor Components The voltage ripples on the capacitors are ignored to simplify the voltage stress analyses of the components of the proposed converter. The voltage stresses on power switches S1 and S2 are derived from 1 Vin . (6) VS 1 = VS 2 = 1D The voltage stresses on the power switches S1 and S2 related to the output voltage Vo and the turns ratio n can be expressed as 2n + 1 Vin . (7) VS 1 = VS 2 = Vo 1D Equations (6) and (7) conrm that low-voltage-rated metal oxidesemiconductor eld-effect transistors (MOSFETs) with low RD S ON can be adopted for the proposed converter to reduce conduction losses and costs. This feature makes our

and magnetizing inductor Lm 1 release energy to voltage-lift capacitor Cb via diode D1 , which stores extra energy in Cb . Mode 6 [t5 , t0 ]: At t=t5 , diode D1 is automatically turned OFF because the total energy of leakage inductor Lk 1 has been completely released to voltage-lift capacitor Cb . Magnetizing inductor Lm 1 transfers energy to the secondary side charging the output lter capacitor C2 via diode D3 until t0 . III. STEADY-STATE ANALYSIS The transient characteristics of circuitry are disregarded to simplify the circuit performance analysis of the proposed converter in CCM, and some formulated assumptions are as follows: 1) all of the components in the proposed converter are ideal; 2) leakage inductors Lk 1 and Lk 2 are neglected;

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Fig. 5. Operating modes of the proposed converter. (a) Mode 1 [t0 , t1 ]. (b) Mode 2 [t1 , t2 ]. (c) Mode 3 [t2 , t3 ]. (d) Mode 4 [t3 , t4 ]. (e) Mode 5 [t4 , t5 ]. (f) Mode 6 [t5 , t0 ].

converter suitable for high step-up and high-power applications. The voltage stresses on the power switches account for half of output voltage Vo , even if turns ratio n is 0. The voltage stress on diode D1 is equal to VC 1 , and the voltage stress on diode D2 is voltage VC 1 minus voltage VC b .

These voltage stresses can be derived from 2 Vin 1D

VD 1 = VC 1 =

(8)

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Fig. 6.

Voltage gain versus turns ratio n and duty cycle.

VD 2 = VC 1 VC b =

1 Vin . 1D

(9)
Fig. 7. Voltage stresses on semiconductor components versus turns ratio n .

The voltage stresses on the diodes D1 and D2 related to the output voltage Vo and the turns ratio n can be expressed as VD 1 = Vo VD 2 2n Vin 1D 2n + 1 Vin . = Vo 1D (10) (11)

The voltage stresses on diodes D1 and D2 are close on power switches S1 and S2 . Although the voltage stress on diode D1 is larger, it accounts for only half of the output voltage Vo at a turns ratio n of 1. The voltage stresses on the diodes are lower as the voltage gain is extended by increasing turns ratio n. The voltage stresses on diodes D3 and D4 both equal the VC 2 plus VC 3 , which can be derived from VD 3 = VD 4 = 2n Vin . 1D (12)

The voltage stresses on the diodes D3 and D4 related to the output voltage Vo and the turns ratio n can be expressed as VD 3 = VD 4 = Vo 2 Vin . 1D (13)

Although the voltage stresses on the diodes D3 and D4 increase as the turns ratio n increases, the voltage stresses on the diodes D3 and D4 are always lower than the output voltage. The relationship between the voltage stresses on all the semiconductor components and the turns ratio n is illustrated in Fig. 7. C. Analysis of Conduction Losses Some conduction losses are caused by resistances of semiconductor components and coupled inductors. Thus, all the components in the proposed converter are not assumed to be ideal, except for all the capacitors. Diode reverse recovery problems, core losses, switching losses, and the ESR of capacitors are not discussed in this section. The characteristics of leakage inductors are disregarded because of energy recycling. The equivalent circuit, which includes the conduction losses of coupled inductors and semiconductor components, is shown in Fig. 8, in which

Fig. 8. Equivalent circuit including conduction losses of coupled inductors and semiconductor components.

rL 11 and rL 21 are the copper resistances of primary windings of the coupled inductor; rL 12 and rL 22 are the copper resistances of secondary windings of the coupled inductor; rD S 1 and rD S 2 denote the on-resistance of power switches; VD 1 , VD 2 , VD 3 , and VD 4 denote the forward biases of the diodes; and rD 1 , rD 2 , rD 3 , and rD 4 are the resistances of the diodes. Small-ripple approximation was used to calculate conduction losses. Thus, all currents that pass through components were approximated by the dc components. The magnetizing currents and capacitor voltages are assumed constant because of the innite values of magnetizing inductors and capacitors. Fig. 9

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In modes 1 and 3, both switches are turned OFF, and the average currents that pass through output lter capacitors C1 , C2 , and C3 are Vo . (24) Ro In mode 2, the average currents that pass through output lter capacitors C1 and C3 are IC 1 = IC 2 = IC 3 = IC 1 = ID 2
Fig. 9. PWM signal of S 1 and S 2 .

Vo Ro

(25)

shows the PWM signals of S1 and S2 . The equivalent operation states, including the four modes, are shown in Fig. 10. Mode 1 [0, (D0.5)]: In this mode, power switches S1 and S2 are turned ON, and diodes D1 , D2 , D3 , and D4 are turned OFF. The equivalent circuit is shown in Fig. 10(a), and the following equations can be derived: Vin = IL m 1 (rL 11 + rD S 1 ) + VL m 1 Vin = IL m 2 (rL 21 + rD S 2 ) + VL m 2 . (14) (15)

Vo . (26) Ro In mode 4, the average currents that pass through output lter capacitor C2 are as follows: IC 3 = ID 4 IC 2 = ID 3 Vo . Ro (27)

The average currents that pass through diodes D2 , D3 , and D4 can be derived from ID 2 = ID 3 = ID 4 = Vo . (1 D)Ro (28)

Mode 2 [(D0.5), 0.5]: In this mode, power switch S2 is turned OFF, and diodes D2 and D4 are turned ON. The equivalent circuit is shown in Fig. 10(b), and the following equations can be derived: Vin = (IL m 1 + nID 4 ) (rL 11 + rD S 1 ) + VL m 1 Vin = (IL m 2 nID 4 ) (rL 21 + rD 2 ) + VL m 2 + VD 2 VC b + VC 1 VC 3 = n(VL m 1 VL m 2 ) ID 4 (rL 21 + rL 22 + rD 4 ) VD 4 . (18) (17) (16)

In mode 2, IC b is equal to ID 2 ; in mode 4, IC b is equal to the negative of ID 1 . Thus, the average current that passes through diode D1 can be derived as follows: ID 1 = Vo . (1 D)Ro (n + 1)Vo . (1 D)Ro (n + 1)Vo . (1 D)Ro (29)

In mode 4, the average value of IL m 1 can be derived thus IL m 1 = ID 1 + nID 3 = (30)

In mode 2, the average value of IL m 2 can be derived by IL m 2 = ID 2 + nID 4 = (31)

Mode 3 [0.5, D]: This mode is similar to mode 1. The equivalent circuit is shown in Fig. 10(c), and the following equations can be derived: Vin = IL m 1 (rL 11 + rD S 1 ) + VL m 1 Vin = IL m 2 (rL 21 + rD S 2 ) + VL m 2 . (19) (20)

The voltage conversion ratio with conduction losses can be derived from
2 n +2 V1 (VD 1 + VD 2 + VD 3 + VD 4 ) Vo in = 1 D (1+ n 2 (2 D 1) r ) n ) 2 r X ]+ r Y X Vin 1+ + [(1+2 R o (1 D ) 2 R o (1 D )

(32)

where rX = rL 11 + rL 12 + rL 21 + rL 22 rY = rL 11 + rL 21 + 2(rL 22 + rL 12 ) + rD S 1 + rD S 2 + rD 1 + rD 2 + rD 3 + rD 4 .

Mode 4 [D, 1]: In this mode, power switch S1 is turned OFF, and diodes D1 and D3 are switched ON. The equivalent circuit is shown in Fig. 10(d), and the following equations can be derived: Vin = (IL m 2 + nID 3 ) rL 21 + VL m 2 + (IL m 1 + IL m 2 ) rD S 2 Vin = (IL m 1 nID 3 ) (rL 11 + rD 1 ) + VL m 1 + (IL m 1 + IL m 2 ) rD S 2 + VD 1 + VC b VC 2 = n(VL m 2 VL m 1 ) ID 3 (rL 21 + rL 22 + rD 3 ) VD 3 . (23) (22) (21)

Because the turns ratio and copper resistances of the secondary windings of the coupled inductors are directly proportional, the copper resistances of the coupled inductors can be expressed as rL 12 = n rL 11 ; 1 1 rL 22 = n rL 21 .

Efciency is expressed as follows: =


(1 D ) V i n (2 n +2) (VD 1 + VD 2 + VD 3 + VD 4 ) . ) 2 (2 D 1) r X n ) 2 r X ]+ r Y + (1+ n + [(1+2 R o (1 D ) 2 R o (1 D )

The average currents that pass through diodes D1 , D2 , D3 , and D4 can be derived by the capacitor charge balance.

(33)

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Fig. 10.

Equivalent operating modes with conduction losses states. (a) Mode 1 [0, (D 0.5)]. (b) Mode 2 [(D 0.5), 0.5]. (c) Mode 3 [0.5, D ]. (d) Mode 4 [D , 1].

On the basis of (33), we infer that the efciency will be higher if the input voltage is considerably higher than the summation of the forward bias of all the diodes, or if the load is substantially larger than the resistances of coupled inductors and semiconductor components. The calculated voltage gain and efciency with different copper resistances are shown in Fig. 11, and rL 11 and rL 21 are dened as rL . The other parameters in (33) are set as follows: 1) input voltage Vin : 40 V; 2) turns ratio n : 1; 3) load Ro : 200 4) on-resistances of switches rD S 1 and rD S 2 : 0.021 ; 5) resistances of diodes rD 1 , rD 2 , rD 3 , and rD 4 : 0.01 ; 6) forward bias of diodes VD 1 , VD 2 , VD 3 , and VD 4 : 1 V; 7) copper resistances of secondary windings of coupled inductors rL 12 and rL 22 =rL at a turns ratio n of 1. Fig. 11 reveals that efciency and voltage gain are affected by various coupled inductor winding resistors and duty cycle, and that efciency is decreased by the extreme duty ratio.

This section provides important information on voltage gain, voltage stresses on semiconductor components, and analysis of conduction losses, which indicates the relationship among duty cycle, turns ratio, and components. The proposed converter for each application can be designed on the basis of selected turns ratios, components, and other considerations.

D. Performance Comparison For demonstrating the performance of the proposed converter, the proposed converter is compared with other high step-up interleaved converters introduced in [30] and [33] as shown Table I. The high step-up interleaved converter introduced in [30] is also suitable as a candidate for high step-up, high-power conversion of the PV system, and the other high step-up interleaved converter introduced in [33], which is an asymmetrical interleaved structure as proposed converter is favorable for

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TABLE II CONVERTER COMPONENTS AND PARAMETERS

Fig. 11. Calculated voltage gain and efciency with different copper resistances.

TABLE I PERFORMANCE COMPARISON OF INTERLEAVED HIGH STEP-UP CONVERTERS

Fig. 12.

Control strategy for the proposed converter.

dc-microgrid applications. Both of converters use coupled inductor and voltage doubler to achieve high step-up conversion. For the proposed converter, the step-up gain is highest and the voltage stress on switch is the lowest, as converter introduced in [30]. Under the turns ratio n designed as less than 2, the highest voltage stress on diodes of the proposed converter is the lowest among the compared converters. In addition, the quantities of diodes are the least as converter introduced in [33]. Because the components of the proposed converter are the least among the compared converters, the reliability is higher and the cost is lower. Thus, the proposed converter is suitable for high step-up, high-power applications such as PV system.

IV. DESIGN AND EXPERIMENT OF THE PROPOSED CONVERTER A prototype of the proposed high step-up converter with a 40-V input voltage, 380-V output voltage, and maximum output power of 1 kW is tested. The switching frequency is 40 kHz, and the corresponding component parameters are listed in Table II for reference. The design consideration of the proposed converter includes components selection and coupled inductors design, which are based on the analysis presented in the previous section. In the proposed converter, the values of the primary leakage inductors of the coupled inductors are set as close as possible for current sharing performance. Due to the performances of high step-up

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Fig. 13. iD 2 .

Measured waveform at P o = 1 kW: (a) V g s 1 , V g s 2 , iL k 1 , and iL k 2 . (b) V d s 1 , V d s 2 , and iL s . (c) V g s 1 , V g s 2 , iD 1 , and iD 2 . (d) V g s 1 , V g s 2 , iD 1 , and

gain, the turns ratio n can be set 1 for the prototype circuit with a 40- V input voltage, 380- V output to reduce cost, volume, and conduction loss of winding. Thus, the copper resistances which affect efciency much can be decreased. The value of magnetizing inductors Lm 1 and Lm 2 can be design based on the equation of boundary operating condition, which is derived from Lm (critical) = D(1 D)2 Ro 2(n + 1)(2n + 2)fs (34)

where Lm (critical) is the value of magnetizing inductors at the boundary operating condition, fs is the switching frequency, and Ro is the load. How to suppress the voltage ripple on the voltage-lift capacitor Cb to an acceptable value is the main consideration. The equation versus the voltage ripple and the output power or output current can be derived by Cb = Po Io = Vo fs VC b fs VC b (35)

where Po is the output power, Vo is the output voltage, fs is the switching frequency, and VC b is the voltage ripple on the voltage-lift capacitor Cb . In control strategy, the proposed converter is controlled by the microchip dsPIC30F4011 as shown in Fig. 12. PV module and battery set are the main input power sources, which can be seen as an equivalent voltage source for the proposed converter, and the MPPT algorithm is employed by referring [35]. The battery management system (BMS) for the charge/discharge controller is not the main priority in this paper; thus, the related designed is not implemented in the paper. The output voltage is changed as load shift and the detected feedback signal is processed via proportional-integral controller, and the internal comparator generates interleaved PWM with

a 180 phase shift. Due to the insufcient voltage of PWM, the PWM is supported by TC4420 to control power switches, and EL50P1 is a Hall sensor to detect the input current for overcurrent protection (OCP). The input voltage Vi supplied by the PV module and battery set is very nearly 40 V even if the load shift. Thus, the efciency of the proposed converter under constant input voltage/constant output voltage can be measured. Fig. 13 illustrates the measured waveforms of Vg s 1 , Vg s 2 , iL k 1 , iL k 2 , Vds 1 , Vds 2 and iL s at Po = 1 kW. In Fig. 13(b), the switch voltage is clamped at 90 V, which is much smaller than the output voltage 380 V. Fig. 13(c) and (d) illustrate the measured waveforms of Vg s 1 , Vg s 2 , iD 1 , iD 2 , iD 3 , and iD 4 at Po = 1 kW. The measured waveforms are consistent with the steady-state analysis. Fig. 14 shows the simulation and experimental result of voltage on all capacitor to illustrate the high voltage storage and theoretical analysis. VC 1 is equal to VC b plus output voltage of boost converter, and VC b is equal to the output voltage of the boost converter. Thus, VC 1 is twice of VC b . VC 2 is equal to VC 3 ; both are nearly VC b because turns ratio n is set 1. Fig. 15(a) shows the input current ripple iin and the currents iL K 1 and iL K 2 of the primary side of the coupled inductors at Po = 1 kW. The peak-to-peak current ripple is about 2 A (6%), which conrms that the input current ripple is very low even if at high-power operation. Fig. 15(b) shows the dynamic response due to the step load variation between 100 and 500 W, and the output voltage is 380 V. Fig. 16 shows the measured efciency of the proposed converter. The maximum efciency is 96.8% at Po = 400 W. At maximum output power, the conversion efciency is about 96.1%. Fig. 17 shows the prototype photograph of the proposed converter.

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Fig. 14.

Simulation and experimental result of high-voltage storage of a capacitor: (a) simulation result (b) and experimental result.

Fig. 15. Performance of current sharing and dynamic response. (a) Input current ripple iL K 1 and iL K 2 at 1000 W. (b) Dynamic response under step load variation between 100 and 500 W.

V. CONCLUSION This paper has presented the topological principles, steadystate analysis, and experimental results for a proposed converter. The proposed converter has been successfully implemented in an efciently high step-up conversion without an extreme duty ratio and a number of turns ratios through the voltage multiplier module and voltage clamp feature. The interleaved PWM scheme reduces the currents that pass through each power switch and constrained the input current ripple by approximately 6%. The experimental results indicate that leakage energy is recycled through capacitor Cb to the output terminal. Meanwhile, the voltage stresses over the power switches are restricted and are much lower than the output voltage (380 V). These switches, conducted to low voltage rated and low on-state resistance MOSFET, can be selected. Furthermore, the full-load efciency is 96.1% at Po = 1000 W, and the highest efciency is 96.8% at Po = 400 W. Thus, the proposed converter is suitable for PV systems or other renewable energy applications that need high step-up high-power energy conversion.

Fig. 16.

Measured efciency of the proposed converter.

REFERENCES
[1] C. Hua, J. Lin, and C. Shen, Implementation of a DSP-controlled photovoltaic system with peak power tracking, IEEE Trans. Ind. Electron., vol. 45, no. 1, pp. 99107, Feb. 1998. [2] J. M. Carrasco, L. G. Franquelo, J. T. Bialasiewicz, E. Galvan, R. C. P. Guisado, M. A. M Prats, J. I. Leon, and N. Moreno-Alfonso, Power-electronic systems for the grid integration of renewable energy sources: A survey, IEEE Trans. Ind. Electron., vol. 53, no. 4, pp. 1002 1016, Jun. 2006.

Fig. 17.

Prototype photograph of the proposed converter.

TSENG et al.: HIGH STEP-UP CONVERTER WITH A VOLTAGE MULTIPLIER MODULE FOR A PHOTOVOLTAIC SYSTEM

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Wei-Yuan Shih was born in Kaohsiung, Taiwan, in 1984. He received the B.S. degrees from National Formosa University, Yunlin County, Taiwan, and the M.S. degree in electronics engineering from the National Kaohsiung First University of Science and Technology, Kaohsiung, in 2006 and 2011, respectively. He is currently an Electronic Engineer and working for Asiatree Technology Co., Ltd. His research interests include power electronics and energy conversion.