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ADC12DxxxxRF Family: Features and Performance

February 2013

Speaker bio: Marjorie Plisch


Marjorie Plisch is an applications engineer in the High Speed Signal Path Group since 2007. She received her BSEE from the University of Illinois, ChampaignUrbana in 2001, a MAPS degree from Multnomah University in 2005, and an MSEE degree from Oregon State University in 2007. Her interests include engineering education, testing and analysis of highspeed ADCs and high-speed ADC applications.

Outline
GSPS ADC Portfolio Overview and Architecture Applications Operating Modes and Features RF vs Non-RF 12-bit GSPS ADCs Key Performance Metrics Tools Overview Common Questions

Portfolio and Architecture Overview

TI GSPS ADC Portfolio

ADC12D2000/1800/1600/1000/800/500RF
RF Sampling ADCs w/ Industrys Largest Nyquist Zone
Configurable: 4.0/3.6/3.2/2.0/1.6/1.0 GSPS interleaved 2.0/1.8/1.6/1/0.8/0.5 GSPS dual ADC Excellent performance beyond 2.7 GHz Excellent performance beyond 11th Nyquist zone Noise floor: -154/-155/-154.6/-154/-152.2/-150.5dBm/Hz IMD3@2.7GHz: -65/-64/-70/-69/-71/-69 dBc Power: 4.6/4.4/4.0/3.5/2.5/2.0W AutoSync feature for multi-ADC applications* Pin-compatible w/ ADC12D1x00 & ADC10D1x00 RF-Sampling capability replaces entire IF- and ZIF-sampling subsystems of mixers, LO synthesizers, filters, amplifiers, and ADCs Industrys widest Nyquist zone of 2 GHz enables wideband software-defined radio (SDR) and allows combining multiple channels into one Reduction in board area, cost, and complexity Pin-compatible family allows range of resolution and speed-grade end-products

3G/4G basestation receive & DPD Microwave backhaul RF-Sampling, wideband SDR T&M (scopes, data acquisition, analyzers) EVM: ADC12D2000RFRB, ADC12D1800RFRB, ADC12D1600RFRB, ADC12D800RFRB

Block Diagram GSPS ADC


Block diagram for ADC12DxxxxRF

What architecture is used for the GSPS ADC family?

Key features: Dual channels or single, interleaved channel Internally terminated, buffered input impedance Option for output 1:2 demultiplexing 2x interleave per channel Exception is ADC12D800/500RF: 1x interleave per channel

Pipelined architecture
Often used for highspeed, medium-accuracy ADCs Theory of operation:
Determine MSB Subtract from Vin Amplify and determine LSB

Example shown is for a 2-stage, 8-bit ADC

Diagram is from Analog Integrated Circuit Design by Johns and Martin, 1997; Circuit Techniques for Low-voltage and High-speed A/D Converters by Waltari and Halonen, 2002.

Flash-based architectures
Basic Flash Architecture
Can achieve high sampling rates with low conversion latency Basic design requires 2N comparators and latches Drawbacks are high power consumption, die area

Flash ADC Implementation

What techniques can make a 12-bit 3.6 GSPS ADC practically realizable?
Folding and interpolating to improve power consumption, reduce area Folding-Interpolating Architecture
Diagrams are from Analog Integrated Circuit Design by Johns and Martin, 1997; Circuit Techniques for Low-voltage and High-speed A/D Converters by Waltari and Halonen, 2002.
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GSPS ADC Detailed Architecture


Architecture employs integrated techniques:
Folding Interpolating Pipelining

Additional techniques:
Calibration Interleaving Error Correction Only one bank is shown, i.e. no interleaving in this diagram
For more details on the GSPS ADC architecture, see A 1.8V 1.0Gsps 10b Self-Calibrating Unified-Folding-Interpolating ADC with 9.1 ENOB at Nyquist Frequency by R. Taft, et al. ISSCC 2009 / Session 4 / High-speed Data Converters.
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Applications

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Applications

Radar

Media Servers / STB

uWave Backhaul

Auto Radar Comms & SIGINT 3G/4G Basestation Data Acq.

Game Systems

FTTH

Test equipment

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Wireless Basestations
Replaces IF-Sampling

DSP

Old: IF-Sampling New: RF-Sampling Cost Area Time

DSP
RF ADC
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Time Domain Applications


Example Time Domain Applications Oscilloscopes RADAR Radio Detection And Ranging LIDAR/LADAR LIght/LAser Detection and Ranging Time of Flight Mass Spectrometry High Speed Digitizers Biotech, Semiconductors, Aerospace, Physics

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Features for Time Domain Applications


Key Features for Time Domain Applications DC coupled inputs Capacity to Synchronize Multiple Converters Adjustable Offset Adjustable Full Scale Range Adjustable Aperture Delay Support for Trigger Functionality

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Operating Modes and Features

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Operating Modes Inputs/Outputs

Input Mode Effective sample


rate, each stream Non-DES DES-I DES-Q DES-IQ DESCLK-IQ Fclk Fclk x 2 Fclk x 2 Fclk x 2 Fclk x 2

Sampled input (I or Q) Both, separately I Q Both, in parallel Both, in parallel

Effective Differential Input Impedance 100 Ohms 100 Ohms 100 Ohms 50 Ohms 50 Ohms DCLK Frequency Fclk/2 Fclk/4

Output Mode
Non-Demux 1:2 Demux

Data Update Rate Each Port Fclk Fclk/2

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Control Modes
Feature Control Mode Extended Control Mode DDR Clock Phase Power Down AC/DC Coupled Input Dual Channel / Interleaved Initiate Calibration Full Scale Range Offset LVDS Output Amplitude LVDS Output Common Mode 1:2 Demux/Non-Demux Yes Yes No Yes Yes 15 bits 12 bits + sign 1 bit No No Non-ECM (pin controlled) DDRPh PDI, PDQ Via Vcmo No CAL FSR (High/Low) No No Via Vbg NDM

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DES Timing Adjust


Interleaving the I- and Qchannels creates a spur at fs/2 fin in part from timing mismatch. The timing mismatch refers to the skew, not jitter. It has static and dynamic components. The Duty Cycle Correct feature addresses the dynamic component and is continuously running. DES Timing Adjust addresses the static component.
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Time Stamp
What does this feature do? Time Stamp captures another input signal than the analog input and converts it with the same total latency as the analog input signal. When Time Stamp is enabled, the DCLK_RST+/- inputs are commandeered as the Time Stamp input and the converted signal appears at the LSB of the ADC. Time Stamp is useful for applications which need to capture a trigger signal relative to the analog input signal.

How does it work?

For which applications is this feature useful?

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Read/Write Calibration Vectors


What happens during calibration?

Trim internal bias currents, analog input and clock Rin.


Why use this feature?

Saves startup time after system deployment, e.g. ADC12D1000RF: tCAL = 5.2 * 107 Sampling Clock Cycles = 52ms tREAD/WRITE = 240 SPI Write Cycles = 0.35ms Return to precisely same calibration vector, e.g. Rin.
When may this feature be used?

If the expected operating conditions, i.e. FSR, Temperature, DES/Non-DES Mode, Sampling Clock, are constant and result in a static calibration vector.

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AutoSync
What does this feature do? How does AutoSync function? Synchronize multiple ADCs in a system.
1. 2. 3. Align Sampling Clock to each ADC to align DCLK edge. Configure ADCs into Master or Slave. Reference Clock (RCLK) to each ADC aligns DCLK phase.

Why is AutoSync better than DCLK Reset?

RCLK generated by ADCs and configured in closed loop. AutoSync runs continuously and any errors can propagate out.

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RF versus non-RF 12-bit GSPS ADCs

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Available Products
Non-RF 12-bit ADCs RF 12-bit ADCs ADC12D500RF ADC12D800RF ADC12D1000 ADC12D1600 ADC12D1800 ADC12D1000RF ADC12D1600RF ADC12D1800RF ADC12D2000RF Decoder Ring: ADC ADC

12 Number of Bits

D Dual channel

1800 MSPS rate

RF Special tag

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Major Enhancements
ADC12Dxx00RF versus ADC12D1x00

Fewer interleaving spurs (ADC12D500/800RF only) New DES mode Noise improvement Linearity improvement

Fewer Interleaving Spurs


Single-Bank Mode (ADC12D500/800RF only) InI InQ
I1 I2 Q1 Q2
Interleave Interleave

OutI OutQ

Non-DES Spurs & Images Fixed spurs at fS/2 Images around fs/2

DES Spurs & Images Fixed spurs at fS/2, fS/4 Images around fs/2, fS/4

ADC12D1x00 InI InQ


I Q

OutI OutQ

No fixed spurs No images

Fixed spurs at fS/2 Images around fs/2

ADC12D500RF/800RF

New, Higher-fIN DES Mode


I Clk I DESI / DESQ Clk I DESIQ Clk I Clk Q

DESCLKIQ for Supporting Higher Input Frequencies

Non-DES

ADC1xD1x00 modes

NEW DESCLKIQ

Improves interleaved fIN range > 100%

Noise Floor Performance

Noise density

ADC12D1800 = -152.5 dBFS/Hz ADC12D1800RF = -154 dBFS/Hz ADC16DV160 = -157 dBFS/Hz

RF parts improve noise floor 1-2 dB versus previous 12-bit GSPS ADCs

Linearity Improvement of New RF Products


IMD3 @ 2.7 GHz input 6 9 dB improvement at 2.7 GHz

Linearity Improvement of New RF Products


IMD3 @ -7 dBFS Input Power

5-10 dB improvement over all frequencies

Key Performance Metrics

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Full-Power Bandwidth (FPBW)


As the frequency to the analog input of the ADC increases, so does the loss in signal level due to parasitic elements in the input network. The FPBW is traditionally the point at which this loss reaches 3dB. The ADC can be used beyond the 3dB point because the dynamic performance is still good, although the part must be driven harder. The FPBW is the same regardless of the Sampling Frequency because it is a function of the analog input.

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ADC12DxxxxRF excels at IMD3 performance

Noise Power Ratio Concept


Noise Power Ratio (NPR) is how quiet one unused channel in a wideband system remains when the other channels cause noise in it due to inter-modulation. In a wideband system and in conjunction with the Noise Floor measurement, it is more appropriate than a simple IMD test as a measurement of system performance.

RMS Noise Level [dB] Frequency fs/2

Product
NPR

NPR [dB] 50.7 50.4

ADC12D500RF ADC12D800RF

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Noise Spectral Density


NSD is measured in [dBm/Hz] in the interleaved (DES Mode). This is a more useful wideband metric because the noise in any channel bandwidth of interest may be calculated. NSD performance of RF ADCs is close to 16-bit ADCs
Product ADC12D500RF ADC12D800RF ADC12D1000RF ADC12D1600RF ADC12D1800RF ADC12D2000RF NSD [dBm/Hz] -150.5 -152.2 -154.0 -154.6 -155.0 -154.0

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Tools Overview

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ADC12DxxxxRF Reference Board (RB)


Additional required equipment: only a PC and clean input signal source On-board sampling clock or external clock External trigger function Pin control or ECM Hooks to use AutoSync FMC expansion header for larger data captures FPGA, schematic and layout source available
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Reference Board Hardware Kit


AC/DC adapter and power cord USB cable (4) 6 SMA cables (4) DC blocks (2) 50 terminators Low-Distortion Balun Board (400MHz 3GHz) Wide-Band Balun Board (4.5MHz 3GHz)

Kit is included with RB

Older reference boards may also include CD with software and reference documents

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Reference Board WaveVision5 Software


Time Domain, FFT, Histogram Read/Write Registers Dynamic Performance Metrics Save/Load Data Simultaneous I/Q data display

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Reference Board Common Pitfalls


Reported Issue
The software does not recognize the boards

Root Cause
The driver failed to install properly

Solution
Watch the Getting Started video Use a band-pass filter after the Signal Generator Turn Signal Generator OFF or remove cable when using INT CLK

The ADC output shows The Signal Generator very large harmonic tones outputs harmonic tones, which the ADC converts Performance issues when Insufficient isolation in switching between relay on RB to entirely INT/EXT Clock block EXT Clock

See the 10-minute video Getting Started with the GSPS ADC Reference Board online in the product folder for help with installing WaveVision5 software, board drivers, test bench setup, and product evaluation.
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Other Reference Board FAQ (1/2)


How can I drive the ADC in DESIQ Mode?
DESIQ Balun Board (TC1-DESIQ-SBB) Available for sale at Product Folder Boards tab $99 This board cannot be used to drive DESCLKIQ Mode

How much does the RB cost?


$999 for the ADC10D1500RB $999 for the ADC12D1800/1600RB $999 for the ADC12D800RFRB $999 for the ADC12D2000/1800/1600RFRB

Can I get extra balun boards? Yes!


ADC-WB-BB $49 ADC-LD-BB $49

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Other Reference Board FAQ (2/2)


How can I get more data than 32k samples off the Reference Board?
High pin-count FMC-connector on Reference Board creates two options: ADCRF2LA board interfaces to Agilent logic analyzer Other data capture and processing board with HPC FMC connector, such as the Xilinx ML605

Xilinx ML605 board


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Common Questions

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What is Max Allowed Input Signal Level?


Limits may be found in the Absolute Maximum and Operating Ratings sections of the datasheet. Required common-mode voltage must be maintained to ensure proper output codes. Operating Limits by Application:
DC-coupled
Range limit to each Vin+ and Vin- pin Differential Vin range limit by lifetime duty-cycle of part

AC-coupled
Max current limit Power limit (dBm)

Absolute Maximum Limits are absolute current and voltage limits.

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Why is the FPBW different by Mode?


The FPBW is a function of the analog input, not the sampling frequency. FPBW is influenced by routing and internal load

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Do I really need to calibrate?


It depends
Calibration is performed once when the ADC12DxxxxRF powers up. It is recommended to calibrate again when the operating conditions change significantly. Operating Condition Changed Full-scale Range Temperature Is calibration necessary? For large changes in FSR, yes. For Temperature < 20C, no. For larger changes, it is application dependent. Yes Yes Yes Yes

DES / Non-DES Mode AC / DC Coupled Mode Power-cycle I- or Q-channel Power supply

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Questions?

Thank you for attending! Any questions?


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