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Cornell University
ECE 4530: Analog Integrated Circuit Design
Fall 2013
Problem Set 1

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A B

(e) A B

2. Find the polar form of A and B and solve a through f in polar form. 3. For the circuit below:

Vout (s ) Vin

2 n 2 s2 +2n s+n

(b) Derive the impulse response (in the time domain) of the circuit above by taking the inverse fourier (or Laplace if you please) transform of the transfer function found above. This problem is harder, so you may want to do it last. Here are some hints to get you started Use the form given in part (a) as the starting point, so work with n and , not RLC 2 n Factor the denomiator and write in the form H (j ) = (jc1 , what are c1 )(j c2 ) and c2 Next take the inverse fourier transform. Notice something important about ? When 0 < < 1, the answer should be of form Aebt sin(ct)u(t), where u(t) is the unit step function. What about when = 1 or > 1? (extra credit) (c) Draw a Bode Plot of the Voltage transfer characteristic of this circuit (gain magnitude 1 L vs. frequency) and its phase. Draw one for R = , one for R = 2 , and one if R is C nite but R =

1 2 L . C

(d) is referred to as the damping coecent in these types of circuits What is the value of in this RLC circuit? What controls damping? What is being damped? What is n ? Which circuit elements controls that? (e) Sketch the step response of this circuit when = 0.1, = 1, and = 2. (No need to derive the expression here) Part II : Devices 1. Draw a top view and cross-sectional view of an NMOS transistor. Label all regions and indicate source, drain, gate and bulk as well as contact regions and type of doping (n or p). 2. Given an NMOS transistor as drawn below, how would you bias the gate, source, drain, and bulk relative to each other to ensure normal above threshold (strong inversion) operation?

3. Given an NMOS device with above threshold source drain current IDS = n Cox W 1 2 [(Vgs Vth )VDS VDS ] L 2

(a) Sketch a curve of IDS vs. Vgs if Vs = 0V = VBulk Dene and graphically show gm 2

(b) If we include channel length modulation and assume VDS Vgs Vth : W 1 IDS = n Cox (Vgs Vth )2 (1 + VDS ) 2 L Sketch a curve of IDS vs VDS if Vgs > Vth and = 0 Dene ro and show it graphically on your sketch. (c) Explain the body eect and how it eects Vth . Show how the curves in part a will change as VBulk is pulled below Vs . Part III: Circuits 1. Consider the dierential pair below:

(a) What are I1 and I2 as a function of Vin = V1 V2 and Ib (large signal expression). Find I = I2 I1 and sketch I1 , I2 , and I as a function of Vin . Assume Q1 and Q2 are saturated and matched. (b) Replace Q1 and Q2 with M1 and M2 , two NFETS, re-derive the expression for I2 I1 . Sketch I2 I1 vs Vin . Assume M1 , M2 saturated and matched. (c) Describe how the common source node changes for the circuit in bas V1 increases relative to V2 and as V1 decreases relative to V2 . 1. Consider the common source amplier below.

The curves for transistor M1 are shown below 1. IDS vs Vgs for VDS = VDD 2. IDS vs VDS for Vgs = 1V, 1.5V, 2V.

(a) What is the condition for the saturation of M1 if Vin = 2V (Voutmin = ?). What is the maximum value of R to maintain saturation? Assume VDD = 2.5V (b) If Vin(DC ) = 2V, and R = 5k , what is the maximum achievable current swing IDS to maintain saturation? (c) Assuming ro >> R, what is the small signal gain, A = you get this number from the curves for IDS .

Vout Vin

(d) Based of c, what is the allowable input swing to maintain M1 in saturation? (e) Draw a small signal model of this amplier at low frequency.

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