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Problems for MIPS

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Question 1

Write MIPS 64 code for next C fragments If (A == 200) B= 900;

Assume A, B, and i correspond to memory locations: 1000, 1500, and 2000, respectively

Answer 1

PART 1 LD LI BNE LI SD SKIP: PART 2 LD LD BNE LI BNE R1, 1000(R0) R2, 1500(R0) R1, R0, SKIP R3, #25 R2, R2, SKIP R1, 1000(R0) R2, #200 R1, R2, SKIP R3, #900 R3, 1500(R0)

PART 3

Question 2

Consider the following fragment of C code: For i=0; I<=100; i++( {A[i] = B[i] + C;} Assume that A and B are arrays of 64-bit integers, and C and I are 64-bit integers. Assume all data values and their addresses are kept in memory ( at locations 0, 5000, 1500, and 2000 for A, B, C, and I, respectively). Assume that values in registers are lost between iteration in the loop. Write MIPS64 code. How many instructions are required dynamically? How many memory-data references will be executed? What is the code size in bytes?

Answer 2

Program list will be as follow

Ex2-8 DADD R1, R0, R0 SW R1, 2000(R0) ; R0 =0; initialize i = 0 ; store i ; get value of i ; R2 = word offset of B[i] ; add base address of B to R2 ; load B[i] ; load C ; B[i] + C ; get value of i ; R2 = word offset of A[i]

Loop: LD R1, 2000(R0) DSLL R2, R1, #3 DADDI R3, R2, #5000 LD LD R4, 0(R3) R5, 1500(R0)

DADDI R7, R2, #0 SD R6, 0(R7) LD R1, 2000(R0) DADDI R1, R1, #1 SD R1, 2000(R0) LD R1, 2000(R0) DADDI R8, R1, #-101 BNEZ R8, loop

; add base address of A to R2 ; A[i] = B[i] + C ; get value of i ; increment i ; store i ; get value of i ; is counter at 101? ; if not 101 then repeat

Dynamic instructions = initialization instructions plus loop instructions times the number of iterations = 2 + (16 X 101) = 1618 Memory data reference is a count of load-store instructions = 0 + (8 X 101) = 808 Code size. Since MIPS instructions are 4 bytes in size then code size = 18 * 4 = 72 bytes

Question 3

Compute the effective CPI for MIPS using next Figure. Suppose we made the following measurements of average CPI for instructions: Instructions All ALU instructions Loads Stores Conditional branches Taken Not Taken Jumps Clock Cycles 1.0 1.4 ---2.0 1.5 1.2

Assume 60% of the conditional branches are taken. Assume other instructions not listed above as ALU. Average the instruction frequencies of gap and gcc to obtain the instruction mix?

Answer 3

WILL BE SOLVED IN LECTURE.

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