You are on page 1of 55


1.1 Introduction Microprocessor is a Central Processing Unit (CPU) etched on a single chip. A single Integrated Circuit (IC) has all the functional components of a CPU namely Arithmetic Logic Unit (ALU), Control Unit and registers. The ! " microprocessor is an #$it processor that includes on its chip most of the logic circuitry for performing computing tas%s and for communicating &ith peripherals. The architecture of a microprocessor is to $e learnt in terms of registers, memory addressing, addressing modes, instruction set, interfacing &ith memory and Input and 'utput (I(') de)ices and interrupt handling. It is necessary to learn a$out the a$o)e mentioned concepts to &rite efficient assem$ly language programs, and to design microprocessor $ased systems. This unit gi)es you an o)erall idea a$out the microprocessors, the detailed discussion a$out ! " architecture and interfacing of ! " &ith Programma$le Peripheral Interface (PPI) de)ices. 1.2 Learning O !ecti"e# To understand the $asics and e)olution of microprocessors To study a$out the functional components of ! " in detail To discuss the different types of memory addressing schemes !f ! " To learn the )arious addressing modes supported $y ! " To study the )arious types of instructions pro)ided $y ! " To study the pin diagram and the signals of )arious pins of ! " To discuss a$out the timing and e*ecution of instructions $y ! " To understand the interrupt handling of ! "

1.$ %unctiona& Co'(onent# o) a Micro(roce##or A digital computer is a programma$le machine specially designed for ma%ing computation. Its main components are+ CPU (Central Processing Unit), memory, input de)ice and output de)ice as sho&n in figure ,.,.




MEMORY -igure ,., .chematic /iagram of a /igital Computer A microcomputer is a small digital computer. The CPU of a microcomputer is a microprocessor. 'ther components are same as those of any other digital computer. In figure ,.,, if &e change the la$el CPU as Microprocessor, &e get the organi0ation of a microcomputer. The physical de)ices and circuitry of a computer are called hard&are. A physical de)ice may $e electronic, magnetic, mechanical or an optical de)ice etc. A se1uence of instructions to perform a particular tas% is called a program. A set of programs &ritten for a particular computer is %no&n as soft&are for that computer. The input and output de)ices are %no&n as peripherals. .ometimes the term peripheral also includes memory. Programs are su$routines stored in 2'M (2ead 'nly Memory)s, Programma$le 2'M (P2'M)s, 3rasa$le P2'M(3P2'M)s and(or 33P2'Ms are %no&n as firm&are. The commonly a)aila$le firm&ares are+ monitors, microprograms, su$routines for input and output de)ices. The Central Processing Unit (CPU) fetches instructions from the memory and performs specified tas%s. It stores results in the memory or sends results to the output de)ice according to the instructions gi)en in the program. The CPU controls and communicates &ith memory and input(output de)ices. Under the control of the CPU, programs and data are stored in the memory and displayed on Cathode 2ay Tu$e (C2T). The schematic diagram of a CPU is sho&n in figure ,.4. ALU ACCUMULATOR GENERAL AND SPECIAL PURPOSE REGISTERS TIMING AND CONTROL UNIT

-igure ,.4 .chematic /iagram of a CPU or a Microprocessor

The CPU of a large computer is implemented on one or more circuit $oards. ICs are used as its components. 2ecent practice is to use microprocessors to perform different functions &ithin the CPU of a large computer. The ma5or sections of a CPU are Arithmetic and Logic Unit (ALU), Accumulator, 6eneral and .pecial purpose registers and Timing and Control Unit. The function of an ALU is to perform arithmetic operations such as addition and su$traction7 and logical operations such as A8/, '2 and 39CLU.I:3#'2. Timing and control unit controls the entire operations of a computer. It acts as a $rain. It also controls all other de)ices connected to the CPU. It generates timing signals necessary for input and output de)ices. The accumulator is a register, &hich contains one of the operands and stores results of most arithmetic and logical operations. 6eneral purpose registers are used for temporary storage of data and intermediate results &hile computer is ma%ing e*ecution of a program. .pecial purpose registers are used $y the microprocessor itself. .ome of them are not accessi$le to programmers. 3*amples of special purpose registers are program counter, stac% pointer, instruction register and status register. The memory is a storage de)ice. It stores program, data, results etc. The computer recei)es data and instructions through input de)ices. An input de)ice con)erts instructions, input data and signals into proper $inary form suita$le for a digital computer. A %ey#$oard and simple s&itches are used as input de)ices. The user enters instructions and data through a %ey#$oard or simple s&itches. Computers are also used to measure and control physical 1uantities li%e temperature, pressure, speed, position etc. -or these purposes transducers are used to con)ert physical 1uantities into proportional electrical signals. A(/ con)erters are used to con)ert analog electrical signals into digital signals, &hich are sent to the computer. Transducers and sensors, data ac1uisition system etc. are also included in input de)ices. A(/ con)erter forms a part of data ac1uisition system. The computer sends results to output de)ices. An output de)ice may store, print, display or send electrical signal to control(actuate certain e1uipment. The e*amples of simple output de)ices are printers, C2T, L3/s, /(A con)erter, controllers, actuators etc. .ometimes input and output de)ices may $e com$ined in a single unit, &hich acts as $oth an input as &ell as an output de)ice. A %ey$oard and C2T are com$ined to form a )ideo terminal, &hich is a common I(' de)ice for human interaction &ith a computer. ;ith the ad)ent of L.I and :L.I technology it $ecame possi$le to $uild the entire CPU on a single chip IC. A CPU $uilt into a single L.I(:L.I chip is called a microprocessor. A digital computer using microprocessor as its CPU is called a microcomputer. The term micro initiates its physical si0e7 not it<s computing po&er. Today the computing po&er of a po&erful microprocessor approaches that a CPU on earlier large computer. The main sections of a microprocessor are+ ALU, timing and control unit, accumulator, general purpose and special

purpose registers. In this su$5ect &e<ll study a$out t&o microprocessors namely Intel ! " ( #$it) and Intel ! = (,=#$it). *a"e +ou under#tood, ,. ;hat are the ma5or components of a digital computer> 4. ;hat are the functional components of a CPU> ?. ;hat is a microprocessor> 1.- E"o&ution o) Micro(roce##or# The first microprocessor &as introduced in ,@A, $y Intel Corporation, U...A. It &as a B#$it microprocessor, the Intel B!!B. The B!!B &as introduced on 8o)em$er ,", ,@A, and originally ran at a cloc% speed of ,! CD0 (,! ,!!! cycles per second, or 5ust o)er one#tenth a megahert0). The B!!B contained 4,?!! transistors and &as $uilt on a ,!#micron process. This means that each line, trace, or transistor could $e spaced a$out ,! microns (millionths of a meter) apart. /ata &as transferred B $its at a time, and the ma*imum addressa$le memory &as only =B! $ytes. The B!!B &as designed for use in a calculator $ut pro)ed to $e useful for many other functions $ecause of its inherent programma$ility. In ,@A4, Intel introduced the , st #$it processor, the Intel !! . The Intel !!B and !! $oth used Positi)e Channel Metal '*ide .emiconductor (PM'.) technology. In ,@A? a more po&erful and faster #$it processor, the Intel ! ! &as introduced. It employed 8egati)e Channel metal '*ide semiconductor (8M'.) technology. The !! processor contained ?,"!! transistors and &as $uilt on the same ,!#micron process as the pre)ious processor. The $ig change in the !! &as that it had an #$it data $us, &hich meant it could mo)e data $its at a time t&ice as much as the pre)ious chip. It could also address more memory, up to ,=CE. This chip &as primarily used in dum$ terminals and general#purpose calculators. The ne*t chip in the lineup &as the ! !, introduced in April ,@AB, running at a cloc% rate of 4MD0. /ue to mostly the faster cloc% rate, the ! ! processor had ,! times the performance of the !! . The ! ! chip contained =,!!! transistors and &as $uilt on a =#micron process. .imilar to the pre)ious chip, the ! ! had an #$it data $us, so it could transfer $its of data at a time. The ! ! could address up to =BCE of memory, significantly more than the pre)ious chip. It &as the ! ! that helped start the PC re)olution $ecause this &as the processor chip used in &hat is generally regarded as the first personal computer, the Altair !!. The CP(M operating system &as &ritten for the ! ! chip, and Microsoft &as founded and deli)ered its first product+ Microsoft EA.IC for the Altair. These initial tools pro)ided the foundation for a re)olution in soft&are $ecause thousands of programs &ere &ritten to run on this platform. In fact, the ! ! $ecame so popular that it &as cloned. A company called Filog formed in late ,@A", 5oined $y se)eral e*#Intel ! ! engineers. In Guly ,@A=, it released the F# ! processor, &hich &as a )astly impro)ed )ersion of the ! !. It &as not pin

compati$le $ut instead com$ined functions such as the memory interface and 2AM refresh circuitry, &hich ena$led cheaper and simpler systems to $e designed. The F# ! also incorporated a superset of ! ! instructions, meaning it could run all ! ! programs. It also included ne& instructions and ne& internal registers, so soft&are designed for the F# ! &ould not necessarily run on the older ! !. The F# ! ran initially at 4."MD0 (later )ersions ran up to ,!MD0) and contained ,"!! transistors. The F# ! could access =BCE of memory. Intel released the ! ", it<s follo&#up to the ! !, in March ,@A=. 3)en though it predated the F# ! $y se)eral months, it ne)er achie)ed the popularity of the F# ! in personal computer systems. It &as popular as an em$edded controller, finding use in scales and other computeri0ed e1uipment. The ! " ran at "MD0 and contained =,"!! transistors. It &as $uilt on a ?#micron process and incorporated an #$it data $us. Along different architectural lines, M'. Technologies introduced the ="!4 in ,@A=. This chip &as designed $y se)eral e*#Motorola engineers &ho had &or%ed on MotorolaHs first processor, the = !!. The ="!4 &as an #$it processor li%e the ! !, $ut it sold for around I4", &hereas the ! ! cost a$out I?!! &hen it &as introduced. The price appealed to .te)e ;o0nia%, &ho placed the chip in his Apple I and Apple II designs. The chip &as also used in systems $y Commodore and other system manufacturers. The ="!4 and its successors &ere also used in game consoles, including the original 8intendo 3ntertainment .ystem (83.) among others. Motorola &ent on to create the = !!! series, &hich $ecame the $asis for the Apple Macintosh line of computers. Today those systems use the Po&erPC chip, also $y Motorola and a successor to the = !!! series. All these pre)ious chips set the stage for the first PC processors. Intel introduced the ! = in Gune ,@A . The ! = chip $rought &ith it the original * = instructions set that is still present in current * =#compati$le chips such as the Pentium B and AM/ Athlon. A dramatic impro)ement o)er the pre)ious chips, the ! = &as a full ,=#$it design &ith ,=#$it internal registers and a ,=#$it data $us. This meant that it could &or% on ,=#$it num$ers and data internally and also transfer ,= $its at a time in and out of the chip. The ! = contained 4@,!!! transistors and initially ran at up to "MD0. The chip also used 4!#$it addressing, so it could directly address up to ,ME of memory. Although not directly $ac%&ard compati$le &ith the ! !, the ! = instructions and language &ere )ery similar and ena$led older programs to 1uic%ly $e ported o)er to run. This later pro)ed important to help 5umpstart the PC soft&are re)olution &ith recycled CP(M ( ! !) soft&are. Although the ! = &as a great chip, it &as e*pensi)e at the time and more importantly re1uired e*pensi)e ,=#$it $oard designs and infrastructure to support it. To help $ring costs do&n, in ,@A@ Intel released &hat some called a crippled )ersion of the ! = called the ! . The ! processor used the same internal core as the ! =, had the same ,=#$it registers, and could address the same ,ME of memory, $ut the e*ternal data $us &as reduced to $its. This ena$led

support chips from the older #$it ! " to $e used, and far less e*pensi)e $oards and systems could $e made. These reasons are &hy IEM chose the ! instead of the ! = for the first PC. This decision &ould affect history in se)eral &ays. The ! &as fully soft&are compati$le &ith the ! =, so it could run ,=# $it soft&are. Also, $ecause the instruction set &as )ery similar to the pre)ious ! " and ! !, programs &ritten for those older chips could $e 1uic%ly and easily modified to run. This ena$led a large li$rary of programs to $e 1uic%ly released for the IEM PC, thus helping it $ecome a success. The o)er&helming $loc%$uster success of the IEM PC left in its &a%e the legacy of re1uiring $ac%&ard compati$ility &ith it. To maintain the momentum, Intel has pretty much $een forced to maintain $ac%&ard compati$ility &ith the ! ( ! = in most of the processors it has released since then. To date, $ac%&ard compati$ility has $een maintained, $ut inno)ating and adding ne& features has still $een possi$le. 'ne ma5or change in processors &as the mo)e from the ,=#$it internal architecture of the 4 = and earlier processors to the ?4#$it internal architecture of the ? = and later chips, &hich Intel calls IA#?4 (Intel Architecture, ?4#$it). IntelHs ?4#$it architecture dates to ,@ ", and it too% a full ,! years for $oth a partial ?4#$it mainstream '. (;indo&s @") as &ell as a full ?4# $it '. re1uiring ?4#$it dri)ers (;indo&s 8T) to surface, and another = years for the mainstream to shift to a fully ?4#$it en)ironment for the '. and dri)ers (;indo&s 9P). ThatHs a total of ,= years from the release of ?4#$it computing hard&are to the full adoption of ?4#$it computing in the mainstream &ith supporting soft&are. 8o& &e are in the midst of another ma5or architectural 5ump, as Intel and AM/ are in the process of mo)ing from ?4#$it to =B#$it computing for ser)ers, des%top PCs, and e)en porta$le PCs. Intel had introduced the IA#=B (Intel Architecture, =B#$it) in the form of the Itanium and Itanium 4 processors se)eral years earlier, $ut this standard &as something completely ne& and not an e*tension of the e*isting ?4#$it technology. IA#=B &as first announced in ,@@B as a CPU de)elopment pro5ect &ith Intel and DP (codenamed Merced), and the first technical details &ere made a)aila$le in 'cto$er ,@@A. The result &as the IA#=B architecture and Itanium chip, &hich &as officially released in 4!!,. The fact that the IA#=B architecture is not an e*tension of IA#?4 $ut is instead a &hole ne& and completely different architecture is fine for non#PC en)ironments such as ser)ers, $ut the PC mar%et has al&ays hinged on $ac%&ard compati$ility. 3)en though emulating IA#?4 &ithin IA#=B is possi$le, such emulation and support is slo&. ;ith the door no& open, AM/ sei0ed this opportunity to de)elop =B#$it e*tensions to IA#?4, &hich it calls AM/=B (originally %no&n as * =#=B). Intel e)entually released its o&n set of =B#$it e*tensions, &hich it calls 3M=BT or IA# ?4e mode. As it turns out, the Intel e*tensions are almost identical to the AM/ e*tensions, meaning they are soft&are compati$le. It seems for the first time that Intel has unargua$ly follo&ed AM/Hs lead in the de)elopment of PC architecture.

To ma%e =B#$it computing a reality, =B#$it operating systems and =B#$it dri)ers are also needed. Microsoft $egan pro)iding trial )ersions of ;indo&s 9P Professional *=B 3dition (&hich supports AM/=B and 3M=BT) in April 4!!", and ma5or computer )endors no& offer systems &ith ;indo&s 9P Professional *=B already installed. Ma5or hard&are )endors ha)e also de)eloped =B#$it dri)ers for current and recent hard&are. Linu* is also a)aila$le in =B#$itcompati$le )ersions, ma%ing the mo)e to =B#$it computing possi$le. The latest de)elopment is the introduction of dual#core processors from Intel, IEM, .un and AM/. /ual#core processors ha)e t&o full CPU cores operating off of one CPU pac%age in essence ena$ling a single processor to perform the &or% of t&o processors. Although dual#core processors donHt ma%e games (&hich use single e*ecution threads and are usually not run &ith other applications) play faster, dual#core processors, li%e multiple single#core processors, split up the &or%load caused $y running multiple applications at the same time. If youH)e e)er tried to scan for )iruses &hile chec%ing email or running another application, youH)e pro$a$ly seen ho& running multiple applications can $ring e)en the fastest processor to its %nees. ;ith dual#core processors a)aila$le from $oth Intel and AM/, your a$ility to get more &or% done in less time $y multitas%ing is greatly enhanced. Current dual#core processors also support AM/=B or 3M=BT =B#$it e*tensions, ena$ling you to en5oy $oth dual#core and =B#$it computingHs ad)antages. PCs ha)e certainly come a long &ay. The original ! processor used in the first PC contained 4@,!!! transistors and ran at B.AAMD0. The AM/ Athlon =B-9 has more than ,!" million transistors, &hile the Pentium B =A! (Prescott core) runs at ?. 6D0 and has ,=@ million transistors than%s to its 4ME L4 cache. /ual# core processors, &hich include t&o processor cores and cache memory in a single physical chip, ha)e e)en higher transistor counts+ The Intel Pentium / processor has 4?! million transistors, and the AM/ Athlon =B 94 includes o)er 4?? million transistors. As dual#core processors and large L4 caches continue to $e used in more and more designs, loo% for transistor counts and real#&orld performance to continue to increase. And the progress doesnHt stop there $ecause, according to MooreHs La&, processing speed and transistor counts are dou$ling e)ery ,."4 years. 1.5 INTEL 8085 Intel ! " is an #$it, 8#channel Metal '*ide semiconductor (8M'.) microprocessor. It is a B! pin IC pac%age fa$ricated on a single Large .cale Integration (L.I) chip. The Intel ! " uses a single J": /C supply for its operation. Its cloc% speed is a$out ?MD0. The cloc% cycle is of ?4! ns. The time for the cloc% cycle of the Intel ! " is 4!! ns. It has ! $asic instructions and 4B= opcodes. The ! " is an enhanced )ersion of its predecessor, the ! !A7 its instruction set is up&ard compati$le &ith that of the ! !A, meaning that ! " instruction set includes all the ! !A instructions plus some additional ones.

Programs &ritten for ! !A &ill $e e*ecuted $y ! ", $ut the ! " and ! !A are not pin compati$le. 1.5.1 .rc/itecture The architecture of Intel ! " consists of three main sections, arithmetic and logic unit, timing and control unit and se)eral registers. The functional $loc% diagram of ! " is sho&n in figure ,.?. These important sections are descri$ed in the su$se1uent sections. Arithmetic and Logic Unit (ALU) The ALU performs the follo&ing arithmetic and logical operations. ,. Addition 4. .u$traction ?. Logical A8/ B. Logical '2 ". Logical 39CLU.I:3 '2 =. Complement (logical 8'T) A. Increment (add ,) . /ecrement (su$tract ,) @. Left shift ,!. Clear The ALU is the unit that manipulates the data. ALU includes the accumulator, the temporary register, the arithmetic and logic circuits and flags.

-igure ,.? Architecture of ! " Timing and Control Unit The timing and control unit is a section of the CPU. It generates timing and control signals, &hich are necessary for the e*ecution of instructions. It controls data flo& $et&een CPU and peripherals (including memory). It pro)ides status, control and timing signals, &hich are re1uired for the operation of memory and I(' de)ices. It controls the entire operations of the microprocessor and peripherals connected to it. Dence you can understand that the control unit of the CPU acts as the $rain of a computer system. This unit synchroni0es all the microprocessor operations &ith the cloc% and generates the control signals necessary for communication $et&een the microprocessor and peripherals. 2egisters -igure ,.? sho&s the )arious registers of Intel ! ". 2egisters are used $y the microprocessor for temporary storage and manipulation of data and instructions. /ata remain in the register till they are sent to the memory or I(' de)ices. In a large computer the num$er of registers is more and hence the program re1uires less transfer of data to and from the memory. In a small computer the num$er of registers is small due to the limited si0e of the chip. If a digital computer re1uires fre1uent access to memory then the performance comes do&n due to the mismatch in the speed &ith &hich the CPU and the memory operate. The ! " programming model includes si* registers, one accumulator, and one flag register, as sho&n in -igure. In addition, it has t&o ,=#$it registers+ the stac% pointer and the program counter. They are descri$ed $riefly as follo&s. 6eneral Purpose 2egisters The ! " has si* general#purpose registers to store #$it data7 these are identified as E, C, /, 3, D, and L as sho&n in the figure ,.B. They can $e com$ined as register pairs # EC, /3, and DL # to perform some ,=#$it operations. The programmer can use these registers to store or copy data into the registers $y using data copy instructions. The DL register pair is also used to address memory locations. In other &ords, DL register pair plays the role of memory address register. Accumulator The accumulator is an #$it register that is a part of arithmetic(logic unit (ALU). This register is used to store #$it data and to perform arithmetic and logical

operations. The result of an operation is stored in the accumulator. The accumulator is also identified as register A. This is used during the e*ecution of a program for temporary storage. It holds one of the operands, &hich ser)es as one of the inputs to ALU. The other operand may $e either in the memory or in one of the registers. The final result of an arithmetic or logic operation is placed in the accumulator.

-igure ,.B 6eneral 2egisters 'ther 2egisters Program Counter This ,=#$it register deals &ith se1uencing the e*ecution of instructions. This register is a memory pointer. Memory locations ha)e ,=#$it addresses, and that is &hy this is a ,=#$it register. The microprocessor uses this register to se1uence the e*ecution of the instructions. The function of the program counter is to point to the memory address from &hich the ne*t $yte is to $e fetched. ;hen a $yte (machine code) is $eing fetched, the program counter is incremented $y one to point to the ne*t memory location. Do&e)er, please note that the program counter is loaded &ith some a$solute )alue during the e*ecution of $ranch instructions. .tac% Pointer The stac% pointer is also a ,=#$it register used as a memory pointer. It points to a memory location in 2(; memory, called the stac%. The $eginning of the stac% is


defined $y loading ,=#$it address in the stac% pointer. The stac% is the se1uence of memory locations defined $y the programmer. The stac% is used to sa)e the content of a register during the e*ecution of the program.


Instruction 2egister(/ecoder The instruction register and the decoder are considered as a part of the ALU. It is a temporary storage for the current instruction of a program. Latest instruction is sent here from memory prior to e*ecution. The decoder decodes the instruction and esta$lishes the se1uence of e)ents to follo&. Do&e)er, you please understand that the instruction register is not programma$le and can not $e accessed through any instruction. -lag 2egister The ALU includes fi)e flip#flops, &hich are set or reset after an operation according to data conditions of the result in the accumulator and other registers. They are called Fero (F), Carry (CK), .ign (.), Parity (P), and Au*iliary Carry (AC) flags7 their $it positions in the flag register are sho&n in the -igure $elo&. The most commonly used flags are Fero, Carry, and .ign. The microprocessor uses these flags to test data conditions. The flag register is sho&n in figure ,.".

-igure ,." -lag 2egister of ! " -or e*ample, after an addition of t&o num$ers, if the sum in the accumulator id larger than eight $its, the flip#flop uses to indicate a carry ## called the Carry flag (CK) L is set to one. ;hen an arithmetic operation results in 0ero, the flip#flop called the Fero (F) flag is set to one. The first -igure sho&s an #$it register, called the flag register, ad5acent to the accumulator. Do&e)er, it is not used as a register7 fi)e $it positions out of eight are used to store the outputs of the fi)e flip# flops. The flags are stored in the #$it register so that the programmer can e*amine these flags (data conditions) $y accessing the register through an instruction. These flags ha)e critical importance in the decision#ma%ing process of the microprocessor. The conditions (set or reset) of the flags are tested through the soft&are instructions. -or e*ample, the instruction GC (Gump on Carry) is implemented to change the se1uence of a program &hen CK flag is set. The thorough understanding of flag is essential in &riting assem$ly language programs. The com$ination of the flag register and the accumulator is called Program .tatus ;ord (P.;) and P.; is the ,=#$it unit for stac% operation. 1.5.2 Pro(ertie# and Pin de#cri(tion 12

Properties .ingle J ": .upply B :ectored Interrupts ('ne is 8on Mas%a$le) .erial In(.erial 'ut Port /ecimal, Einary, and /ou$le Precision Arithmetic /irect Addressing Capa$ility to =BC $ytes of memory The Intel ! " is a ne& generation, complete $it parallel central processing unit (CPU). The ! " uses a multiple*ed data $us. The address is split $et&een the $it address $us and the $it data $us.

Pin /escription -igure ,.= sho&s the pin diagram of ! ". The follo&ing descri$es the function of each pin+ A # A," ('utput ? .tate) Address Eus7 The most significant $its of the memory address or the the I(! address,? stated during Dold and Dalt modes.

$its of

A/! # A (Input('utput ?state) Multiple*ed Address(/ata Eus7 Lo&er $its of the memory address (or I(! addresses) appear on the $us during the first cloc% cycle of a machine state. It then $ecomes the data $us during the second and third cloc% cycles. ? stated during Dold and Dalt modes. AL3 ('utput) Address Latch 3na$le+ It occurs during the first cloc% cycle of a machine state and ena$les the address to get latched into the on chip latch of peripherals. The falling edge of AL3 is set to guarantee setup and hold times for the address information. AL3 can also $e used to stro$e the status information. AL3 is ne)er ?stated.


.', ., ('utput) /ata Eus .tatus. 3ncoded status of the $us cycle+ ., .! ! ! DALT ! , ;2IT3 , ! 23A/ , , -3TCD ., can $e used as an ad)anced 2(; status. 2/ ('utput ?state) 23A/7 indicates the selected memory or ,(! de)ice is to $e read and that the /ata Eus is a)aila$le for the data transfer. ;2 ('utput ?state) ;2IT37 indicates the data on the /ata Eus is to $e &ritten into the selected memory or ,(! location. /ata is set up at the trailing edge of ;2. ?stated during Dold and Dalt modes. 23A/K (Input) If 2eady is high during a read or &rite cycle, it indicates that the memory or peripheral is ready to send or recei)e data. If 2eady is lo&, the CPU &ill &ait for 2eady to go high $efore completing the read or &rite cycle. D'L/ (Input) D'L/7 indicates that another Master is re1uesting the use of the Address and /ata Euses. The CPU, upon recei)ing the Dold re1uest. &ill relin1uish the use of $uses as soon as the completion of the current machine cycle. Internal processing can continue. The processor can regain the $uses only after the Dold is remo)ed. ;hen the Dold is ac%no&ledged, the Address, /ata, 2/, ;2, and I'(M lines are ?stated. DL/A ('utput) D'L/ ACC8';L3/637 indicates that the CPU has recei)ed the Dold re1uest and that it &ill relin1uish the $uses in the ne*t cloc% cycle. DL/A goes lo& after the Dold re1uest is remo)ed. The CPU ta%es the $uses one half cloc% cycles after DL/A goes lo&. I8T2 (Input) I8T322UPT 23MU3.T7 is used as a general purpose interrupt. It is sampled only during the ne*t to the last cloc% cycle of the instruction. If it is acti)e, the Program Counter (PC) &ill $e inhi$ited from incrementing and an I8TA &ill $e issued. /uring this cycle a 23.TA2T or CALL instruction can $e inserted to 5ump to the interrupt ser)ice routine. The I8T2 is ena$led and disa$led $y soft&are. It is disa$led $y 2eset and immediately after an interrupt is accepted.


I8TA ('utput) I8T322UPT ACC8';L3/637 is used instead of (and has the same timing as) 2/ during the Instruction cycle after an I8T2 is accepted. It can $e used to acti)ate the 4"@ Interrupt chip or some other interrupt port. 23.TA2T I8T322UPT.7 These three inputs ha)e the same timing as I8T2 e*cept they cause an internal 23.TA2T to $e automatically inserted. 2.T A." L Dighest Priority 2.T =." 2.T "." L Lo&est Priority The priority of these interrupts is ordered as sho&n a$o)e. These interrupts ha)e a higher priority than the I8T2. T2AP (Input) Trap interrupt is a nonmas%a$le restart interrupt. It is recogni0ed at the same time as I8T2. It is unaffected $y any mas% or Interrupt 3na$le. It has the highest priority of any interrupt. 23.3T I8 (Input) 2eset sets the Program Counter to 0ero and resets the Interrupt 3na$le and DL/A flip flops. 8one of the other flags or registers (e*cept the instruction register) is affected The CPU is held in the reset condition as long as 2eset is applied. 23.3T 'UT ('utput) Indicates CPlG is $eing reset. Can $e used as a system 23.3T. The signal is synchroni0ed to the processor cloc%. 9,, 94 (Input) Crystal or 2(C net&or% connections to set the internal cloc% generator 9, can also $e an e*ternal cloc% input instead of a crystal. The input fre1uency is di)ided $y 4 to gi)e the internal operating fre1uency. CLC ('utput) Cloc% 'utput for use as a system cloc% &hen a crystal or 2( C net&or% is used as an input to the CPU. The period of CLC is t&ice the 9,, 94 input period.


I'(M ('utput) I'(M indicates &hether the 2ead(;rite is to memory or l(' Tristated during Dold and Dalt modes. .I/ (Input) .erial input data line The data on this line is loaded into accumulator $it A &hene)er a 2IM instruction is e*ecuted. .'/ (output) .erial output data line. The output .'/ is set or reset as specified $y the .IM instruction. :cc J" )olt supply. :ss 6round 2eference. 1.5.$ %unctiona& De#cri(tion The ! " is a complete $it parallel central processor. It re1uires a single J" )olt supply. Its $asic cloc% speed is ? MD0 thus impro)ing on the present ! !Hs performance &ith higher system speed. Also it is designed to fit into a minimum system of three ICHs+ The CPU, a 2AM(I', and a 2'M or P2'M(I' chip. The functional description of ! " is sho&n in figure ,.A. Address Eus The ! " has eight signal lines, A,"#A , &hich are unidirectional and used as the high order address $us. Multiple*ed Address(/ata Eus The signal lines A/A#A/! are $idirectional. They ser)e a dual purpose. They are used as the lo&#order address $us as &ell as the data $us. In e*ecuting an instruction, during the earlier part of the cycle, these lines are used as the lo&# order address $us as &ell as the data $us. /uring the later part of the cycle, these lines are used as the data $us. Do&e)er the lo& order address $us can $e separated from these signals $y using a latch.


-igure ,.= ! " Pin /iagram Control and .tatus .ignals Address Latch 3na$le (AL3) is used to implement the multiple*ed address(data $us. The ! "A uses a multiple*ed /ata Eus. The address is split $et&een the higher $it address $us and the lo&er $it Address(/ata Eus. /uring the first cycle the address is sent out. The lo&er $its are latched into the peripherals $y the Address Latch 3na$le (AL3). /uring the rest of the machine cycle the /ata Eus is used for memory or l(' data. The ! "A pro)ides 2/, ;2, and I'(Memory signals for $us control. Along &ith I'(M, ., and .! can identify


)arious operations, $ut they are rarely used in small systems. The follo&ing ta$le sho&s the ! " machine cycle status and control signals. Machine Cycle 'pcode -etch Memory 2ead Memory ;rite I(' 2ead I(' ;rite Interrupt Ac%no&ledge Dalt Dold 2eset I'(M ! ! ! , , , F F F ., , , ! , ! , ! 9 9 .! , ! , ! , , ! 9 9 Control signals 2/N! 2/N! ;2N! 2/N! ;2N! I8TAN! 2/, ;2N0 and I8TAN, 2/, ;2N0 and I8TAN, 2/, ;2N0 and I8TAN,

Po&er .upply and Cloc% -re1uency The po&er supply and fre1uency signals are as follo&s+ :cc+ J": po&er supply :ss+ 6round 2eference 9,, 94+ A crystal (or 2C, LC net&or%) is connected at these t&o pins. The fre1uency is internally di)ided $y t&o7 therefore, to operate a system at ?MD0, the crystal should ha)e a fre1uency of = MD0. CLC ('UT) L Cloc% 'utput+ This signal can $e used as the system cloc% for other de)ices.

Interrupt and .erial l(' The ! "A has " interrupt inputs+ I8T2, 2.T".", 2.T=.", 2.T A.", and T2AP. I8T2 is identical in function to the ! ! I8T. 3ach of the three 23.TA2T inputs, ".", =.", A.", has a programma$le mas%. T2AP is also a 23.TA2T interrupt e*cept it is nonmas%a$le. The three 23.TA2T interrupts cause the internal e*ecution of 2.T (sa)ing the program counter in the stac% and $ranching to the 23.TA2T address) if the interrupts are ena$led and if the interrupt mas% is not set. The non#mas%a$le T2AP causes the internal e*ecution of a 2.T independent of the state of the interrupt ena$le or mas%s. The interrupts are arranged in a fi*ed priority that determines &hich interrupt is to $e recogni0ed if more than one is pending as follo&s+ T2AP highest priority, 2.T A.",


2.T =.", 2.T ".", I8T2 lo&est priority This priority scheme does not ta%e into account the priority of a routine that &as started $y a higher priority interrupt. 2.T "." can interrupt a 2.T A." routine if the interrupts &ere re#ena$led $efore the end of the 2.T A." routine. The T2AP interrupt is useful for catastrophic errors such as po&er failure or $us error. The T2AP input is recogni0ed 5ust as any other interrupt $ut has the highest priority. It is not affected $y any flag or mas%. The T2AP input is $oth edge and le)el sensiti)e. An Interrupt Ac%no&ledge signal (I8TA) is also pro)ided. Dold, 2eady, and all Interrupts are synchroni0ed. The ! "A also pro)ides serial input data (.I/) and serial output data (.'/) lines for simple serial interface.


-igure ,.A -unctional /escription .ystem Eus A typical digital system uses a num$er of $usses, collection of &ires, &hich transmit $inary num$ers, one $it per &ire. A typical microprocessor


communicates &ith memory and other de)ices (input and output) using three $usses+ Address Eus, /ata Eus and Control Eus. Address Eus 'ne &ire for each $it, therefore ,= $its N ,= &ires. Einary num$er carried alerts memory to Oopen< the designated location. A location is also called a $o* collo1uially. /ata ($inary) can then $e put in or ta%en out. The Address Eus consists of ,= &ires, therefore ,= $its. Its P&idthP is ,= $its. A ,= $it $inary num$er allo&s 4,= different num$ers, or ?4!!! different num$ers, i.e. !!!!!!!!!!!!!!!! up to ,,,,,,,,,,,,,,,,. Eecause memory consists of $o*es, each &ith a uni1ue address, the si0e of the address $us determines the si0e of memory, &hich can $e used. To communicate &ith memory, the microprocessor sends an address on the address $us, e.g. !!!!!!!!!!!!!!,, (? in decimal), to the memory. The memory then selects $o* num$er ? for reading or &riting data. Address $us is unidirectional, i.e. num$ers only sent from microprocessor to memory, not other &ay. /ata Eus /ata Eus carries Odata<, in $inary form, $et&een microprocessor and other e*ternal units, such as memory. Typical si0e is or ,= $its. It is important to note that si0e of the data $us is called the &ord length of the microprocessor. The performance or the data processing capacity of a microprocessor is determined $y si0e of the data $us. As the si0e of the data $us increases the processing capacity increases in proportion. The data $us of ! " consists of &ires. Therefore, 4 com$inations of $inary digits are possi$le. /ata $us used to transmit PdataP, i.e. information, results of arithmetic, etc, $et&een memory and the microprocessor. /ata $us is $i#directional. .i0e of the data $us determines &hat arithmetic can $e done. If only $its &ide then largest num$er is ,,,,,,,, (4"" in decimal). Therefore, larger num$er has to $e $ro%en do&n into chun%s of 4"". This slo&s the microprocessor. /ata $us also carries instructions from memory to the microprocessor. .i0e of the $us therefore limits the si0e of the instruction $rought from memory. Control Eus Control $us are )arious lines &hich ha)e specific functions for coordinating and controlling microprocessor operations. 3.g.+ 2ead(;rite(Acti)e Lo&) line, single $inary digit. Control &hether memory is $eing O&ritten to< (data stored in memory) or Oread from< (data ta%en out of memory) , N 2ead, ! N ;rite. May also include cloc% line(s) for timing(synchroni0ing, Ointerrupts<, Oreset< etc. Typically the microprocessor has ,! control lines. A microprocessor cannot function correctly &ithout these )ital control signals. The Control $us carries control signals partly unidirectional, partly $i#directional. Control signals are things li%e Pread or &riteP. This tells memory that &e are reading from a location, specified on the address


$us, or &riting to a location specified. :arious other signals are used to control and coordinate the operation of the system. Modern day microprocessors, li%e !? =, !B = ha)e much larger $usses. They ha)e typically ,= or ?4 $it $usses, &hich allo& larger num$er of instructions, more memory location, and faster arithmetic. The term O$us<, in relation to control signals, is confusing. These are not group of lines li%e address or data $uses $ut indi)idual lines that pro)ide a pulse to indicate a microprocessor operation. *a"e +ou under#tood, ,. 4. ?. B. ". =. A. . /efine the &ord length of a microprocessor. ;hat is the &ord length of Intel ! "> ;hat is the specialty of accumulator> .tate the general purpose registers of ! " and the com$ination in &hich they are used as ,=#$it registers. ;hat is the purpose of the flag register> Mention the )arious types of flags supported $y ! ". ;hat is the function of AL3 signal> ;hy address and data $uses are multiple*ed in ! ">

1.0 8085 1a#ed Microco'(uter The ! " $ased microcomputer includes de)ices such as the ! " microprocessor, input de)ice (%ey$oard), output de)ice (display) and other interfacing de)ices. The interfacing de)ices include latches, decoders and $uffers. -igure ,. sho&s the )arious parts of the ! " $ased microcomputer. The octal latch demultiple*es the $us A/A#A/! using the signal AL3, and the logic gates generate the necessary control signals. -igure ,. sho&s the demultiple*ed address $us, the data $us, and the four acti)e lo& control signals+ M3M2, M3M;, I'2 and I';. In addition, to increase the dri)ing capacity of the $uses, a unidirectional $us dri)er is used for the address $us and a $idirectional $us dri)er is used for the data $us. The ! " microprocessor is designed to e*ecute AB different instruction types. 3ach instruction has t&o parts+ operation code, %no&n as opcode, and operand. The opcode is a command such as Add, and the operand is an o$5ect to $e operated on, such as a $yte or the commands such as Add, and the operand is an o$5ect to $e operated on, such as a $yte or the contents of a register. .ome instructions are ,#$yte instructions and some are multi$yte instructions. ! " needs to perform )arious operations such as Memory 2ead(;rite and I' 2ead(;rite to e*ecute an instruction. Do&e)er, there is no direct relationship $et&een the num$er of $ytes in an instruction and the num$er of operations the ! " has to perform.


Easically, the microprocessor e*ternal communication functions can $e di)ided into three categories. ,. Memory 2ead and ;rite 4. I(' 2ead and ;rite ?. 2e1uest Ac%no&ledge These functions are further di)ided into )arious operations (machine cycles). 3ach instruction consists of one or more of these machine cycles, and each machine cycle is di)ided into T states. 1.0.1 O(code %etc/ Mac/ine c+c&e The first operation in any instruction is opcode fetch. The microprocessor needs to get (fetch) this machine code from the memory register &here it is stored $efore the microprocessor can $egin to e*ecute the instruction. The steps and the timing of data flo& &hen the instruction code !,!! ,,,, (B-D#M': C,A), stored in location 4!!"D, is $eing fetched. To fetch the $yte (B-D), the MPU needs to identify the memory location 4!!"D and ena$le the data flo& from memory. This is called fetch cycle. The data flo& is sho&n in figure ,.@ and figure ,.,! sho&s the timing of ho& a data $yte is transferred from memory to the MPU. .tep , The program counter places the ,=#$it memory address on the address $us. At T, the high#order memory address 4!D is placed on the address lines A,"#A , the lo&#order memory address !"D is placed on the $us A/A#A/! and the AL3 signal goes high. .imilarly the status signal I'(M goes lo&, indicating that this is a memory related operation. .tep 4 The control unit sends the control signal 2/ to ena$le the memory chip. The control signal 2/ is sent out during the cloc% period T4, thus ena$ling the memory chip. The 2/ signal is acti)e during t&o cloc% periods. .tep ? The $yte from the memory location is placed on the data $us. ;hen the memory is ena$led, the instruction $yte (B-D) is placed on the data $us A/A#A/! and transferred to the microprocessor. The 2/ signal causes B-D to $e placed on $us A/A#A/!, &hen 2/ goes high7 it causes the $us to go into high impedance. .tep B


The $yte is placed in the instruction decoder of the microprocessor, and the tas% is carried out according to the gi)en instruction. The machine code or the $yte (B-D) is decoded $y the instruction decoder, and the contents of the accumulator are copied into register C. The tas% is performed during the period TB.
8085 MPU A15 A7
L*(', ($ D#0u+(!-+#8 AD7 9 AD0

Bus D !"# $ Bu%%#

3!4,5O &# A&& #ss Bus

L$:5O &# A&& #ss Bus

A0 C,!S#+#'( D#'$& # C,!S#+#'( D#'$& # P$ ( S#+#'( D#'$& # P$ ( S#+#'( D#'$&#


M!' $- $'#ss$ 6MPU7



CS R./ M#0$ 1 RD /R

EN E)'$& #

2#1 B$* &

EN L*(',

LED D!s-+* 1

MEMR C$)( $+ L$4!' D7 D0 D*(* Bus Bus D !"# B!&! # '(!$)* + D*(* Bus



-igure ,.

! " $ased Microcomputer .ystem

D*(* Bus I)(# )*+ D*(* Bus

M#0$ 1


I)s( u'(!$) D#'$&#

B C D 3 SP PC 2005 E L


2004 2005 4;

C$)( $+ L$4!' RD

-igure ,.@ /ata -lo& 1.0.2 De'u&ti(&e2ing t/e u# .D34.D0 The Intel ! " is an #$it microprocessor. Its data $us is #$it &ide and hence, $its of data can $e transmitted in parallel form or to the microprocessor. The Intel ! " re1uires a ,=#$it &ide address $us as the memory addresses are of ,= $its. The most significant $its of the address are transmitted $y the address $us (A #A,"). The least significant $its of the address are transmitted $y address(data $us (A/A#A/!). The address(data $us transmits data and address information at different times. This is the $asic need for demultiple*ing the $us A/A#A/!. Kou understand clearly that Intel has follo&ed this approach to reduce the num$er of pins in the chip. -igure ,.,! sho&s that the address on the high# order $us (4!D) remains on the $us for three cloc% periods. Do&e)er, the lo&# order address (!"D) is lost after the first cloc% period. This address needs to $e


latched and used for identifying the memory address. If the $us A/Q#A/) is used to identify the memory location (4!!"D), the address &ill change to 4!B-D after the first cloc% period. -igure ,.,, sho&s a schematic that uses a latch and the AL3 signal to demultiple* the $us. The $us A/A#A/! is connected as the input to the latch ABL.?A?. The AL3 signal is connected to the ena$le (6) pin of the latch, and the 'utput control ('C) signal of the latch is grounded.

O-'$&# ;#(', T1 CL< T2 T3 T4

A15 A8
L$:5O &#


3!4,5O &# M#0$ 1 A&& #ss



053 M#0$ 1 A&& #ss

4;3 O-'$&#

S(*(us IO.M = 0> S0 = 1> S1 = 1 O-'$&# ;#(',


-igure ,.,! Timing /iagram



8085 M!' $- $'#ss$

A15 A14 A13 A12 A11 A10 A9 A8

D ;;




A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 Address D0

-igure ,.,, .chematic /iagram of Latching Lo&#'rder


-igure ,.,! sho&s that AL3 goes high during T,. ;hen the AL3 is high, the latch is transparent. This means that the output changes according to input data. /uring T,, the output of each of the latch is !"D. ;hen the AL3 goes lo&, the data $yte !"D is latched until the ne*t AL3 and the output of the latch represents the lo&#order address $us AA#A! after the latching operation. Intel has circum)ented the pro$lem of demultiple*ing the lo&#order $us $y designing special de)ices such as the ,"" (4"= $ytes of 2(; memory J I('s), &hich are compati$le &ith the ! " multiple*ed $us. These de)ices internally demultiple* the $us using the AL3 signal. After carefully e*amining figure ,.,!, &e can ma%e the follo&ing o$ser)ations. ,. The machine code B-D (!,!! ,!!!) is a one#$yte instruction that copies the contents of the accumulator into register C. 4. The ! " microprocessor re1uires one e*ternal operation L fetching a machine code from memory location 4!!"D. ?. The entire operation L fetching, decoding and e*ecuting L re1uires four cloc% periods.


Instruction cycle is defined as the time re1uired to complete the e*ecution of an instruction. The ! " instruction cycle consists of one to si* machine cycles or do one to si* operations. Machine cycle is defined as the time re1uired to complete one operation of accessing memory, I(', or ac%no&ledging an e*ternal re1uest. This cycle may consists of three to si* T#states. T#state is defined as one su$di)ision of the operation performed in one cloc% period. These su$di)isions are internal states synchroni0ed &ith the system cloc%, and each T state is precisely e1ual to one cloc% period. The terms T#state and cloc% period are used synonymously.

-igure ,.,! sho&s the 2/ (2ead) as a control signal. Eecause this signal is used for $oth reading memory and for reading a input de)ice, it is necessary to generate t&o different 2ead signals+ one for memory and another for input. .imilarly t&o separate ;rite signals must $e generated. -igure ,.,4 sho&s that four different control signals are generated $y com$ining the signals 2/, ;2 and I'(M. The signal I'(M goes lo& for the memory operation. This signal is A8/ed &ith 2/ and ;2 signals $y using the ABL.?4 1uadruple t&o#input '2 gates as sho&n in figure ,.,4. The '2 gates are functionally connected as negati)e 8A8/ gates. ;hen $oth input signals go lo&, the outputs of the gates go lo& and generate M3M2 (Memory 2ead) and M3M; (Memory ;rite) control signals. ;hen the I'(M signal goes high, it indicates the peripheral I(' operation. -igure ,.,4 sho&s that this signal is complemented using the De* in)erter ABL.!B and A8/ed &ith the 2/ and ;2 signals. To demultiple* the $us and to generate the necessary control signals, the ! " microprocessor re1uires a latch and logic gates to $uild the MPU, as sho&n in figure ,.,4. The MPU can $e interfaced &ith any memory or I('. To illustrate the Memory 2ead machine cycle, &e need to e*amine the e*ecution of a 4#$yte or a ?#$yte instruction $ecause in a ,#$yte instruction the machine code is an opcode7 therefore the operation is al&ays an opcode fetch. T&o machine codes L !!,, !,,, (?3D) and !!,, !!,! (?4D) L are stored in memory locations 4!!!D and 4!!,D, respecti)ely as sho&n $elo&. The first machine code (?3D) represents the opcode to load a data $yte in the accumulator, and the second code (?4D) represents the data $yte to $e loaded in the accumulator. Instruction Memory Location M:I A,?4D7 Load $yte ?4D in the accumulator 4!!!D !!,, ,,,! ?3D 4!!,D !!,, !!,! ?4D


8085 IO.M 6M A'(!"# L$: RD 6A'(!"# L$:7 /R 6A'(!"# L$:7 MEMR 6A'(!"# L$:7

MEM/ 6A'(!"# L$:7

IOR 6A'(!"# L$:7

IO/ 6A'(!"# L$:7

-igure ,.,4 .chematic to generate control signals for memory This instruction consists of t&o $ytes. The first is the opcode and the second is the data $yte. The ! " needs to read these $ytes first from memory and thus re1uires at least t&o machine cycles. The first machine cycle is 'pcode -etch and the second machine cycle is Memory 2ead, as sho&n in figure ,.,?. This instruction re1uires se)en T#states for these t&o machine cycles. The timings of the machine cycles are descri$ed in the follo&ing paragraphs. ,. The first machine cycle M, is for opcode fetch. At T,, the microprocessor identifies that it is an 'pcode -etch cycle $y placing !,, on the status signals (I'(MN!, .,N,). It places the memory address (4!!!D) from the program counter on the address $us, 4!D on A,"#A , and !!D on A/A# A/! and increments the program counter to 4!!,D to point to the ne*t machine code. The AL3 signal goes high during T,, &hich is used to latch the lo& order address !!D from the $us A/A#A/!. At T4, the ! " asserts the 2d control signal, &hich ena$les the memory, and the memory places the $yte ?3D from location 4!!!D on the data $us. Then the ! " places the opcode in the instruction register and disa$les the 2/ signal. The fetch cycle is completed in state T?. /uring TB, the ! " decodes the 2/ signal. The fetch cycle is completed in state T?. /uring TB, the ! " decodes the opcode and finds out that a second $yte needs to $e read. After the T? state, the contents of the $us A,"#A are un%no&n, and the data $us A/A#A/! goes into high impedance. 29

M1 T1 CL< T2

O-'$&# ;#(', T3 T4 T1

M2 M#0$ 1 R#*& T2 T3

A15 A8
L$:5O &#


3!4,5O &# M#0$ 1 A&& #ss



3!4,5 O &# M#0$ 1 A&& #sss


003 M#0$ 1 A&& #ss

3E3 O-'$&#

M#0$ 1 A&& #ss

323 D*(*


IO.M S(*(us S1> S0 IO.M = 0> S0 = 1> S1 = 1 O-'$&# ;#(',

IO.M = 0>

S1 = 1>

S0 = 0



-igure ,.,? Timing for 3*ecution of the Instruction M:I A,?4D 4. After the completion of the 'pcode -etch cycle, the ! " places the address 4!!,D on the address $us and increments the program counter to the ne*t address 4!!4D. The second machine cycle M4 is identified as the Memory 2ead Cycle (I'(MN!, .,N,, .!N!) and the AL3 is asserted. At T4, the 2d signal $ecomes acti)e and ena$les the memory chip. ?. At the rising edge of T4, the ! " acti)ates the data $us as an input $us, memory places the data $yte ?4D on the data $us, and the ! " reads and stores the $yte in the accumulator during T?. *a"e +ou under#tood, ,. ;hat are the components of an ! " $ased microcomputer> 4. .tate the three categories of e*ternal communication functions of ! ".


?. ;hat are the )arious machine cycles in)ol)ed in the e*ecution of an instruction> B. ;hat is the usage of an octal latch in a ! " $ased microcomputer system> ". ;hat are the four control signals generated in a memory#mapped I('> 1.3 .ddre##ing Mode# It is o$)ious that each instruction re1uires certain data on &hich it has to operate. 8o& the issue is ho& to specify the operand so that the specified operation in the instruction is performed o)er the correct data. To impro)e the fle*i$ility in &riting the assem$ly language programs, the ! " MPU permits the programmers to specify the operands (data) in different &ays. These )arious &ays of specifying the operands or )arious formats for specifying the operands is called addressing mode. .ome possi$le techni1ues to specify data for the instructions are #$it or ,=#$it data may $e directly gi)en in the instruction itself. The address of the memory location, I(' port or I(' de)ice, &here data resides, may $e gi)en in the instruction itself. In some instructions only one register is specified. The content of the specified register is one of the operands. It is understood that the other operand is in the accumulator. .ome instructions specify one or t&o registers. The contents of the registers are the re1uired data. In some instructions data is implied. The most instructions of this type operate on the content of the accumulator.

/ue to different &ays of specifying data for instructions, the machine codes of all instructions are not of the same length. There are three types of Intel ! " instructions namely single#$yte instruction, t&o#$yte instruction and three#$yte instruction. The )arious &ays of specifying the operands for the instructions in ! " $elong to any one of the follo&ing address modes. ,. Implicit addressing 4. Immediate addressing ?. /irect addressing B. 2egister addressing ". 2egister indirect addressing Implicit addressing There are certain instructions &hich operate on the content of the accumulator. .uch instructions do not re1uire the address of the operand. Dere the content of the accumulator is the implied operand. 3*amples+ CMA L Complement the contents of accumulator 31

2AL L 2otate the contents of accumulator to the left through carry 22C L 2otate the contents of accumulator to the right In all of the a$o)e instructions the implied operand is the contents of the accumulator. In most of the arithmetic operations the content of the accumulator is one of the implied operands. -or e*ample in the arithmetic instruction A// E, register E is one operand and the other operand is accumulator (not specified, $ut implied). Immediate addressing In this addressing mode, &e specify the data (operand) in the instruction itself. In other &ords, the data is present in the instruction. These instructions do not re1uire the address of the operand. 3*amples+ M:I 2, !"D A/I !=D In the a$o)e instructions the data itself is specified in the instruction itself (!"D and !=D are data) /irect addressing In this mode of addressing, &e specify the address of the operand in the instruction. Please note that operand (data) itself is not specified as in immediate addressing mode. :ery often a $eginner gets confused $et&een immediate addressing and direct addressing. 3*amples+ .TA 4B!!D, I8 !4D In the instruction .TA 4B!!D, &e specify the address of the operand (4B!!D). 4B!!D is the memory location &here the data is present. In the instruction I8 !4D, &e specify the port address from &hich the data is to $e accepted. 2egister addressing In register addressing mode the operands are in the general purpose registers. The opcode specifies the address of the registers in addition to the operation to $e performed. In short, &e can say that data is pro)ided through the registers. 3*amples+ M': A, E A// E In the instruction M': A, E, the data is present in the register E and in instruction A// E7 E is the register &here the data is present. 2egister indirect addressing In this addressing mode, the memory location is specified $y the contents of the registers. Please note that in register addressing or register direct addressing,


registers ha)e the operands themsel)es &hereas in register indirect addressing mode registers ha)e only the address of the operand. 3*amples+ L/A9 E .TA9 / In the instruction L/A9 E, the register pair EC has the address of the location &here the data is present and in instruction the register pair /3 has the address of the location &here the data is to $e stored. Da)e you understood> ,. ;hat is meant $y an addressing mode> 4. ;hat is the necessity of ha)ing a )ariety of addressing modes> ?. In &hich addressing mode, the operand itself is specified in the instruction> B. 6i)e an e*ample for implied addressing mode. ". ;hat is the addressing mode follo&ed in the instruction L9I D, 4!"!D> 1.8 In#truction Set C&a##i)ication An instruction is a $inary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions, called the instruction set, determines &hat functions the microprocessor can perform. These instructions can $e classified into the follo&ing fi)e functional categories+ data transfer (copy) operations, arithmetic operations, logical operations, $ranching operations, and machine#control operations. /ata Transfer (Copy) 'perations This group of instructions copy data from a location called a source to another location called a destination, &ithout modifying the contents of the source. In technical manuals, the term data transfer is used for this copying function. Do&e)er, the term transfer is misleading7 it creates the impression that the contents of the source are destroyed &hen, in fact, the contents are retained &ithout any modification. The )arious types of data transfer (copy) are listed in figure ,.,B. Types ,. Eet&een 2egisters 3*amples ,. M': E,/ L Copy the contents of the register E into 2egister / 4. .pecific data $yte to a register or a 4. M:I E,?4D L Load register E &ith the memory location data $yte ?4D ?. Eet&een a memory location and a ?. L9I D, 4!!!D register M': E,M -rom a memory location 4!!!D to register E


B. Eet&een an I(' de)ice and the B. I8 !"D L The contents of the input accumulator port designated in the operand are read and loaded into the accumulator -igure ,.,B /ata Transfer Instructions Arithmetic 'perations These instructions perform arithmetic operations such as addition, su$traction, increment, and decrement. Addition # Any #$it num$er, or the contents of a register or the contents of a memory location can $e added to the contents of the accumulator and the sum is stored in the accumulator. 8o t&o other #$it registers can $e added directly (e.g., the contents of register E cannot $e added directly to the contents of the register C). The instruction /A/ is an e*ception7 it adds ,=#$it data directly in register pairs. 3*amples A// E A// M /A/ E L # L RAS T##### RASJRES RAS T##### RASJRRDLSS RDLS T##### RDLSJRECS

.u$traction # Any #$it num$er, or the contents of a register, or the contents of a memory location can $e su$tracted from the contents of the accumulator and the results stored in the accumulator. The su$traction is performed in 4Hs compliment, and the results if negati)e, are e*pressed in 4Hs complement. 8o t&o other registers can $e su$tracted directly. 3*amples .UE C .UI A=D .EE M L L L RAS T##### RASJRCS RAS T#### RAS#A=D RAS T##### RAS#RRDLSS#RCS

Increment(/ecrement # The #$it contents of a register or a memory location can $e incremented or decrement $y ,. .imilarly, the ,=#$it contents of a register pair (such as EC) can $e incremented or decrement $y ,. These increment and decrement operations differ from addition and su$traction in an important &ay7 i.e., they can $e performed in any one of the registers or in a memory location. 3*amples I82 E L I89 E RES T###### RESJ, L RECS T##### RECSJ,


/C2 M


Logical 'perations These instructions perform )arious logical operations &ith the contents of the accumulator. A8/, '2 3*clusi)e#'2 # Any #$it num$er, or the contents of a register, or of a memory location can $e logically A8/ed, '2ed, or 3*clusi)e#'2ed &ith the contents of the accumulator. The results are stored in the accumulator. 3*amples A8A C A8I "D '2A M 92A E L L L L RAS RAS RAS RAS T##### RAS U RCS T##### RAS U "D T##### RAS ) RRDLSS T###### RAS 9'2 RES

2otate# 3ach $it in the accumulator can $e shifted either left or right to the ne*t position. 3*amples 2LC RAnJ,S T##### RAnS RA!S T###### RAAS RC.S T##### RAAS 2A2 RAnS T###### RAnJ,S RC.S T###### RA!S RAAS T###### RC.S Compare# Any #$it num$er or the contents of a register, or a memory location can $e compared for e1uality, greater than, or less than, &ith the contents of the accumulator. 3*amples CMP 2 L The content of register r is su$tracted from the content of the accumulator and status flags are set according to the result of the su$traction. Eut the result is discarded. The content of the accumulator remains unchanged. CPI data L The second $yte of the instruction (data) is su$tracted from the contents of the accumulator and the status flags are set according to the result of su$traction. Eut the result is discarded. The content of the accumulator remains unchanged.


Complement # The contents of the accumulator can $e complemented. All !s are replaced $y ,s and all ,s are replaced $y !s. 3*amples CMA CMC L L RAS T#### RAS< RC.S T##### RC.S<

Eranching 'perations This group of instructions alters the se1uence of program e*ecution either conditionally or unconditionally. Gump # Conditional 5umps are an important aspect of the decision#ma%ing process in the programming. These instructions test for a certain conditions (e.g., Fero or Carry flag) and alter the program se1uence &hen the condition is met. In addition, the instruction set includes an instruction called unconditional 5ump. 3*amples GMP 4!"!D L GF ?,!!D L G8C B4"!D L RPCS T##### 4!"!D RPCS T##### ?,!!D if FN,, other&ise RPCS T##### RPCSJ, RPCS T##### B4"!D if CN!, other&ise RPCS T##### RPCSJ,

Call, 2eturn, and 2estart # These instructions change the se1uence of a program either $y calling a su$routine or returning from a su$routine. The conditional Call and 2eturn instructions also can test condition flags.


3*amples CALL Addr RR.PS#,S T####### RPCDS RR.PS#,S T####### RPCLS R.PS T##### R.PS#4 RPCS T##### Addr CC # C8C # CF # Call su$routine, if carry status C.N, Call su$routine if carry status C.N! Call su$routine if the 0ero status FN,

23T RPCLS T###### RR.PSS RPCDS T###### RR.PSJ,S R.PS T###### R.PSJ4 2C # 28C # 2F # 2eturn from su$routine if carry status C.N, 2eturn from su$routine if carry status C.N! 2eturn from su$routine if 0ero status FN!

Machine Control 'perations These instructions control machine functions such as Dalt, Interrupt, or do nothing. 3*amples DLT 8'P The microprocessor operations related to data manipulation can $e summari0ed in four functions+ ,. Copying data 4. Performing arithmetic operations ?. Performing logical operations B. Testing for a gi)en condition and alerting the program se1uence The follo&ing o$ser)ations may help you to understand the instruction set of ! " in a $etter &ay. ,. In data transfer, the contents of the source are not destroyed7 only the contents of the destination are changed. The data copy instructions do not affect the flags. 4. Arithmetic and Logical operations are performed &ith the contents of the accumulator, and the results are stored in the accumulator (&ith some e*pectations). The flags are affected according to the results.


?. Any register including the memory can $e used for increment and decrement. B. A program se1uence can $e changed either conditionally or $y testing for a gi)en data condition. *a"e +ou under#tood, ,. ;hether the content of the source is changed in a data transfer instruction> 4. In the arithmetic instruction A// E, the content of register E is added to &hich register> ?. ;hich logical instruction can $e used to clear the contents of the accumulator> B. Do& does the Program Counter register is updated &hile e*ecuting a conditional 5ump instruction> ". List do&n the )arious rotate instructions supported $y ! ". 1.5 In#truction %or'at An instruction is a command to the microprocessor to perform a gi)en tas% on a specified data. 3ach instruction has t&o parts+ one is tas% to $e performed, called the operation code (opcode), and the second is the data to $e operated on, called the operand. The operand (or data) can $e specified in )arious &ays. It may include #$it (or ,=#$it) data, an internal register, a memory location, or #$it (or ,=#$it) address. In some instructions, the operand is implicit. Instruction &ord si0e The ! " instruction set is classified into the follo&ing three groups according to &ord si0e+ ,. 'ne#&ord or ,#$yte instructions 4. T&o#&ord or 4#$yte instructions ?. Three#&ord or ?#$yte instructions In the ! ", P$yteP and P&ordP are synonymous $ecause it is an #$it microprocessor. Do&e)er, instructions are commonly referred to in terms of $ytes rather than &ords. 'ne#Eyte Instructions A ,#$yte instruction includes the opcode and operand in the same $yte. 'perand(s) are internal register and are coded into the instruction.


These instructions are ,#$yte instructions performing three different tas%s. In the first instruction, $oth operand registers are specified. In the second instruction, the operand E is specified and the accumulator is assumed. .imilarly, in the third instruction, the accumulator is assumed to $e the implicit operand. These instructions are stored in # $it $inary format in memory7 each re1uires one memory location. M': rd, rs rd T## rs copies contents of rs into rd. Coded as !, ddd sss &here ddd is a code for one of the A general registers &hich is the destination of the data, sss is the code of the source register. 3*ample+ M': A,E Coded as !,,,,!!! N A D N ,A! octal (octal &as used e*tensi)ely in instruction design of such processors). A// r A T## A J r 3*ample+ A// E Add the content of register r &ith accumulator

T&o#Eyte Instructions In a t&o#$yte instruction, the first $yte specifies the operation code and the second $yte specifies the operand. .ource operand is a data $yte immediately follo&ing the opcode. -or e*ample+

Assume that the data $yte is ?4D. The assem$ly language instruction is &ritten as


The instruction &ould re1uire t&o memory locations to store in memory. M:I r,data r T## data data is copied into the register r 3*ample+ M:I A,?!D coded as ?3D ?!D as t&o contiguous $ytes. This is an e*ample of immediate addressing. A/I data result is A T## A J data /ata is added &ith accumulator and the stored in accumulator Three#Eyte Instructions In a three#$yte instruction, the first $yte specifies the opcode, and the follo&ing t&o $ytes specify the ,=#$it address. 8ote that the second $yte is the lo&#order address and the third $yte is the high#order address. opcode J data $yte J data $yte -or e*ample+

This instruction &ould re1uire three memory locations to store in memory. Three $yte instructions # opcode J data $yte J data $yte L9I rp, data,= rp T## data,= ,= $it data is copied into the register pair rp rp is one of the pairs of registers EC, /3, DL used as ,=#$it registers 3*ample+ L9I D,!"4!D coded as 4,D 4!D "!D in three $ytes. This is also immediate addressing.


L/A addr

A T## (addr) Addr is a ,=#$it address in L D order.

3*ample+ L/A 4,?BD coded as ?AD ?BD 4,D. This is also an e*ample of direct addressing. *a"e +ou under#tood, ,. ;hat are the t&o parts of an instruction> 4. Do& many $ytes are in the he* code of the instruction M': A, E> ?. 6i)e e*amples for three $yte instructions. 1.10 6riting an .##e' &+ Language Progra' An assem$ly language program is a set of instructions &ithin the mnemonics of a gi)en microprocessor. These instructions are the commands to the microprocessor to $e e*ecuted in the gi)en se1uence to accomplish a tas%. 'ne should $e familiar &ith the programming model and the instruction set of the microprocessor for &hich the assem$ly language program is to $e de)eloped. ;e ha)e already e*plained the programming model (the set of general registers, accumulator, flags and pointer registers) and the instruction classification of ! ". The follo&ing steps are to $e follo&ed in &riting and e*ecuting an assem$ly language program. ,. /efine the pro$lem clearly and ma%e the pro$lem statement. 4. Analy0e the pro$lem thoroughly. In this step &e di)ide the pro$lem into smaller steps to e*amine the process of &riting programs. ?. /ra& the flo& chart. The steps listed in the pro$lem analysis and the se1uences are represented in a $loc% diagram. B. Translate the $loc%s sho&n in the flo&chart into ! " operations and then su$se1uently into mnemonics. ". Con)ert the mnemonics into De* code7 &e need to loo% up the code in ! " instruction set. =. .tore the program in 2ead(;rite memory of a single#$oard microcomputer. This may re1uire the %no&ledge a$out memory addresses and the output port addresses. A. -inally e*ecute the program. This re1uires us to tell the microprocessor &here the program $egins $y entering the memory address. As soon as the e*ecute %ey is pushed, the microprocessor loads 4!!!D in the program counter and the program control is transferred from the monitor program to our program. 8o& let us see an e*ample for de)eloping an assem$ly language program that selects the $iggest num$er in a data array.


Pro$lem statement 8 num$ers are stored in an array. The program has to select the largest of these 8 num$ers. Pro$lem Analysis Let us assume that 8N". The count is placed in the location 4"!!D. The num$ers are placed in the memory locations 4"!,D to 4"!"D. The result is to $e stored in the memory location 4B"!D. The ,st num$er of the series is placed in the accumulator and it is compared &ith the 4nd num$er residing in the memory. The larger of the t&o num$ers is placed in the accumulator. Again this num$er &hich is in the accumulator is compared &ith the ?rd num$er in the series and larger num$er is placed in the accumulator. This process of comparison is repeated till all the num$ers of the series are compared and the largest num$er is stored in the desired memory location. -lo& Chart The steps listed in the pro$lem analysis and the se1uences are represented in the flo& chart as sho&n in figure ,.,".







-igure ,.,"7 Program to find the largest num$er from a series of num$ers Program La$els Mnemonics 'perands L9I M': I89 M': /C2 I89 D, 4"!!D C, M D A, M C D Comments Address for count in DL pair Count in register C Address of ,st num$er in DL pair ,st num$er in accumulator /ecrement count Address of ne*t num$er



CMP pre)ious G8C accumulator. M': AD3A/ compared .TA DLT .ample Input and 'utput /ATA 4"!! 4"!, 4"!4 4"!? 4"!B 4"!" 23.ULT 4"B! 3E !" ? @B 3E A E" /C2 G8F

Compare ne*t num$er &ith ma*imum. Is ne*t num$er V Pre)ious num$er> 8o, larger num$er is in 6o to the la$el AD3A/. Kes, 6et larger num$er in Accumulator /ecrement count If more num$ers are to $e go to la$el L''P .tore result in 4B"!D .top

AD3A/ A, M C L''P 4B"!D

.ample Programs ;rite an assem$ly program to add t&o num$ers M:I /, ED M:I C, =-D M': A, C A// / 'UT P'2T, DLT ;rite an assem$ly program to multiply a num$er $y M:I A, ?!D 22C


22C 22C 'UT P'2T, DLT ;rite an assem$ly program to find greatest $et&een t&o num$ers M:I E, ?!D M:I C, B!D M': A, E CMP C GF 3MU GC 62T 'UT P'2T, DLT 3MU+ M:I A, !,D 'UT P'2T, DLT 62T+ M': A, C 'UT P'2T, DLT *a"e +ou under#tood, ,. Do& many columns may $e re1uired to &rite a line of an assem$ly language program> 4. ;hich particular field is a must for all lines> ?. ;hat is the purpose of the comment field> B. ;hat is the purpose of the la$el field> ". ;hich types of instruction is used to construct loops> 1.11 Direct Me'or+ .cce## /irect memory access (/MA) facilitates data transfer operations $et&een main memory and I(' su$systems &ith limited CPU inter)ention. The ma5ority of I(' de)ices pro)ide t&o methods for transferring data $et&een a de)ice and memory. The first method, called programmed I(' (PI'), is fairly easy to implement, $ut re1uires the processor to constantly read or &rite a single memory &ord ( #$its, ,=#$its or ?4#$its, depending on the de)ice interface) until the data transfer is complete. Although PI' is not necessarily slo&er than /MA, it does consume more processor cycles and can $e detrimental in a multi# processing en)ironment. The second method, called /MA, allo&s a system to issue an I(' command to a de)ice, initiate a /MA transaction and then place the process in a &aiting 1ueue. The system can no& continue $y selecting another process for e*ecution, there$y utili0ing the CPU cycles typically lost &hen using PI'. The /MA controller &ill inform the system &hen its current operation has $een completed $y issuing an interrupt signal. Although the data is still


transferred , memory unit at a time from the de)ice, the transfer to main memory no& circum)ents the CPU $ecause the /MA controller can directly access the memory unit. .teps in)ol)ed in the mode of /MA transfer are as follo&s. ,. /e)ice &ishing to perform /MA asserts the processors $us re1uest signal. 4. Processor completes the current $us cycle and then asserts the $us grant signal to the de)ice. ?. The de)ice then asserts the $us grant ac% signal. B. The processor senses in the change in the state of $us grant ac% signal and starts listening to the data and address $us for /MA acti)ity. ". The /MA de)ice performs the transfer from the source to destination address. =. /uring these transfers, the processor monitors the addresses on the $us and chec%s if any location modified during /MA operations is cached in the processor. If the processor detects a cached address on the $us, it can ta%e one of the t&o actions+ o Processor in)alidates the internal cache entry for the address in)ol)ed in /MA &rite operation o Processor updates the internal cache &hen a /MA &rite is detected A. 'nce the /MA operations ha)e $een completed, the de)ice releases the $us $y asserting the $us release signal. . Processor ac%no&ledges the $us release and resumes its $us cycles from the point it left off. Pins of ! " for /MA The ! " microprocessor has t&o pins a)aila$le for /MA mode of I(' communication+ D'L/ (Dold) and DL/A (Dold Ac%no&ledge). Conceptually this is an important techni1ue. It introduces t&o ne& signals a)aila$le on the ! " L D'L/ and DL/A. D'L/ L Dold. This is an acti)e high input signal to the ! " from another master re1uesting the use of the address and data $uses. After recei)ing the D'L/ re1uest, the MPU relin1uishes the $uses in the follo&ing machine cycle. All $uses are tri#stated and a Dold Ac%no&ledge signal is sent out. The MPU regains the control of $uses after D'L/ goes lo&. DL/A L Dold Ac%no&ledge. This is an acti)e high output signal indicating that the MPU is relin1uishing the control of the $uses.

Typically, an e*ternal peripheral such as /MA controller sends a re1uest L a high signal L to the D'L/ pin. The processor completes the e*ecution of the current machine cycle7 floats (high impedance state) the address, the data, and the control lines7 and sends the Dold Ac%no&ledge (DL/A) signal. The /MA controller ta%es control of the $uses and transfers data directly $et&een source and destination, thus $ypassing the microprocessor. At the end of data transfer,


the controller terminates the re1uest $y sending a lo& signal to the D'L/ pin, and the microprocessor regains control of the $uses. *a"e +ou under#tood, ,. ;hat is meant $y programmed I('> 4. ;hat are the limitations of programmed I('> ?. ;hat is meant $y cycle stealing> B. ;hat are the pins present in ! " for /MA operation> ". ;hat are the ad)antages of /MA> 1.12 Interru(t *and&ing The interrupt I(' is a process of data transfer &here $y an e*ternal de)ice or a peripheral can inform the processor that it is ready for communication and it re1uests attention. The process is initiated $y an e*ternal de)ice and is asynchronous, meaning that it can $e initiated at any time &ithout reference to the system cloc%. Do&e)er, the response to an interrupt re1uest is directed or controlled $y the microprocessor. The interrupt re1uests are classified into t&o categories namely mas%a$le interrupts and non#mas%a$le interrupts. A mas%a$le interrupt can $e ignored or delayed $y the microprocessor, if it is performing some critical tas%7 ho&e)er, the microprocessor has to respond to a nonmas%a$le re1uest immediately. The non#mas%a$le interrupt is one &hich can not $e ignored $y the microprocessor. The interrupt process allo&s the microprocessor to respond to these e*ternal re1uests for attention or ser)ice on a demand $asis and lea)es the microprocessor free to perform other tas%s. 'n the other hand, in the polled or the status chec% I(', the microprocessor remains in a loop, doing nothing, until the de)ice is ready for data transfer. In a typical microprocessor system, the soft&are can $e di)ided into ? possi$le groups. 'ne is the 'perating Loop, another is the Interrupt .er)ice 2outines, and the last is the EI'.('. functions and su$routines. The 'perating Loop is the main part of the system. It &ill usually end up $eing a se1uence of calls to EI'.('. su$routines, arranged in an order that accomplishes &hat &e set out to do, &ith a little manipulation and data transfer in $et&een. At the same time, at least it loo%s li%e itHs happening at the same time, interrupts are $eing ser)iced as they happen. In the ! ", there are thirteen (,?) possi$le e)ents that can trigger an interrupt. -i)e of them are from e*ternal hard&are interrupt inputs (T2AP, 2.T A.", =.", ".", and I8T2), that can $e from &hate)er hard&are &eH)e added to the ! " that &e deem to need ser)icing as soon as they happen. The remainders are soft&are instructions that cause an interrupt &hen they are e*ecuted (2.T ! L A). To digress 5ust a moment, there are t&o &ays to ser)ice, or act on, e)ents that happen in the system. 'ne is to scan or poll them and the other is to use interrupts. .canning is 5ust &hat is sounds li%e. 3ach possi$le e)ent is scanned 47

in a se1uence, one at a time. This is o% for things that donHt re1uire immediate action. Interrupts, on the other hand, cause the current process to $e suspended temporarily and the e)ent that caused the interrupt is ser)iced, or handled, immediately. The routine that is e*ecuted as a result of an interrupt is called the interrupt ser)ice routine (I.2), or recently, the interrupt handler routine. In the ! ", as &ith any CPU that has interrupt capa$ility, there is a method $y &hich the interrupt gets ser)iced in a timely manner. ;hen the interrupt occurs, and the current instruction that is $eing processed is finished, the address of the ne*t instruction to $e e*ecuted is pushed onto the .tac%. Then a 5ump is made to a dedicated location &here the I.2 is located.. .ome interrupts ha)e their o&n )ector, or uni1ue location &here itHs ser)ice routine starts. These are hard coded into the ! " and canHt $e changed (see $elo&). T2AP # has highest priority and cannot $e mas%ed or disa$led. A rising#edge pulse &ill cause a 5ump to location !!4BD. 2.T A."# 4nd priority and can $e mas%ed or disa$led. 2ising#edge pulse &ill cause a 5ump to location A." W N !!?CD. This interrupt is latched internally and must $e reset $efore it can $e used again. 2.T =." L ?rd priority and can $e mas%ed or disa$led. A high logic le)el &ill cause a 5ump to location =." W N !!?BD. 2.T "." L Bth priority and can $e mas%ed or disa$led. A high logic le)el &ill cause a 5ump to location "." W N !!4CD. I8T2 L "th priority and can $e mas%ed or disa$led. A high logic le)el &ill cause a 5ump to specific location as follo&s+ ;hen the interrupt re1uest (I8T2) is made, the CPU first completes it<s current e*ecution. Pro)ided no other interrupts are pending, the CPU &ill ta%e the I8TA pin lo& there$y ac%no&ledging the interrupt. It is up to the hard&are de)ice that first triggered the interrupt, to no& place an #$it num$er on the data $us, as the CPU &ill then read &hate)er num$er it finds on that data $us and do the follo&ing+ multiply it $y and 5ump to the resulting address location. .ince the # $it data $us can hold any num$er from !! L --D (! L 4"") then this interrupt can actually 5ump you to any area of memory $et&een !W and 4""W ie+ !!!! and !A--D ( a 4C space). 8.E+ This interrupt does not sa)e the PC on the stac%, li%e all other hard&are and soft&are interruptsX Kou &ill notice that there isnHt many locations $et&een )ector addresses. ;hat is normally done is that at the start of each )ector address, a 5ump instruction (? $ytes) is placed, that 5umps to the actual start of the ser)ice routine &hich may $e in 2AM.. This &ay the ser)ice routines can $e any&here in program memory. The )ector address 5umps to the ser)ice routine. There is more than enough 48

room $et&een each )ector address to put a 5ump instruction. Loo%ing at the ta$le a$o)e, there are at least locations for each of the )ectors e*cept 2.T ".", =.", and A.". ;hen actually &riting the soft&are, at address !!!!h &ill $e a 5ump instruction that 5umps around the other )ector locations. Eesides $eing a$le to disa$le(ena$le all of the interrupts at once (/I ( 3I) ie+ e*cept T2AP, there is a &ay to ena$le or disa$le them indi)idually using the .IM instruction and also, chec% their status using 2IM. There are other things a$out interrupts that &e &ill co)er as they come up, $ut this lesson &as to get you used to the idea of interrupts and &hat theyHre used for in a typical system. It<s similar to the scene &here one is standing at a $usy intersection &aiting for the traffic light to change, &hen a person came up and tapped us on the shoulder and as%ed &hat time it &as. It didnHt stop us from going across the street, it 5ust temporarily interrupted us long enough to tell them &hat time it &as. This is the essence of interrupts. They interrupt normal program e*ecution long enough to handle some e)ent that has occurred in the system. Polling, or scanning, is the other method used to handle e)ents in the system. It is much slo&er than interrupts $ecause the ser)icing of any single e)ent has to &ait its turn in line &hile other e)ents are chec%ed to see if they ha)e occurred. There can $e any num$er of polled e)ents $ut a limited num$er of interrupt dri)en e)ents. The choice of &hich method to use is determined $y the speed at &hich the e)ent must $e handled. The soft&are interrupts are the instructions 2.T n, &here n N ! L A. The )alue n is multiplied $y and the result forms an address that the program 5umps to as it )ector address ie+ 2.T B &ould 5ump to location BW N ?4 (4!D). Interru(t *and&ing 8it/out /ard8are #u((ort Dere &e descri$e interrupt handling in a scenario &here the hard&are does not support identifying the de)ice that initiated the interrupt. In such cases, the possi$le interrupting de)ices need to $e polled in soft&are. ,. A de)ice asserts the interrupt signal at a hard&ired interrupt le)el. 4. The processor registers the interrupt and &aits to finish the current instruction e*ecution. ?. 'nce the current instruction e*ecution is completed, the processor initiates the interrupt handling $y sa)ing the current register contents on the stac%. B. The processor then s&itches to super)isor mode and initiates an interrupt ac%no&ledge cycle. ". 8o de)ice responds to the interrupt ac%no&ledge cycle, so the processor fetches the )ector corresponding to the interrupt le)el. =. The address found at the )ector is the address of the interrupt ser)ice routine (I.2).


A. The I.2 polls all the de)ices to find the de)ice that caused the interrupt. This is accomplished $y chec%ing the interrupt status registers on the de)ices that could ha)e triggered the interrupt. . 'nce the de)ice is located, control is transferred to the handler specific to the interrupting de)ice. @. After the de)ice specific I.2 routine has performed its 5o$, the I.2 e*ecutes the Preturn from interruptP instruction. ,!. 3*ecution of the Preturn from interruptP instruction results in restoring the processor state. The processor is restored $ac% to user mode. Dere &e descri$e interrupt handling in a scenario &here the hard&are does support identifying the de)ice that initiated the interrupt. In such cases, the e*act source of the interrupt can $e identified at hard&are le)el. ,. A de)ice asserts the interrupt signal at a hard&ired interrupt le)el. 4. The processor registers the interrupt and &aits to finish the current instruction e*ecution. ?. 'nce the current instruction e*ecution is completed, the processor initiates the interrupt handling $y sa)ing the current register contents on the stac%. B. The processor then s&itches to super)isor mode and initiates an interrupt ac%no&ledge cycle. ". The interrupting de)ice responds to the interrupt ac%no&ledge cycle &ith the )ector num$er for the interrupt. =. Processor uses the )ector num$er o$tained a$o)e and fetches the )ector. A. The address found at the )ector is the address of the interrupt ser)ice routine (I.2) for the interrupting de)ice. . After the I.2 routine has performed its 5o$, the I.2 e*ecutes the Preturn from interruptP instruction. @. 3*ecution of the Preturn from interruptP instruction results in restoring the processor state. The processor is restored $ac% to user mode. *a"e +ou under#tood, ,. 4. ?. B. ". =. ;hether interrupt I(' is synchronous or asynchronous> ;hat is the ad)antage of interrupt I(' o)er programmed I('> ;hat are the t&o types of interrupt> ;hat are the interrupt pins a)aila$le in ! "> ;hat is the non#mas%a$le interrupt pro)ided $y ! "> ;hat is meant $y interrupt ser)ice routine>

Su''ar+ ,. The functional components of a digital computer are input, processor (CPU), output and memory.


4. The Central Processing Unit (CPU) has Arithmetic Logic Unit (ALU), Control Unit (CU) and registers ($oth general purpose and special). ?. The Central Processing Unit (CPU) etched on a single :ery Large .cale Integration (:L.I) single chip is called microprocessor. B. The num$er of $its that can $e processed $y the microprocessor at a time is called the &ord length of the system. ". The &ord length of the processor chips has increased form B $its to =B $its. =. Intel ! " is an $it microprocessor. A. ! " has si* #$it general purpose registers $y name E, C, /, 3, D and L. These #$it registers can $e used as three ,=#$it registers namely EC, /3 and DL. . Accumulator is a special purpose register that is used as an input to the Arithmetic and Logic Unit (ALU) and in most of the arithmetic operations it is one of the operand and the result is stored in it. Moreo)er this register is considered as a part of the ALU. @. DL register pair functions li%e the memory address register, i.e., it functions li%e the pointer to&ards the memory. ,!. .tac% Pointer is a special purpose register that acts li%e the pointer to&ards the area of the memory that is used as a Last in -irst out (LI-') structure (stac%). ,,. Program Counter is the special purpose registers that point to&ards the ne*t instruction to $e e*ecuted. In other &ords it functions li%e the pointer to&ards the area of the memory &here the program is stored. ,4. Instruction 2egister is the special purpose register in &hich the fetched instruction is recei)ed and decoded. Eased on the result of decoding a se1uence of e)ents ta%e place to e*ecute the instruction. ,?. -lag register is a collection of fi)e flip flops &hich are used to indicate the status of the ongoing acti)ity &ithin the microprocessor. -lags are used $y the $ranch instructions to implement po&erful programming constructs li%e decision ma%ing and loops. ,B. ! " Integrated Circuit has pins for address $us, data $us and control $us. To reduce the num$er of pins lo& order address $us is multiple*ed &ith data $us. Control $us is actually a collection indi)idual control signals. ,". Instruction cycle is defined as the time re1uired to complete the e*ecution of an instruction. ,=. Machine cycle is defined as the time re1uired to complete one operation of accessing memory, I(', or ac%no&ledging an e*ternal re1uest. ,A. T#state is defined as one su$di)ision of the operation performed in one cloc% period. These su$di)isions are internal states synchroni0ed &ith the system cloc%, and each T state is precisely e1ual to one cloc% period. , . 3ach instruction cycle consists of one or more machine cycles and each machine cycle is di)ided into T states. ,@. The &ay of specifying the operand in an instruction is called addressing mode and ! " supports a )ariety of addressing modes to pro)ide fle*i$ility to programmers.


4!. Ma5or category of ! " instructions are data transfer instructions, arithmetic instructions, logical instructions, rotate instructions, compare and testing instructions, $ranch instructions and machine control instructions. 4,. An assem$ly language program is a set of instructions &ithin the mnemonics of a gi)en microprocessor. These instructions are the commands to the microprocessor to $e e*ecuted in the gi)en se1uence to accomplish a tas%. 44. /irect memory access (/MA) facilitates data transfer operations $et&een main memory and I(' su$systems &ith limited CPU inter)ention. 4?. A mas%a$le interrupt can $e ignored or delayed $y the microprocessor, if it is performing some critical tas%7 ho&e)er, the microprocessor has to respond to a nonmas%a$le re1uest immediately. In this unit, you ha)e learnt a$out the architecture, programming and interfacing of ! " an #$it microprocessor. ! " microprocessor &as &idely used in special purpose systems and it is not meant for the construction of digital computers. Unit II deals &ith ! = a ,=#$it microprocessor that &as intended to $e used as the CPU in a microcomputer. E2erci#e# ,. ;hile e*ecuting a program, &hen ! " completes the fetching of the machine code located at the memory address 4!BAD, &hat is the content of the program counter> 4. Assume that memory location 4!A"D has a data $yte BAD. .pecify the contents of the address $us A,"#AA and the multiple*ed $us A/A#A/! &hen the MPU asserts the 2d (Acti)e Lo&) signal> ?. The instruction M': E,M copies the contents of the memory location in register E. It is ,#$yte instruction &ith t&o machine cycles and se)en T states. Identify the second machine cycle and its control signal. B. If the ! " adds AD and A@D, specify the contents of the accumulator and the status of ., F and CK flags. ". 3*plain &hy the num$er of output ports in the peripheral#mapped I(' is restricted to 4"= ports> =. 3*plain &hy a latch is used for an output port, $ut a tri#state $uffer can $e used for an input port. A. -ind the De* machine code for the follo&ing instructions from the ! " instruction summary and identify the num$er of $ytes each instruction. M:I E,B-D M:I C,A D M': A,C A// E 'UT !AD DLT


. If the starting address of the system memory is 4!!!D, and you &ere to enter the De* code for the instructions in 1uestion A, identify the memory addresses and their corresponding De* codes. @. The follo&ing $loc% of data is stored in the memory location from 99""D to 99"AD. Transfer the data to the locations 99 !D to 99 "D in the re)erse order (e.g., the data $yte 44D should $e stored at 99" D and ?AD at 99 !D). data(D) 44,A",E4,@@,A-,?A ,!. A string of si* data $ytes is stored starting from memory location 4!"!D. The string indicates some $lan%s ($ytes &ith 0ero )alue). ;rite a program to eliminate the $lan%s from the string. /ata(D) -4, !!, !!, BA, @ , !! .n#8er# ,. The program counter has to point to the memory location from &hich the ne*t $yte is to $e read. Dence the content of the program counter &ill $e 4!B D. 4. (A,"#A ) L 4!D, (A/A#A/!) L BAD ?. The second machine cycle is memory read. The processor reads the contents of memory in register E, and the control signal is 2/ (Acti)e Lo&) B. AD J A@D N ,!!D. Therefore !!D is stored in the accumulator &ith a carry of ,. Dence .N!, CKN, and FN, ". The num$er of output ports in the peripheral I(' is restricted to 4"= ports $ecause the operand of the 'UT instruction is #$it7 it can ha)e only 4"= com$inations. =. A latch is necessary to hold the output data for the display. Do&e)er, the input data $yte is o$tained ena$ling a tri#state $uffer and placed in the accumulator. A. != B!3 A A@ ! /? !A A= . 4!!!D != 4!!,D B4!!4D !3 4!!?D A 4!!BD A@ 4!!"D ! 4!!=D /? 4!!AD !A 4!! D A= @. .TA2T+ L9I D,4!""D L9I /,4! "D M:I E,!=D L''P+ .TA9 E


,!. .TA2T+ L''P+

I89 /C2 G8F DLT M:I L9I L9I

E / L''P


E,!=D D,4!"!D /,4!"!D M': A,M '2A A G8F .CIP .TA9 / I89 / I89 D /C2 E G8F L''P DLT