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# Slide 1 W.

## Rhett Davis NC State University ECE 546 Fall 2012

ECE 546 - VLSI Systems Design
Lecture 16: SRAM
Fall 2012
W. Rhett Davis
NC State University
with significant material from Rabaey, Chandrakasan, and Nikoli
Slide 2 W. Rhett Davis NC State University ECE 546 Fall 2012
Announcements
Re-grade Requests for Midterm due in 1 week
HW#7 Due Tuesday
Project Introduction Tuesday
Continue forming project groups
Slide 3 W. Rhett Davis NC State University ECE 546 Fall 2012
Todays Lecture
SRAM
Multi-Port SRAM
CAM
Slide 4 W. Rhett Davis NC State University ECE 546 Fall 2012
6-transistor CMOS SRAM Cell
WL
BL
V
DD
M
5
M
6
M
4
M
1
M
2
M
3
BL
Q
Q
Slide 5 W. Rhett Davis NC State University ECE 546 Fall 2012
Assume bit-lines precharged high, Q=1, Q=0
What could go wrong?
WL
BL
V
DD
M
5
M
6
M
4
M
1
V
DD
V
DD
V
DD
BL
Q
=
1
Q
=
0
C
bit
C
bit
Slide 6 W. Rhett Davis NC State University ECE 546 Fall 2012
Modified equations
(12.2) and (12.3)
(by Harun Demircioglu)
What are the operating
regions assumed by
these equations?
Is this valid for our
technology?
WL
BL
V
DD
M
5
M
6
M
4
M
1
V
DD V
DD
V
DD
BL
Q
=
1
Q
=
0
C
bit
C
bit
5 5
1 1
L W
L W
CR =
( ) ( ) ( )
|
|
.
|

\
| A
A A + =
|
|
.
|

\
|
A + A
2 2
2
0 1 ,
2
0 5 ,
V
V V B V V k
V
V V V B V V V k
n n T DD M n
DSATn
DSATn DD n n T DD M n
( ) ( ) ( ) ( )
( )CR B
V V CR CR V V V CR V B
V
n
n T DD DSATn n T DD DSATn n
2 1
2 1 1
2
0
2 2
0

+ + + +
~ A
Slide 7 W. Rhett Davis NC State University ECE 546 Fall 2012
For which side of this curve does the SRAM work properly?
0
0
0.2
0.4
0.6
0.8
1
1.2
0.5 1 1.2 1.5 2
Cell Ratio (CR)
2.5 3
V
o
l
t
a
g
e

R
i
s
e

(
V
)
Slide 8 W. Rhett Davis NC State University ECE 546 Fall 2012
A more robust definition is the maximum noise voltage
needed to flip the value during a read
For simplicity on HW and Exams, we wont use this definition
At low supply voltages, Read SNM is too often negative,
due to Vt variation between transistors
As a result, supply voltages have not scaled below 1V in
Source:
Calhoun &
Chandrakasan,
JSSC 2007
V from slide 6
Slide 9 W. Rhett Davis NC State University ECE 546 Fall 2012
CMOS SRAM Analysis (Write)
Assume cell contains 1, try to write 0
What needs to happen for a successful write?
BL
=
1 BL
=
0
Q
=
0
Q
=
1
M
1
M
4
M
5
M
6
V
DD
V
DD
WL
Slide 10 W. Rhett Davis NC State University ECE 546 Fall 2012
Conditions for Successful Write
Modified equations
(12.5) and (12.6)
(by Harun Demircioglu)
What are the operating
regions assumed by
these equations?
Is this valid for our
technology?
BL
=
1 BL
=
0
Q
=
0
Q
=
1
M
1
M
4
M
5
M
6
V
DD
V
DD
WL
6 6
4 4
L W
L W
PR =
( ) ( ) ( )
|
|
.
|

\
|
=
|
|
.
|

\
|
+
2 2
2
0 4 ,
2
0 6 ,
DSATp
DSATp DD Q p p T DD M p
Q
Q Q n n T DD M n
V
V V V B V V k
V
V V B V V k
( ) ( ) ( )
( )
n
DSATp
DSATp p T DD p
n
p
DSATp p n T DD DSATp p n T DD
Q
B
V
V V V B PR V B V V V B V V
V
2 1
2
1 2
2
0
2
0 0

|
|
.
|

\
|
+ +
=

## Slide 11 W. Rhett Davis NC State University ECE 546 Fall 2012

CMOS SRAM Analysis (Write)
For which side of this curve does the SRAM work properly?
Slide 12 W. Rhett Davis NC State University ECE 546 Fall 2012
6T-SRAM Layout
V
DD
GND
Q
Q
WL
BL BL
M1 M3
M4 M2
M5 M6
Slide 13 W. Rhett Davis NC State University ECE 546 Fall 2012
Another Bit-Cell Layout
This bit-cell was created
by Xi Chen, Ting Zhu,
and Harun Demircioglu
for the Fall 2007 project
Best performance in
class
See their report on last
years web-page
group 35
see Project Results
Will this bit-cell still work,
now that we have
lithographic simulations?
Slide 14 W. Rhett Davis NC State University ECE 546 Fall 2012
Summary
In an SRAM
Size NMOS larger than pass-gate to avoid read-upset
Size PMOS small for successful write
Slide 15 W. Rhett Davis NC State University ECE 546 Fall 2012
Todays Lecture
SRAM
Multi-Port SRAM
CAM
Slide 16 W. Rhett Davis NC State University ECE 546 Fall 2012
Extending the SRAM Cell
This bit-cell supports
a read or write to one
location in the array
How would we
change it if we
write to two
locations?
WL
BL BL
Slide 17 W. Rhett Davis NC State University ECE 546 Fall 2012
2-Port SRAM Cell
This bit-cell supports
two locations in the
array
How could we
optimize the cell if the
second port were
Slide 18 W. Rhett Davis NC State University ECE 546 Fall 2012
What is the
of this cell?
What is the
of this cell?
R/WWL
R/WBL RBL
RWL
R/WBL
Slide 19 W. Rhett Davis NC State University ECE 546 Fall 2012
What is the
of this cell?
What is the
of this cell?
R/WWL
R/WBL RBL
RWL
R/WBL
Slide 20 W. Rhett Davis NC State University ECE 546 Fall 2012
Another Approach to Multi-Ports
Use two separate single-port arrays and re-
direct logic to send requests to each
R
o
w

D
e
c
o
d
e
r
Bit line
2
L 2 K
Word line
A
K
A
K1 1
A
L2 1
A
0
M.2
K
A
K2 1
Sense amplifiers / Drivers
Column decoder
Input-Output
(M bits)
Storage cell
R
o
w

D
e
c
o
d
e
r
Bit line
2
L 2 K
Word line
A
K
A
K1 1
A
L2 1
A
0
M.2
K
A
K2 1
Sense amplifiers / Drivers
Column decoder
Input-Output
(M bits)
Storage cell
Re-direct logic
Slide 21 W. Rhett Davis NC State University ECE 546 Fall 2012
Todays Lecture
SRAM
Multi-Port SRAM
CAM
Slide 22 W. Rhett Davis NC State University ECE 546 Fall 2012
Primary function is to look up the address of
stored data, rather than the data itself
Most often used in Internet Protocol Routers to
classify & forward packets
Similar to SRAM, but has 4 types of wires in the
array
Bit-line (BL) and Word-line (WL), used to write data
into the array
Search-Line (SL), used to drive the searched value
Match-line (ML), used to indicate a match
Ternary CAM (TCAM) also stores "don't care"
Slide 23 W. Rhett Davis NC State University ECE 546 Fall 2012
High-Level CAM Architecture
Slide 24 W. Rhett Davis NC State University ECE 546 Fall 2012
CAM Bit-Cells
Source: Pagiamtzis & Sheikholeslami, JSSC '06
NOTE: Bit-lines and access transistors removed