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David J. Sager

Copyright 1972 and 1999, David J. Sager. Permission is hereby given for anyone to copy, reproduce, and distribute this work in its entirety or in part, for any purpose, provided that proper attribution to the author is included, and a reference to where the entire work may be obtained is included. If the entire work, including this copyright notice, is kept intact and unaltered, then this in itself constitutes such reference. Otherwise, the requirement for a reference may be satisfied by including a World Wide Web location or Internet Address from which the entire work may be downloaded. If the work is altered, this must be clearly noted in the attribution. The author is available by email at

Table of Contents
0. 1. Foreword..................................................................................................................... 2 Introduction.................................................................................................................. 6 1.1 Circuit Analysis....................................................................................................... 6 1.2 Describing Circuits.................................................................................................. 6 2. Network Topology....................................................................................................... 8 2.1 Terminals................................................................................................................. 8 2.2 Links and Currents................................................................................................... 8 2.3 Nodes and Voltages................................................................................................. 9 2.4 Devices.................................................................................................................... 9 2.5 A Network Topology............................................................................................... 9 2.6 Semidevices and Ports............................................................................................. 9 3. Descriptive Remarks................................................................................................. 11


Some Important Devices and Some Examples........................................................... 15 4.1 One Terminal Devices........................................................................................... 15 4.2 Two Terminal Devices.......................................................................................... 15 4.2.1 The Current Source........................................................................................ 15 4.2.2 The Voltage Source........................................................................................ 17 4.2.3 The Resistor................................................................................................... 19 4.2.4 The Diode...................................................................................................... 21 4.2.5 The Inductor and the Capacitor...................................................................... 24 4.3 Three Terminal Devices........................................................................................ 26 4.3.1 The Silicon Bipolar Transistor...................................................................... 26 4.3.2 The MOSFET................................................................................................ 34 5. Composite Devices.................................................................................................... 37 6. Numbers of Equations and Independence of Equations.............................................. 41 6.1 The Essentials........................................................................................................ 41 6.2 Topology................................................................................................................ 42 6.2.1 Summary........................................................................................................ 42 6.2.2 Independence of the Current Balance Equations............................................ 42 6.2.3 Equation Counting.......................................................................................... 45 6.3 Devices.................................................................................................................. 47 6.3.1 Summary........................................................................................................ 56 7. A Circuit Analysis Program....................................................................................... 57 7.1 Description............................................................................................................ 57 7.2 Example................................................................................................................. 60 8. Estimating.................................................................................................................. 66

0. Foreword
I wrote this presentation of circuit analysis at the University of California, Riverside in 1972. I scanned it, reedited it, and filled it out more in 1998 and 1999. This presentation was written and used to teach circuit analysis very quickly in a course on processor design for computer science students. The students began with no background in electronics or circuits at all. They did have significant programming ability, and were relatively sophisticated in mathematics. The circuits unit was to bring these students to a level of sophistication in circuits so that they would be capable of doing a DC analysis of a TTL or ECL gate circuit, with a number of transistors and diodes and any applied input voltage, by hand. Therefore they would be able to produce the Z shaped transfer function of such a gate by hand. They would also be able to analyze a 2 transistor flip flop by hand and to show that it can be in 3 different states. Perhaps more importantly, the students wrote a circuit analysis program that could do DC analysis on quite complex circuits containing voltage sources, current sources, resistors, diodes, and transistors. This program could analyze significant circuits with many states including many selfsustaining states. Writing this program was an exercise in writing a complex application program. It was also proof that the students understood circuit analysis. If you can write a program to do it, you know how to do it. Besides circuits, it was a goal that the students leave with a keen understanding of where circuit states come from at the lowest level of circuits, how these states become logic levels and how they become self sustaining states in latches and flip flops memory devices. This circuits unit was just a part of the course. This course went on to examine how important logic families worked at the circuit level, and to combinational logic design, design of registers, muxes, adders and other important structures, sequential logic design, and design of entire processors with emphasis on the control logic. The actual instruction in circuits took place in about 3 to 4 weeks. The project, writing a circuit analysis program, took quite a few more weeks outside of class. Meanwhile the class moved on. The challenge was how to bring a class from 0 to considerable sophistication with circuit analysis, including a solid understanding of some complex circuit devices, in 3 or 4 weeks, about 10 classroom hours. The advantage that I had was that the students started out fairly sophisticated in mathematics and programming. In the 3 or 4 weeks of instruction we did not cover all of the material in this paper. We were very brief on composite devices in section 5. We did not touch section 6 at all. Indeed I make the point in section 6 that although this material may be interesting to some people, it is not actually required for almost anything you might want to do. I learned circuit analysis at the University of Wisconsin in 1964 to 1965. I was taught several different complex and arcane methods for writing the equations for a circuit (e.g., loop equations, cut-set equations). These involved extracting the graph of the circuit, constructing the tree, etc. I was taught from notes, Elementary Topology and Network Equilibrium Equations written at the University of Wisconsin. I have provided a copy of these notes together with this paper in my postings of this paper. It should be very interesting indeed to compare the approach in Elementary Topology and Network Equilibrium Equations with the approach in this paper. Elementary Topology and Network Equilibrium Equations is the conventional way to write circuit equations. The only other known choice at the time was to write random loop equations. With random loop equations, there is no effective procedure for getting a complete set of equations. That is why there was this arcane thing with trees and so forth. The conventional way to write circuit equations was entirely too complex. I was also convinced that it was needlessly complex. If I had to teach it this way, I would never be able to teach what I wanted in circuits in 3 to 4 weeks. It was also much, much too complex to write a circuit analysis program with this conventional approach. Students would have little chance of success with their projects of writing a quite sophisticated circuit analysis program if they were taught the conventional approach to writing circuit equations and told to go with it. I also believed that the conventional approach was conceptually opaque. Students would not get what is really going on in circuits in a few weeks if they had to see circuits from the conventional vantage point. I therefore developed the approach of this paper. To my knowledge, no one else has presented circuit analysis this way. There is no new science in this presentation. Everything here is well known. But as far as I know, it is a completely new presentation and method of writing the circuit equations. I believe this paper is a superior presentation of circuit analysis compared to the conventional approach, which is exemplified in Elementary Topology and Network Equilibrium Equations. This is not picking on these notes in particular. These notes are very representative of the conventional approach to writing circuit equations. They did a good job of presenting this conventional approach. You will see exactly the same thing in an endless string of textbooks on circuit analysis. In the conventional approach you never quite know if a resistor is some special thing that is intrinsic to circuit analysis itself, or if it is a device. Is Ohms law fundamental to circuit analysis, or is it a device characteristic? The approach of this paper makes it very, very clear what a device is. No devices are special. You can use any devices you want. A resistor is a device just like any other device. Ohms law is a device characteristic. It is neither more nor less fundamental than any other device characteristic. The conventional approach is entirely built around 2 terminal devices. There really is no provision in the circuit analysis itself for anything but 2 terminal devices. This follows directly from the conventional approach of having currents flowing through devices. If a current flows through a device, it is very hard to have that device be anything but 2 terminals. 3 terminal devices, like transistors, must be modeled in terms of 2 terminal devices. Then there must be some extra equations thrown in in the form of dependent sources. You cannot model a 3 terminal device without

something like dependent sources. I believe that the inability of the conventional approach to deal with atomic devices with anything other than 2 terminals is a significant disappointment. Further, I believe it is conceptually limiting. In the presentation of this paper it is very natural to have atomic devices with any number of terminals. This paper presents and uses devices with 1, 2, 3 and 4 terminals. In this paper, quite unlike the conventional approach, currents flow in links which are ideal wires. (Note that the word link in this paper is used differently from the way the word link is used in the conventional approach.) Having currents in links frees devices to be whatever they want to be. Links, of course, have to be two ended. But it is not limiting to have ideal wires be restricted to be two ended. In this presentation, 2 terminal devices are in no way any more legitimate or natural than devices with any other number of terminals. The whole point of Elementary Topology and Network Equilibrium Equations is a complex way to get a complete set of independent equations. With the conventional approach, getting the right equations is a very big issue. If you do not get the right equations, it can lead to the wrong conclusions. It is easy enough to not get the right equations, so there is this complex topology thing with trees, etc. just to have an effective method to get the right equations. By contrast, in the presentation of this paper, getting the right equations is essentially trivial. There is no issue about getting the right equations. There is no complex procedure required. There is one obvious current balance equation for each device, and then the device characteristics. Period. It is that simple. These are always, even under extremely bizarre and pathological conditions, exactly the right equations from which you get the right conclusions. There are cases in which the circuit equations should not be complete and independent. Such cases occur pretty frequently. Since the conventional approach is centered on a complex procedure to get complete and independent equations, it does not deal with these cases well. But these are real cases that are accurate models of circuits you can and do actually build. The presentation of this paper deals with cases in which there are no solutions or multiple solutions as being just as natural as when there is a unique solution. When there is no solution, there should not be a solution and it is exactly the correct description of what the circuit behavior is. If there are multiple solutions, there should be multiple solutions and this again is a correct description of what the circuit behavior is. It is not generally appreciated how common these cases are because conventional circuit analysis does not deal with them very well so they tend to be swept under the rug. Although we did not get into it much in the limited time for circuit analysis in the course, and this paper is quite brief on it too, this approach really provides a natural way to make composite devices; to determine their characteristics, and then to use them in circuits as devices that are completely on a par with atomic devices. From the method of writing circuit equations presented in this paper it is totally obvious how to write a program to form those equations and solve them. Section 7 describes the writing of a program in detail. This emphasizes how easy it is, but it should not be necessary. It is obvious. The conventional approach to writing circuit equations is not pointless. The conventional approach results in a very small number of unknowns and a comparably small number of equations. It was designed to do just that. These methods were developed at a time when the equations would have to be solved by hand, perhaps with a slide rule, or with a mechanical calculator at best. It was thought that it was important to get a small number of equations with a small number of unknowns for such a hand solution. This is not unreasonable. If equations are written for the same circuit according to this paper there will be many more unknowns and many more equations. The few classical equations will be quite dense. The many more equations according to this paper will be very sparse. On the other hand, to really do hand analysis of typical circuits encountered everyday in design, one rarely writes out all the equations and solves them classically. The common circuits can be solved rapidly by hand without the formality of writing the equations out. The method by which one does this is illustrated in section 8. In fact, the way one can rapidly analyze complex circuits as illustrated in section 8 inspired the approach of this paper. As it turns out, really fast hand solution demands a large number of very sparse equations not a smaller number of dense equations. Knowing the method of this paper makes it easy to go to fast hand solution. By contrast, there is much less connection between the conventional approach with dense equations and fast hand solutions. For the few cases where fast methods dont help and there is no alternative to writing out the equations and solving them classically, it could be argued that dense equations with fewer unknowns is better. But today, one would not do such problems by hand anyway; you would use a circuit analysis program.

1. Introduction
1.1 Circuit Analysis
This is a very modern approach to network analysis. It is strongly influenced by two factors. The first is the explosive growth in the complexity of systems in the last 15 years, which is certain to go on for the foreseeable future. The second is the increasing importance of computers in network analysis. In the beginning there was classical circuit analysis. There were the classic (mathematical) devices: the resistor, capacitor, and the inductor. These were THE passive linear components. There were a few other (mathematical) elements: the voltage source and the current source and for those who were really with it, the switch. These were the tube days. There were rather few real devices too: the physical realizations of the resistor, capacitor, and inductor, and a few kinds of vacuum tubes and just a few others. For the purpose of analysis, vacuum tubes were represented by combinations of basic devices that have about the same properties (tube equivalent circuit). Today systems often enough have thousands of components. There are also, a great many real devices. There are switching diodes, voltage reference diodes, current regulator diodes, tunnel diodes, variable capacitance diodes, thyrector diodes, and more, and these are just the diodes. There are also many kinds of transistors. New devices are appearing almost literally every day. If you consider integrated circuits, the possible variety is almost limitless. It would seem that a more open-minded idea of what a device is in the mathematics of network analysis is indicated. The modern trend is to define a device in circuit analysis so that almost anything can be one. There are those (for example in the field called optimal control) essentially doing network analysis wherein a typical component device is an entire computer. The second big factor influencing the form of this presentation of circuit analysis is the computer. Now much of the network analysis that is actually done is done by computer. A number of systems have been developed so that a circuit can be more or less drawn with a light pen on a graphic display device and the computer immediately analyzes it. The form that network analysis takes in this presentation is intended to be suitable for implementation on a computer.

1.2 Describing Circuits

The complete description of a network is broken into 2 parts. The first part is called network topology. The network is viewed as a bunch of black boxes (we don't ask what is in the boxes). Each black box has a number of terminals, and wires connect various of the terminals. In the network topology then, we are interested in how many black boxes (devices) there are, how many terminals each one has, and exactly which terminals are connected to which other terminals. In the second phase of network analysis we ask what the nature of each device is. We expect the answer to come in the form of the characteristics of the device. We still view the device as a black box and we still don't want to know what's inside but rather we want a description of what it does. These characteristics come to us from other fields such as device physics with which we are not concerned in network analysis. In network analysis we are doing mathematics and strictly speaking, everything we talk about is a mathematical object. I will define devices like resistors purely in mathematical terms with no reference to any physical object at all. For most of the mathematical objects we define, physical objects with the same name exist. The mathematical object is frequently idealized to some degree, but its behavior models a real device well enough to be useful. Better and better models of a real device can be made but making such models is a discipline of study in itself. We associate the real components of a real circuit with mathematical devices that model them, usually of the same name, to get a model of the circuit. One final remark before we begin is that the presentation will consist essentially of just definitions. The definitions will be presented in the style of formal definition, theorem, proof mathematics with little text around them. There are some theorems that are unique to circuit analysis but this presentation is mostly not about theorems. The mathematical objects used here are well known in mathematics. Once we have defined what we are doing, in a real sense, the theorems come from mathematics.

2. Network Topology
2.1 Terminals
Let T be a set with a finite, nonzero number of members. If t is a member of T, then t is called a terminal. T is the set of terminals. Or, in plain English: suppose I have a bunch of things I want to call terminals.

2.2 Links and Currents

Let L be a collection of ordered pairs from T. L may be empty or have any possible ordered pairs in it. L is the set of Links. If l is a member of L, call l a link. Assume that for each link there is a real number. Precisely stated, let C be a function from L into the real numbers. The real number corresponding to any link is the current in that link. A link is the mathematical object that represents a wire. This says suppose some terminals are connected by wires. A wire is described by telling which two terminals it connects (thus the mathematical object, a link, can just be the pair of terminals). Now wires don't have any special directions - one way along a wire is the same as the other, but currents do go in directions. We arbitrarily assign a direction to the wire just so we will be able to talk about which way the current is going. We do this by saying a link is an ordered pair of terminals. That way we can say the current is positive if it goes from the first terminal to the second and negative if it happens to be going the opposite way. Let la,b be a link from terminal a to terminal b. If Ia,b is the current in la,b then we say: la,b contributes a current Ia,b into b. la,b contributes a current Ia,b out of a. For any terminal t, the current entering t is defined to be the sum of all the contributed currents into t minus the sum of all contributed currents out of t. {To be absolutely correct, a link is a named ordered pair from T. If a and b are two real terminals in a real world circuit, it would be possible to connect any number of wires between them. Since this is true in the real world, we would like to be able to represent this in the mathematical model with any number of links between the mathematical terminals a and b. Strictly speaking, there can be no more than 2 ordered pairs of the terminals a and b and they would have to be (a, b) and (b, a). Every ordered pair containing a and b must be indistinguishable from one of these. But if we add a name, then there can be any number of named ordered pairs containing a and b, distinguishable by different names. This is an extremely minor point, of very little practical value. It will be completely ignored in this paper except for section 6, which examines the effect of having more than 1 link connecting the same terminals.}

2.3 Nodes and Voltages

A set of all terminals connected by links is called a node. If there are any terminals not elements of links they are also nodes. Thus we see that the terminals are broken up into groups, each group called a node and each terminal is in one and only one node. Let N be the set of nodes. Assume that there is a real number for each node. Precisely stated, let V be a function from N into the real numbers. The real number corresponding to any node is the voltage at that node. We want to have voltages at each terminal but we want to make sure that if any two terminals are connected by wires, then they must have the same voltages. We do this by lumping together all the terminals that are joined by wires - they must all have the same voltage - and we call the bunch of terminals a node. We then make voltages properties of the nodes. We define the voltage at a terminal to be just the voltage of the node to which it belongs.

2.4 Devices
Assume now that D is a collection of disjoint, ordered subsets of T and that if t is a member of T, then t is a member of d for some d in D. The elements, d, of D are called devices, and we observe that each terminal belongs to exactly one device. The current entering a device is defined to be the sum of all currents entering all terminals of the device. Each device is an ordered set of terminals. In general, different terminals of the device play different roles in the device characteristics that go with the device. This just means that we can tell which terminal on a device is which.

2.5 A Network Topology

If we have sets T, L, D and functions C and V as described, and if the total current entering each device in D is zero, then (T, L, D, C, V) is called a network topology.

2.6 Semidevices and Ports

There are just a couple more words that will be handy to have around: If d is a device in a network topology and if S is a subset of d (that is S is some of the terminals in d) such that the sum of the currents entering all the terminals in S = 0 then S is a semidevice. In particular, a semidevice consisting of exactly two terminals is called a port. Devices that consist of exactly 2 ports are nice for many things. Not surprisingly, such a device is called a 2-port.

3. Descriptive Remarks.
The plan is to describe a real circuit by associating a network topology with it. The theory consists of saying that for any circuit there is a suitable topology for describing it. Mostly, the network topology is just a way to talk about the terminals and which terminals are connected together, but there is one more very significant thing. There is this condition that in a network topology, the total current entering each device must be 0. This may be viewed as expressing a physical law, conservation of charge. Every network topology must have all of its terminals be members of devices. We can immediately deduce that the total current entering all of the terminals of the entire network topology must also be 0. And now we have asserted that every physical circuit can be described (quite well) by a network topology. Along with the topology comes a bunch of equations of the form

Ia + Ib + ... + Ic - Id - Ie ... - If = 0
which express the fact that the total current entering each device must be zero. There will be one such equation for each device. The topology also says that there must be a bunch of real numbers called voltages, one for each node, but it says nothing further about the voltages. Consequently the equations involving the currents are the only restrictions on currents and voltages made by the topology. One wants to also have descriptions of each of the devices in the network. In general, with each device there will be additional restrictions on the permissible choices of numbers for the currents and voltages. These restrictions are called the device characteristics. They may often take the form of one or more equations such as

Vi - Vj = RIi
Or of inequalities like

Vj Vi
When all the proper characteristics are combined with the topology, the result is a complete description of the circuit. The principle task of network analysis is then to find out exactly what choices of numbers for the currents and voltages are consistent with all restrictions (topology and device characteristics), if any. There are 3 possibilities: 1. There are no choices of currents and voltages that are consistent with all restrictions; 2. There is exactly one unique set of voltages and currents that satisfy all restrictions; 3. There are many sets of currents and voltages that are consistent. I will say a few words about each of these situations. There may be no choice of currents and voltages which satisfies all restrictions. This is a situation similar to the case in algebra in simultaneous linear equations when the equations are "inconsistent". In fact, that is often exactly how this happens. There is perhaps a tendency to think of such a case as abnormal. In fact in network analysis, this is a comparatively normal case and gives very useful information. It says DON'T DO IT!! Many circuits can easily be built that result in descriptions with "no solutions". The analysis, in finding no voltages and currents that satisfy all requirements, is telling you that the universe cannot exist in the state that you are describing. It is predicting the end of the universe if you construct this circuit. It seems in practice that some factor, not represented in the formal analysis, always intervenes to prevent destruction of the entire universe. Nevertheless, if you insist on building the circuit you can expect in the worst case catastrophic failure of some of the devices, and in the best case the circuit just won't be useful. It may be that there is a unique choice of currents and voltages that satisfy all restrictions. We are perhaps conditioned to think of this as normal and desirable. In network analysis, this is extremely abnormal. In any cases we examine, it should not happen. The reason for this is that the topology places no restrictions on the voltages - all restrictions on voltages come from device characteristics. All normal devices we will consider place restrictions only on differences between voltages at pairs of nodes. Physicists have great confidence that it will never be possible to construct a device that can restrict voltages except in terms of differences between two voltages. One can see that if one has a network (a network is considered to be a network topology along with all device characteristics) that has a solution (that is, there is a choice of currents and voltages satisfying all requirements) that in general, one can add a constant to all voltages and obtain another solution. This is so because all differences between pairs of voltages will remain the same. This is a very normal case. This is also equivalent to saying that there is one free parameter in the system or, stated still differently, one can choose any number at all for one of the voltages and there still remains at least one choice of remaining voltages that produces a solution. In view of the fact that one voltage can be chosen arbitrarily, it has become customary to choose one node in a network and call it ground. One arbitrarily dictates that the voltage at this node will be zero. The ground node is usually designated with the symbol:

It has further become customary to not explicitly draw the links connecting all the terminals of the ground node. Thus a network

may be drawn

The ground symbol on a terminal means there is a link from that terminal to others of the ground node. After arbitrarily dictating the voltage of the ground node, one is about equally likely to find that there is then a unique solution or many solutions (assuming there is a solution at all). The job then is to list all the solutions or express them in some form.

4. Some Important Devices and Some Examples.

4.1 One Terminal Devices
There is only one reasonable one terminal device. It is called a tie point and it has no characteristics at all. Thus it places no further restrictions on currents or voltages than just that required by the topology. Physically, the devices that correspond to tie points are just places where a number of wires can be connected together and held, or splices in wires.

4.2 Two Terminal Devices

When one considers 2 terminal devices there is already a wealth of them. I will give a few.

4.2.1 The Current Source

First, there is the current source. It's symbol and characteristics are:



Ii = I

where Ii is the current entering terminal ti. I is the value of the current source. Physically, there are current regulator diodes that are well described by a current source over a limited range of conditions. Otherwise current sources are generally made of a number of other components. Power supplies can often be operated in "current regulating mode" in which case they are very well described as current sources. Current sources are very commonly "synthesized" out of other components like transistors and resistors and appear as parts of circuits. We will analyze two circuits as examples. The first is just the current source alone not connected to anything.



In the topology we see there are 2 terminals labeled t1 and t2. They form 2 nodes since they are not connected. There are no links. Consequently there are no currents and the current entering terminal t1 = 0. The current entering terminal t2 is 0 too. Topology requires that the current entering t1 + the current entering t2 = 0, i.e., that the current entering the one device = 0. This is trivially satisfied. The device characteristic requires the current entering terminal t1 = I. Except in the special case where I = 0 this is inconsistent and there are no solutions. Current sources should not be "open circuited"; they must always be connected to something. Consider the second example:



Again, there are two terminals, t1 and t2, belonging to the same one device. There is one link, l1,2, from t1 to t2. Consequently there is only one current, I1,2. There is one node consisting of t1 and t2. Consequently there is only one voltage V1. The current entering t1 is -I1,2 and that entering t2 is I1,2. Topology requires

-I1,2 + I1,2 = 0
which is, of course, true for any value of I1,2. The device characteristic requires

-I1,2 = I.
There are therefore an infinite number of solutions all with the one current, I1,2 = -I, but with the one voltage V1 being any number at all. This is the situation we talked about. If I now declare that the one node is ground, we have


or, as it might also appear

and then there is a unique solution which is

V1 = 0 I1,2 = -I.

4.2.2 The Voltage Source

The next 2-terminal device is the voltage source with the symbol and characteristics:



Vj - Vi = V

where Vi and Vj are voltages at terminals ti and tj. V is the value of the voltage source. There are many devices that are well described by voltage sources: flashlight batteries, car batteries, the 115V wall receptacle and power supplies operated in their usual mode. Also, there are voltage regulator diodes called Zener diodes that are described well by voltage sources over a limited range of conditions. We will also analyze 2 circuits with voltage sources. First consider:



The one device has two terminals. There are no links so there are no currents and there are 2 nodes. We have, therefore, 2 voltages, V1 and V2. The topology contributes no restrictions since there are no currents. The device characteristic requires

V2 - V1 = V
There is an infinity of solutions. If we dictate that terminal 1 is ground then there is a unique solution

V1 = 0 V2 = V.
Next consider



There is one link, l1,2 and one current, I1,2. The current entering t1 is -I1,2 and that entering t2 is I1,2 so the topology requires

-I1,2 + I1,2 = 0
which is trivially satisfied. There is one node, since t1 and t2 are joined by a link, and we call the voltage at this node V1. The device characteristic requires

V1 - V1 = V
Since the voltage at terminal 2 is defined to be the voltage of the node of which it is a part, it is V1. So is the voltage at terminal 1. Except for the special case V = 0 there can be no solutions. Don't short out car batteries, power supplies or the 115V wall receptacle. The existence of the universe is at stake!

4.2.3 The Resistor

The next 2-terminal device is the resistor. Its symbol and characteristic are



Vi - Vj = R Ii

where Ii is the current entering terminal ti and Vi and Vj are the voltages at terminals ti and tj. R is the resistance of the resistor. Physically resistors are bought as such. The degree to which this mathematical idealization describes a real resistor is particularly excellent.

There is another number concerning the resistor above that is of interest. It is called the power dissipated. This number does not appear in network analysis but it is of importance for considerations outside of network analysis. The power dissipated is:

RIi = (Vi - Vj) Ii = (Vi - Vj) / R

Physical resistors have a maximum power they can dissipate without being damaged or destroyed. They generate heat and the power dissipated is exactly the heat power generated. Let us analyze one resistor circuit:

There are 3 devices containing 6 terminals. There are 3 links: l2,3, l4,5, l6,1, and obviously 3 nodes we will call N1, N2, N4 (naming them after the lowest numbered terminal in the node). Consequently, there are 3 currents, I2,3, I4,5, I6,1, and 3 voltages, V1, V2, V4. The topology requires that the total current entering each device is zero:

I6,1 - I2,3 = 0 I2,3 - I4,5 = 0 I4,5 - I6,1 = 0

The device characteristics are:

V2 - V1 = V V2 - V4 = I2,3 R1 V4 - V1 = I4,5 R2
In addition, we dictate that the node containing terminal 1 is ground so we have

V1 = 0
Looking at the first 3 equations we immediately see that if there is any solution at all, all 3 currents must be equal. (As a point of interest, you will also note that of these first 3 equations, which come from the topology, 1 equation, any one of them, is redundant. We could leave any one of these 3 equations out and lose nothing.) From the rest of it we quickly get

V1 = 0 V2 = V V4 = V (R2 / (R1 + R2))

I2,3 = I4,5 = I6,1 = V / (R1 + R2)

This is the unique solution. One further remark is that it is a little pedantic to go through this much work to analyze this simple circuit. With practice, much of it would be done on sight. For example, it should be immediately obvious that all the currents are the same and so the first 3 equations would not even be written down. With just a little experience, the whole circuit would be analyzed on sight.

4.2.4 The Diode

The next 2-terminal device is the diode:




Vi - Vj = 0.75 Volts Ii 0


Vi - Vj 0.75 Volts Ii = 0

where Ii is the current entering terminal ti and Vi and Vj are the voltages at terminals ti and tj. Notice that this device can exist in 2 distinct states. Real silicon junction diodes are reasonably well described by this piecewise linear silicon junction diode. It does not describe germanium diodes which are rather little used now. Real diodes, however, have a maximum forward current and if it is exceeded the device can be damaged. There is also a maximum value for Vj - Vi called the maximum reverse voltage. If this is exceeded, the diode will "breakdown". When diodes or other devices with multiple states are in the network the amount of work in the analysis can greatly increase. For a complete analysis of a network with one diode, one would generally assume the diode is in the "ON STATE" and analyze using the on characteristics. There may or may not be solutions. One would then assume the diode is in the off state and analyze using the off characteristics. Again, there may or may not be solutions. One may find that there are solutions only when the diode is in one state or the other, or solutions in both states or none at all. If the network contains, say 5 diodes, one would have to investigate 32 possible situations of various diodes in various states. The whole thing quickly gets out of hand. The only thing that saves us is that most of the possibilities can usually be discounted on sight. There are two remarks that can be made about diodes: The existence of two distinct states is very important. There are other devices with multiple states - some with more than 2 states. This is the origin of switching behavior in circuits. The performance of logic or switching circuits is directly traceable to these sorts of devices. Secondly, there is the magic quantity 0.75 volts. This is the silicon junction diode forward voltage drop. The number also appears in silicon bipolar transistor characteristics. It is not an absolute constant of nature. Various real diodes may show on voltages somewhat more or less than this and it also depends somewhat on the forward current. The piecewise linear model of the diode is an abstraction that is useful to model the qualitative and perhaps semiquantitative behavior of real silicon junction diodes. There are far more accurate nonlinear models which are required to get good quantitative results. These models describe a variation of the forward voltage with forward current, as well as with temperature, and manufacturing process variables, and also a tiny reverse current when the diode has a negative Vi - Vj. The 0.75 volts in the piecewise linear model is rather a typical, or rule of thumb number. It is, however, a very useful number that will come up again and again. Various notable voltages in devices or circuits, especially logic circuits, are multiples of 0.75 volts. It is therefore sort of a basic unit or quantum of voltage at least in the bipolar world. Let's analyze a diode circuit. For example

From the topology:

I6,1 - I2,3 = 0 I2,3 - I4,5 = 0 I4,5 - I6,1 = 0

It will be noticed that these are exactly the same 3 equations we got from the topology for the 2 resistor circuit we analyzed. That is because the topology is the same. Only the characteristics of one of the devices have changed. R2 is here replaced by a diode. The resistor and diode both have 2 terminals which is all the topology cares about. This being so, the conclusion is the same: all the currents are equal, which we should have known from sight. Let's just call the common value of these currents I. The device characteristics are

V2 - V1 = 5 V2 - V4 = 1 X 10 I
+ diode characteristics and V1 = 0 3

Let us first assume the diode is off. In this state the diode characteristics are

V4 - V1 0.75 I=0
we quickly find

V2 = V4
and then

V2 - V1 0.75
but above we have V2 - V1 = 5 and this certainly can never be! There is no solution with the diode off. Let us now assume the diode is on. In this state the diode characteristics are

V4 - V1 = 0.75 I0
Now we get

V1 = 0 (of course)

V2 = 5 V V4 = 0.75 V I = 4.25 ma. (milliamps)

and with the indicated assumption that node 1 is ground, the solution is unique. There is, in this circuit, a solution only when the diode is on. We therefore say that "the diode is on".

4.2.5 The Inductor and the Capacitor

I would like to mention two other important 2-terminal devices, the inductor and the capacitor. In order to make sense of these devices a new level of complication is required. Time is now involved. Speaking informally, what we want to do now is make the voltages and currents not numbers, but functions. For each time t we want to have voltages V(t) and currents I(t). In any event, we will assume for the next little while that the currents and voltages are, in general, time varying. Then the inductor is given by:



Ii is required to be continuous and differentiable almost everywhere and Vi(t) - Vj(t) = L Ii(t)
(Ii means the derivative of Ii). The Capacitor is given by:



Define VC = Vi - Vj. VC is required to be continuous and differentiable almost everywhere and Ii(t) = C VC(t)
(VC means the derivative of VC). Physical inductors are basically coils of wire. The degree to which a real inductor is modeled by the mathematical inductor varies all the way from quite poorly to very well. This depends on the particular inductor. It also depends greatly on the nature of the rest of the circuit in which it is used. In general, the mathematical capacitor is a pretty good model of those on the market. Apparently with the introduction of inductors and capacitors the restrictions on the currents and voltages become differential equations. In a large and important fraction of the cases, the equations turn out to be linear. In this case, the idea of taking the Fourier or Laplace transform of everything is popular. This leads to the concepts of frequency, impedance and all such. That process is called frequency domain analysis. If one does not take transforms then he is doing time domain analysis. I will not pursue this part of the subject any further. All real voltages and currents in real circuits take nonzero time to change values. The simple models of devices (other than the inductor and capacitor) given in this paper do not provide this. Capacitors and, to a lesser extent inductors, are frequently added to the simple models of other devices given here to produce composite devices (Section 5) that are better models of real devices. These improved models enable the networks they

are in to model the temporal behavior of real circuits. It is also perfectly OK to define better atomic models that directly incorporate temporal behavior in the characteristics. This is done too.

4.3 Three Terminal Devices

4.3.1 The Silicon Bipolar Transistor
A very important 3-terminal device is the Silicon Bipolar Transistor. It comes in 2 flavors: NPN and PNP. The NPN piecewise linear model is:

tk Collector

ti Emitter


Ij = 0 Ik = 0 Vj - Vi 0.75 volts Vj - Vk 0.75 volts Ij 0 Ik = b Ij Vj - Vi = 0.75 volts Vj - Vk 0.75 volts



Ij 0 Ik b Ij Ii bR Ij Vj - Vi = 0.75 volts Vj - Vk = 0.75 volts


Ij 0 Ii = bR Ij Vj - Vk = 0.75 volts Vj - Vi 0.75 volts

The PNP silicon transistor piecewise linear model is:

tk Collector

ti Emitter


Ij = 0 Ik = 0 Vj - Vi -0.75 volts Vj - Vk -0.75 volts Ij 0 Ik = b Ij Vj - Vi = -0.75 volts Vj - Vk -0.75 volts



Ij 0 Ik b Ij Ii bR Ij Vj - Vi = -0.75 volts Vj - Vk = -0.75 volts


Ij 0 Ii = bR Ij Vj - Vk = -0.75 volts Vj - Vi -0.75 volts

The piecewise linear mathematical transistor is a remarkably adequate description of real silicon bipolar transistors in many cases. It models the real transistor qualitatively very well, and semiquantitatively. There are more sophisticated nonlinear models that are required for accurate

quantitative modeling of real transistors. The magic number, 0.75 V. is the same magic number that is in the silicon junction diode piecewise linear model. It is a rule of thumb number here just as it was there. The Reverse Active state of the transistor is rarely used in practice. It is just like the active state but the functions of the emitter and collector are interchanged. In principle the transistor can work like this, but in manufacture it is optimized for the active state, not the reverse active state. The transistor will break down and can be damaged if the voltages, Vj - Vi and Vj - Vk are too low in the NPN case, or too high in the PNP case. This is reverse voltage breakdown. The emitter reverse voltage breakdown generally happens at a very small reverse voltage of perhaps 2 V. or less (with the appropriate sign) in Vj - Vi. Generally the collector reverse breakdown voltage is very much higher. This is one of the reasons why the Reverse Active State is generally regarded as not very useful. The other 3 states: cutoff, active and saturated, are all useful states and designs routinely use all of these states. It can be seen that the transistor is characterized by two parameters (which conveniently turn out to be dimensionless): b, bR, Beta, and Reverse Beta. Transistor manufacturers will almost never specify Reverse Beta, and almost never test it. This is in keeping with the view that the Reverse Active state is not very useful. bR also appears in the Saturate State characteristics in an inequality that describes the boundary between the Saturated State and the Reverse Active State. In most practical cases it would be good enough to simply use 0 for bR. This would make a part of the range of the Saturated State unavailable, namely that part where the emitter current is reversed. This is usually not a very useful part of the saturated state. In any event, we will usually not have any good number for bR. For most practical purposes b is the one and only parameter for the piecewise linear silicon bipolar transistor. The beta of a small signal audio preamplifier transistor may be 250-1000. Power transistors and switching transistors normally have lower betas like 25-150. The transistor beta is not a "well controlled parameter". Different units from the same manufacturer and with the same type number may have much different betas. The parameter also depends on temperature and other factors. Consequently, it is poor design practice to make the performance of a circuit depend on the betas of the transistors. Techniques for making circuit performance depend mainly on resistor values, for example, and be almost independent of betas, are highly developed. Just for information, bR for a transistor is typically less than b by a factor of 10 to 50. A transistor with a b of 250 - 1000 could well have a bR of 5 to 50. But, as we said, bR is usually unspecified. One example transistor circuit will be analyzed in complete detail:

From the topology we have

I10,11 - I1,2 = 0

I1,2 - I3,4 = 0 I3,4 - I5,6 + I9,10 - I10,11 = 0 I5,6 - I7,8 = 0 I7,8 - I9,10 = 0
from which we immediately deduce

I1,2 = I3,4 = I10,11 I5,6 = I7,8 = I9,10

Thus there are two significant currents which we can take to be I3,4 and I5,6. The ground node identification gives

V9 = 0
The device characteristics are

V1 - V9 = VIN V1 - V3 = R1 I3,4 V5 - V7 = R2 I5,6 V7 - V9 = VPWR

+ transistor characteristics. We can deduce that

V1 = VIN V7 = VPWR V3 = VIN - R1 I3,4 V5 = VPWR + R2 I5,6

A. Assume the transistor is off.

I3,4 = 0 I5,6 = 0 V3 .75 V3 - V5 .75

We then find

V3 = VIN V5 = VPWR VIN .75 VIN - VPWR .75

In the usual application of such a circuit VPWR is positive and VPWR VIN. VPWR, in fact, would normally be the "power supply". In that case VIN - VPWR .75 is always satisfied. We then learn that the transistor will be cutoff if the "input voltage", VIN, is less than .75 V., and under these conditions, the "output voltage", V5, = VPWR, the "power supply voltage". B. Assume the transistor is active

I3,4 0 -I5,6 = b I3,4 V3 = .75 V3 - V5 .75

We find

I3,4 = (VIN - .75) / R1 V5 = VPWR - R2 b (VIN - .75) / R1 VIN .75 VIN .75 + VPWR R1 / (b R2)
The transistor will be active if the "input voltage", VIN, is between

.75 volts
and .75 + VPWR R1 / (b R2) volts. In this case the "output voltage", V5, is

VPWR - b (VIN - .75) R2 / R1

Notice that the "output voltage" depends on b. It would be a poor design practice to use this circuit in the active state.

C. Suppose the transistor is Saturated.

I3,4 0 -I5,6 b I3,4 I5,6 - I3,4 0 V3 = .75 V3 - V5 = .75

Here I have said it is good enough to just use 0 for bR. We can then find

V5 = 0 I3,4 = (VIN - .75) / R1 VIN .75 VIN .75 + VPWR R1 / (b R2) VIN .75 - VPWR R1 / R2

Assuming VPWR > 0 and b > 1, which would be the case in practical situations,

VIN .75 + VPWR R1 / (b R2)

is the strongest condition. Thus, if VIN satisfies this condition then the transistor is saturated and the "output voltage", V5 = 0. Notice that the conditions for the various states meet nicely.

VIN .75 .75 VIN .75 + VPWR R1 / (b R2) VIN .75 + VPWR R1 / (b R2)

=> Off => Active => Saturated

There is a unique solution to the network for all values of "input voltage", VIN.

This circuit would normally not be used in the active state because the output depends on the relatively unreliable parameter b in the active state. Instead this circuit is normally used in systems where the input, VIN is always either less than .75 or else large enough to saturate the transistor. VIN may change from one of these conditions to the other from time to time which will cause the transistor to switch between the cutoff and saturated states. The output, V5, in the cutoff and saturated states (0 and VPWR) does not depend on b. For a transistor, b is known approximately. A given transistor may be guaranteed by the manufacturer to have b between 50 and 150. The other parameters (R1, R2, VPWR) would be chosen so that for worst caseb (50), the high level input voltage would be sufficient (and an added safety margin besides) to cause saturation. A very similar circuit

is found to be a good design choice for operation in the active region. The output of this circuit, V5, is nearly independent of b in the active state, provided that b is large, say more than 100. It has less desirable properties for use as a switching device between the cutoff and saturated states.

4.3.2 The MOSFET

An important 3 terminal device is the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) which is also known as an Insulated Gate Field Effect Transistor (IGFET). Such devices come as Enhancement Mode or Depletion mode. We will be talking only about the Enhancement Mode devices.



Source Full Symbol Simplified Symbol

(VT is positive)

Vj - Vi VT

Vj - Vk VT Ij = 0 Ik = 0

Vj - Vi > VT Vj - Vk VT Ij = 0 R Ik = Vj - Vi - VT


Vj - Vi > VT Vj - Vk > VT Ij = 0 R Ik = Vk - Vi



Source Full Symbol Simplified Symbol

(VT is negative)

Vj - Vi VT Vj - Vk VT Ij = 0 Ik = 0


Vj - Vi < VT

Vj - Vk VT Ij = 0 R Ik = Vj - Vi - VT

Vj - Vi < VT Vj - Vk < VT Ij = 0 R Ik = Vk - Vi

5. Composite Devices
Modern networks may often contain thousands or even millions of devices (consider a modern large scale computing system). The conceptual problem of dealing with any system consisting of so many parts is staggering. A better approach is to invent new devices that are built from a manageable number of previously known devices - and then still bigger devices composed of a manageable number of the previously invented composites. This process can be continued indefinitely. One can then analyze all networks (even entire computer systems) in terms of a more reasonable number of pieces. In this presentation of network analysis, the idea of a device is fundamental. In addition, there are practically no restrictions on what can be a device. All that is necessary is that the characteristics of the device be known. In particular, any combination of other devices can be defined and certain of the terminals be designated as "externally available", and then if the characteristic can be found, this composite can be considered a device. From then on, one need never be concerned with the internal details of the composite device - the characteristic is sufficient information. Now the characteristic of a device is exactly the set of restrictions that are placed on the possible set of solutions to any network that contains the device. The other devices in the network may have characteristics, but if so, this only reduces the number of possible solutions still further. In any case, the solution set for the network will be a subset of the possible solutions that are permitted by the characteristics of any one device. Suppose that a network contains a composite device with some characteristics and all the other devices have no characteristics at all. This network will have the largest solution set of any network containing the composite. In fact, the solution set of this network is just a way of expressing the characteristics of the composite itself. This gives a method for finding the characteristic of a composite. Make a complete network by connecting all the "externally available" terminals of the composite to a device with the required number of terminals (device X). Device X should itself have no characteristics at all and hence, be completely general. Device X represents the collection of all the other devices in any network that contains the composite. Any network that contains the composite would differ from this at most by the addition of more characteristics and hence, would have a smaller solution set. The network containing a composite and device X is a complete network and therefore, can be analyzed in the usual way. Its solution set is exactly the characteristics of the composite. For example, consider the composite device consisting of two resistors in series:

ti and tj are "externally available". tm and tk are not externally available. To find the characteristics of the composite, connect it to device X which has two terminals and no characteristics.

The solution set of this network is the characteristic of the composite. We have from the topology

In,i - Ik,m = 0 Ik,m - Ij,p = 0 Ij,p - In,i = 0

The device characteristics are

Vi - Vk = In,i R1 Vk - Vj = Ik,m R2
Ik,m and Vk are internal variables that are not observable from the externally available terminals. Ij,p, In,I, Vi and Vj are externally available variables. We want to put the set of equations for this network in a form in which each internal variable is expressed in terms of only external variables in one equation per internal variable. Then the internal variables are eliminated from all the rest of the equations and inequalities using these. In this specific case we can write

Ik,m = In,i Vk = Vi - In,i R1

Then using these,

In,i - Ij,p = 0 Ij,p - In,i = 0 Vi - In,i R1 - Vj = In,i R2

If we are successful in putting the equations in this form, as we were in this case, then the equations in which an internal variable is expressed in terms of external variables are not retained in the characteristics of the composite. These are not constraints on the external variables. They say for given values of the external variables what values the internal variables must be. Of the 5 equations above this gets rid of the first 2. We also do not retain equations that are redundant with the current balance equation for this composite device. Equations redundant with the current balance equation for this composite device will add no constraints when this composite is used in a network. Of the 5 equations above, this gets rid of equations 3 and 4. Only equation 5 is left as the composite device characteristics. We call In,i simply Ii, the external current entering terminal I of the composite device. The composite device characteristic, with a little rearrangement is:

Vi - Vj = Ii (R1 + R2)
This composite has exactly the same characteristic as a single resistor of value R1 + R2. It could well be said that the elimination of internal voltages and currents from the composite device characteristics represents the whole value of making a composite device. If you cant eliminate any internal variables, you gain nothing. This is the only way that a network containing the composite gets to be any simpler than that network with all the stuff that the composite is made of exposed. There may be cases in which the internal currents and voltages cannot be expressed in terms of the external variables. This could be because there is no solution to the test network made with device X, or it could be for other reasons. If the test network has no solutions, then any network containing this composite cannot have any solutions. The composite device itself is internally contradictory. If there are other reasons that some internal variable cannot be expressed in terms of external variables only, then this internal variable cannot be eliminated from the rest of the equations. In this case, the internal variable that cannot be eliminated is state internal to the composite device. This state may appear in its characteristics.

6. Numbers of Equations and Independence of Equations

6.1 The Essentials
For almost all practical purposes, including even writing a program to do circuit analysis, even a quite sophisticated circuit analysis program, what you need to know is this: Write one equation for each device that says the total current entering that device is 0. One of these equations will be redundant. Which one? Any one. Pick any one of these current balance equations arbitrarily and throw it away. Add an equation that fixes the voltage of 1 arbitrarily chosen (or maybe predesignated) node at any arbitrary value (0 if that was defined in the network). For each state of all devices, add the device characteristic equations for all devices. These are exactly the equations that you want for this network in this state. If the equations are inconsistent, then they are supposed to be inconsistent. There will then be no solution in this state, and there should not be a solution in this state. If the equations are redundant, then they are supposed to be redundant. It is also possible that there may be fewer equations than unknowns (voltages and currents). This happens only for multiply connected networks, which you may consider real odd balls. But, if this is so, then it is supposed to be so. In either of these 2 cases, if there is a solution in this state, there will be an infinite set of solutions in this state. There truly are free parameters for this network. You may then be able to add arbitrary conditions such as fixing certain voltages or certain currents, and arrive at a unique solution. Whatever you get with these equations, it is absolutely not the case that you have somehow not picked the right equations, and if you had been smart enough to pick the right equations, they would be independent. You have the right equations and they are telling you the truth. Or, you may find that the equations are independent and consistent and there are just as many equations as unknowns (voltages and currents). Then, if all the devices are piecewise linear devices, so the equations are all linear, there will be a unique solution. If there are nonlinear equations, that is perfectly OK, but it is much harder to say anything in general about the uniqueness of solutions. The rest of this section goes into this in more depth. There is no need to look at this in more depth for almost all practical purposes. If you are not particularly interested in all the nitty gritty, I suggest you skip the rest of this section. In the event that you really are interested and want to see all the dirty laundry, then please enjoy it.

6.2 Topology
6.2.1 Summary
Suppose we have a network topology with T terminals, D devices, and L links. In the following we will show that, under reasonable conditions, there will be N = T-L nodes. You can see this easily by just thinking about adding links one by one to a bunch of terminals. (Under reasonable conditions) each link you add connects another terminal to an existing node, where you can consider a single terminal to be an existing node. To begin with, we have N nodes each starting out with one terminal. The L links use up L terminals connecting them to the N nodes, so T = N +L. From this we can see that we will have L unknown currents and N unknown voltages for a total of L+N = T total unknowns. The topology gives us D current balance equations. One of them is redundant (any one of them). So we through away one equation picked arbitrarily. But, we add one equation that says that the voltage of some arbitrary node is some value, for example 0. We still have D equations. In general, a device with u terminals will have u-1 equations in each state in its characteristics. Each device then has 1 terminal that gets it no equations, but each terminal after that gets it an equation. So there are D terminals that did not get us any equations. All of the rest of the terminals got us equations. So there are T-D device characteristic equations in each state. The topology plus picking a node to call ground got us D equations. There are T-D equations from device characteristics. The total equation count is T. It is, of course, very fortunate that, at least under reasonable conditions, we get exactly the same number of equations in each state as there are unknowns. Under reasonable conditions there is one unknown and 1 equation for each terminal. The work to follow determines exactly what are these reasonable conditions under which this happens, and exactly what happens under not so reasonable conditions. Then there is the very big question of whether these equations are independent or not. We already know the answer; sometimes they are and sometimes they are not. They are independent when they should be and they are dependent when they should be. We show that it is certainly not a matter of doing a poor job of picking the equations. These are the right equations, giving us the right message. There is no better choice of equations. Here we try to get much more specific and more detailed about what is going on when the equations are not independent. Exactly what does it mean and how do we get useful results.

6.2.2 Independence of the Current Balance Equations

We define that all of the terminals that belong to a single device are connected. We also define that if there is a link from terminal a to terminal b, then terminals a and b are connected. Next we define that if terminal a is connected to terminal b and terminal b is connected to terminal c, then terminals a and c are connected. Thus if you can get from terminal a to terminal b by any path from terminal to terminal that either goes through a device or through a link, then terminals a and b are connected.

Define that a Network Topology, N, is fully connected if every terminal in N is connected to every other terminal in N. If a Network Topology, N, is not fully connected, then the devices can be put in mutually exclusive groups such that each group of devices is fully connected within the group. In fact, there is a unique way to do this such that no terminal in one group of devices is connected to any terminal in another group of devices. These groups of devices are totally isolated from each other. We may call these groups Subnetworks. A subnetwork is then fully connected within itself and not connected to any other subnetwork of the network Topology. Theorem: If a Network Topology, N, has d devices in it, then we get d equations that express that for each of the d devices, the total current entering that device is 0. Equation x for device X, is a linear combination of the equations for the other devices in the same subnetwork as device X. Proof: Suppose we wrote all of the equations that say the sum of the currents entering device d is zero, for all of the devices in a subnetwork S. We want to look carefully at what this list of equations looks like. Each link L has a current IL that goes from some terminal, t, on some device in S to some terminal, u, on some device in S. Terminals t and u must be in S because there is no connection from any device in S to anything outside of S. L contributes a current out of one terminal, t, and into one terminal, u. L therefore causes exactly 2 terms to appear somewhere in the list of equations. The equation for the device containing terminal t gets a term -IL and the equation for the device containing terminal u gets a term IL. It is possible that terminals t and u are in the same device; it is even possible that terminals t and u are the same terminal. If t and u are in the same device, then the terms IL and IL go in the same equation where they cancel each other out and both disappear. If t and u are in different devices then the terms IL and IL go in different equations. Either there will be no term involving IL in any form, including IL, or else a term involving IL will appear exactly twice in the whole list of equations, once as IL and once as IL. It will be so for every link in the subnetwork S. We can conclude from this that if we add all of the equations, one for each device in S, what we get is 0 = 0. The right hand side of all of the equations is 0, to that clearly adds up to 0. On the left-hand side, for each term, IL, an exactly matching term, -IL, occurs somewhere in the list to cancel it out. Now suppose that in the list of equations, one for each device in S, we pick any equation. Lets call it e. Suppose we add up all of the other equations except e. We must get exactly -e. We know that because if we now add e in as well, we get 0 = 0, as we just showed. Hence, equation e is exactly minus the sum of all the other equations. This shows equation e is a linear combination of the current balance equations for the other devices in S. Theorem: If a Network Topology, N, has d devices in it, then we get d equations that express that for each of the d devices, the total current entering that device is 0. Let Q be the list of such equations for a subnetwork, S, of N. Pick any equation, e, in Q. Let P be the list of equations Q, with e removed. All equations in the list P are linearly independent. Proof: Suppose the theorem is not true. Then there is an equation, x, in P which is a linear combination of a set of other equations, R, in P. We can then say that a linear combination of the equations R together with x exists that is 0 = 0, no matter what the values of any of the link currents. Let N be the set of equations in Q which are not x, and not in R. There is at least one equation in N: e. There may or may not be any other equations in N. Consider the set of devices, D, that correspond with the equation, x, and the list of equations, R. I claim that there could not be any link from D to E, where E is the set of devices corresponding to the equations N. Suppose there was such a link, L. Then a term involving IL must occur exactly once somewhere in the equations, R, or equation x. It may have a + or - sign but it would appear just once. The other matching term involving IL would appear in the equations, N, with some sign. By assumption, a linear combination of equations R and x is 0 = 0, and there is a nonzero coefficient in front of each equation, R and x. There could be no way to make this single occurrence of IL go away. These equations could not sum to 0 = 0. Hence there must be no link connecting the non-empty set of devices E and the non-empty set of devices D in S. But S is a subnetwork and is therefore fully connected. It cannot have devices D and E in it that are not connected. We must conclude that the assumption that the theorem is false is incorrect and in fact the theorem is true. If a bunch of devices are connected together and we single out any device, we can ask what is the total current entering this device? Current in a link is always flowing from somewhere to somewhere else. It cannot go into one device without coming out of another. So the answer is that the total current entering this device is the same as the total current leaving all the other devices. If we have already said that the total current leaving all the other devices is 0 (because the total current leaving each one of them individually is 0), this implies that the total current entering the selected device is 0. It is then redundant to say that again. So it makes sense. This tells us that when we write the equations, one for each device, that says that the total current entering that device is 0, we can always arbitrarily pick any one of those equations and leave it out. If it turns out that the network is not fully connected, you can arbitrarily pick one equation from each subnetwork and leave it out. It is only fair. A network with 2 subnetworks is exactly like two completely separate networks that you might write equations for separately and solve separately. If you did the 2 subnetworks as two completely separate problems, in each problem you could leave out 1 equation. So if you choose to do them both together you can also leave out 2 equations. If a Network topology is not fully connected, we will find that we can pick the voltage on one node arbitrarily in each subnetwork. There will be no restrictions on the voltages except on the differences between voltages of nodes in the same subnetwork.

6.2.3 Equation Counting

Let N be a node in a Network Topology. We say node N is Simply Connected if there is no link that could be removed and still have all of the terminals of N connected by links. If N is not simply connected then we say N is Multiply Connected. If every node in a Network Topology is simply connected, then we say that the Network topology is simply connected. If one or more nodes are multiply connected, then the Network Topology is multiply connected. If N is multiply connected then there is more than one route one could take along links to get from some terminal, t, to some terminal, u, in N. Since this is true, there is a closed loop somewhere following links among the terminals in N. In a degenerate case, a link may connect a terminal, t, to itself. This makes the node containing t multiply connected. The node containing t might also contain other terminals or it could just contain t. In a multiply connected node, since there is more than one route from some terminal, t, to some terminal, u, some of the current from t to u takes one route and some takes another route. Circuit analysis will have nothing to say about how much goes one way and how much goes the other way. All of the equations of the topology only involve the total current from t to u. Even the device characteristics of any device cannot tell by which route the current arrives; they involve only the total current entering a terminal. If we have a set of currents that satisfies the Network, then we can subtract any current from the current along one path and add it to the other and we still have a solution. In fact, there can be an arbitrary amount of current circulating in the loop of links. This does happen in physical reality. In actual, physical circuits, there are sometimes redundant wires, sometimes put there intentionally for various reasons, and sometimes by accident. There can be very good reasons (that are beyond the scope of this paper) for having redundant connections. In the cases where this does happen, in fact, it is not known how much of the current takes one path or the other. In actual fact there can be arbitrary currents circulating around the closed loop. We can get this under control by actually modeling the wires as devices rather than as just links. If the wires are accurately modeled as devices, circuit analysis can tell us how much current is going one way or the other and even how much current is circulating. Suppose we have a Network Topology with T terminals, D devices and L links. We already know that there are L unknown currents, one in each link. We would like to know how many nodes there are because that will tell us how many unknown Voltages there are. Think of starting with T terminals and no links so that each terminal is a node. There are therefore T nodes. Now add links one by one. I argue that if the network will be simply connected, then I can add links in such a way that each time I add a link, a single terminal is joined to some other node. This means that that single terminal is no longer a node by itself. Hence with each added link, the number of nodes is decreased by 1. When we are finished, we must have N=T-L It remains to show that links can be added in such as way that each link joins a single terminal to some other node. First, partition the T terminals into groups that will be the nodes. Within each group, we will have a set of terminals at each time, which we call the growing node. All terminals in the growing node are connected by links. Initially pick any arbitrary terminal in each group and let that be the growing node for the group. Now we add a link. I must always be able to choose to add a link that connects to the growing node. If that was not possible then there are no links that connect to a growing node. This means there is no link that connects the remaining terminals in this group to the growing node. This group cannot form a node then, since not all terminals are connected. But, by assumption, this group will form a node. Hence, it must be true that I can choose to add a link that connects to the growing node. The other end of this link cannot connect to the growing node. This is because all terminals in the growing node are already connected. If I add a link that connects from the growing node to the growing node, then the growing node will be multiply connected. This means the finished node that this group becomes will be multiply connected, contrary to assumptions that this network is simply connected. The link I add therefore connects the growing node with some terminal that is not yet part of the growing node. The only other terminals in the group are single, unconnected terminals. So this link will cause 1 single unconnected terminal to be added to the growing node.

Observe that there are then N unknown voltages and L unknown currents. The total number of unknown variables is N + L which is exactly T, in a simply connected Network topology. If the Network topology is not simply connected, the number of unknowns, N + L, will be greater than T. Consider the argument above. We add a link that connects to a growing node. But one or more such links now connect from the growing node back to the growing node. Such a link does not add a new terminal to the growing node. This means that we will have to add an additional link to use up all the terminals in the group. If the network was simply connected L = T N. If the network is multiply connected it will take more links so L > T N. If the network is simply connected the number of unknowns, L + N, is T. If the network is multiply connected the number of unknown, L + N, is more than T. Now, how many equations do we have? The Topology gives us one current balance equation for each device. We therefore have D equations. We know they are not all independent. Even in a fully connected network, one is redundant, so we have D-1. If the network is not fully connected, then there are even fewer independent equations. In fact if the network has S subnetworks, then we have D-S independent current balance equations. A fully connected network consists of exactly 1 subnetwork so S is 1, in this case.

We assert that we can arbitrarily dictate the voltage of S nodes. This represents S more equations (very simple equations to be sure). If we do this, then we again have D independent equations from the Topology. Now it is up to the devices.

6.3 Devices
A fully defined, piecewise linear device with t terminals will have t-1 device characteristic equations in each state, not counting inequalities which serve to determine which states are possible. The Tie Point, a 1 terminal device, had no characteristics. The two terminal devices all had one equation in each state, the three terminal devices, the transistors, had 2 equations in each state. Go back to our Network Topology with D devices, and T terminals. All of the terminals belong to some device. We get one equation with each terminal, but for each device, we get shorted by one. The total piecewise linear device characteristic equations are T-D There were D independent equations from the Topology + ground reference choices. The total is therefore T. Conveniently there are also T unknown voltages and currents, if the network is simply connected. If the network is multiply connected, then there are more than T unknowns and there are not enough equations to go around. But, as we said, if the network is simply connected then we have T unknowns and T equations. Ah, but are the device characteristic equations all independent, and independent of the equations from the Topology? A device is defined to be internally disconnected if one or more of the equations that constitute its characteristics express that the total current entering some subset of its terminals is zero. It must be possible to show that the total current entering this subset of terminals is 0 from the characteristics alone, not using the current balance equation for the device from the topology. An internally disconnected device has characteristics that demand that a subset of its terminals forms a semidevice. Note that we may find that certain terminals of a device form a semidevice in certain circuits by virtue of the circuit. This does not make the device internally disconnected. To be internally disconnected, the characteristics of the device itself must make a subset of its terminals a semidevice independent of what circuit it is used in. We have already seen a trivial example of an internally disconnected device: the MOSFET. In each state, one of the equations of its characteristics is that the gate current is zero. Technically this makes it an internally disconnected device. As a practical matter though, a semidevice consisting of 1 terminal is not very interesting. A better example is a new device called the Ideal Transformer. The ideal transformer is a model of physical transformers. A physical transformer is a fundamental device in that it is not made out of parts that are circuit devices. The Ideal Transformers symbol and characteristics are

Ij = - Ii N Il = - Ij Vl Vk = N (Vj Vi)

The single parameter, N, is called the turns ratio. It can be any real number, positive or negative or 0. A turns ratio of 0 is a degenerate case of limited interest. Notice that it has 4 terminals and, as expected, 3 equations in its characteristics.

The characteristics directly define that one pair of terminals, (ti, tj), will be a port, i.e. the total current entering terminal i and terminal j is 0. When the transformer is used in any network, including the trivial network that contains it alone and nothing else, the topology will demand that the total current entering the ideal transformer is 0. This will imply that the other pair of terminals also forms a port. The ideal transformer is therefore a 2 port, enforced by its own characteristics. There are other fundamental devices that are internally disconnected. In addition, a composite device can be internally disconnected. This can happen if the composite device contains an internally disconnected device, or if it is a network topology that is not fully connected, as we defined in the beginning of this section. It may also be noted that devices can become internally disconnected sort of by accident. For example an ideal current source is normally not internally disconnected but if its strength just happens to be 0, then it is internally disconnected. All of the transistors are internally disconnected in the cutoff state. The diode is internally disconnected in the off state. Lets use the ideal transformer as our example of an internally disconnected device, and see how it might be used in a network. The transformer could be used in a network like this

In this case, all of the devices in the network besides the transformer have been put into 2 groups. Group of devices A is connected to one port of the transformer and group of devices B is connected to the other port of the transformer. Anything you want can be in group of devices A or group of devices B. It is important in this example that there is no connection whatever from group of devices A to group of devices B, except by virtue of them being connected to the transformer. There is no connection between one port on the transformer and the other port on the transformer except whatever is internal to the transformer itself. In this example, one of the equations of the transformer characteristics will say that the current entering the first port must be 0. The topology provides a current balance equation for each device in group A. The effect of all of those current balance equations is also to require that the total current entering the first port of the transformer is 0. This is because the total current entering all of the devices of group A must be exactly the total current leaving the transformer port to which they are attached, since they are not connected to anything else. Then if one is 0, the other must be 0. This shows that the equation in the transformer characteristic that says the current entering the first port is 0 is redundant with the equations from the topology for the devices in group A. And we still have for the whole network, that one of the current balance equations is redundant besides, as is usual. Suppose we write the equations for this network as we usually do. From the topology we write one equation for each device stating that the total current entering that device is 0. We know that one of these equations is redundant. In usual fashion, we pick one of these equations arbitrarily and throw it away. In usual fashion we pick one node arbitrarily and we write 1 equation that arbitrarily fixes the voltage of that node. Then we add all of the equations of the device characteristics in some particular state of the whole system. If T is the number of terminals, the total number of current

and voltage unknowns is T. We also now have T equations. These equations are, however, redundant as we just saw from the previous paragraph. The solution to the equations (if any) will not be unique. In fact, in the case being considered, there will be one free variable. It will be a voltage. In this case, it will be possible to arbitrarily dictate the voltages of not just 1 node, as we usually do, but 2 nodes. You can arbitrarily pick any node on the left including in the group of devices A, or the first port of the transformer, and dictate that it shall be any arbitrary voltage. Then you may pick an arbitrary node on the right including in the group of devices B or the second port of the transformer, and dictate that it shall be any arbitrary voltage. If the rest of the network is reasonably normal then we can get a unique solution (at least in states for which there are any solutions). In effect, the internally disconnected device, the transformer, has split this network into 2 disconnected pieces even though, in the topological sense, this is a fully connected network. It would be clear that this is happening if, instead of the transformer, we had a composite device there that was internally disconnected because it was itself a network that is not fully connected, and we could see inside the device to see that. The transformer does this disconnection in a very nice way. The left and right sides of the network still greatly influence each other. The voltage across one port of the transformer determines the voltage across the other port. The current passing through one port determines the current passing through the other port. But it is disconnected in the sense that everything on the left, for example, may be within a few volts of 0, while everything on the right may be within a few volts of 10,000 volts. A transformer is sometimes used exactly for the purpose of dividing the network so that there is an arbitrary voltage on each side, exactly as happened in this example. For this use, it is crucial that the transformer is internally disconnected and that is what makes it useful. A transformer is also frequently used for other purposes and it doesnt really matter if it is internally disconnected or not. Now lets consider a slight variation on the previous network. Here we see the same network with all the same devices, but we have added 1 more link that was not in the previous network. This link connects one terminal of the first port of the transformer to one terminal of the second port of the transformer.

Now the network topology equations that say that the total current entering all the devices in group A is 0 are not saying the total current leaving the first port of the transformer is 0. There is another place for that current to go: the link we added. We will now find that the equation in the ideal transformers characteristics that says that the total current entering its first port is 0 is NOT redundant with the current balance equations for the devices of group A. This is proven formally for the general case below. The crucial factor here is that the left and right sides of this network cannot be effectively disconnected, even though the transformer is internally disconnected, because there is a link from the left side to the right side. Note also that we could no longer have everything on the left within a few volts of 0 and everything on the right within a few volts of 10,000 volts. Some things on the left and right are now part of the same node and must be at a single voltage. There is no longer freedom to pick an arbitrary voltage on the left and right. Instead of just a link, we could have added a voltage source that would maintain a 10,000 volt difference between one terminal of the first port of the transformer and one terminal of the second port of the transformer. The stuff on the left would then be all within a few volts of 0, for example,

while all the stuff on the right would all be within a few volts of 10,000 volts. This network is now not effectively disconnected, but this indicates one way that the transformer, with its internally disconnected characteristics, can be useful.

So, if internally disconnected devices are used in networks this may or may not lead to their device characteristics being redundant with the equations of the topology, depending on how they are used. If the rest of the network connects up the things that these devices effectively leave disconnected, then their characteristics are not redundant with the topology. If the network fails to connect together things that these devices effectively leave disconnected (which can happen), then certain device characteristics will be redundant with the topology, leading to free variables in solutions. Definition: Let N be a network containing a device, D. Let S be a subset of the terminals of D. We define that each Terminal in S is connected to S, with respect to D. If terminal a is connected to S, with respect to D, and there is a link between a and b (regardless of the direction of the link), then terminal b is connected to S, with respect to D. If a is a terminal of device X in N, and a is connected to S, with respect to D, and b is also a terminal of X, and X is not D, then b is connected to S, with respect to D. Further define that a device X is connected to S, with respect to D, if X is not D and any terminal in X is connected to S, with respect to D. We can observe that if device X is connected to S, with respect to D, then, in fact, all terminals of X will be connected to S with respect to D. The concept of terminals a and b being connected, with respect to D, is just like the original concept of connected except that the one device, D, does not cause its terminals to be connected, with respect to D. All other devices connect their terminals, with respect to D, but device D does not. Definition: Let S be a subset of the terminals of a device D. Then D S is the set of terminals of D that are not in S. Theorem: Let N be a network containing a device D. The current balance equations of the network topology, N will be redundant with the characteristics of D if there exists a subset, S, of the terminals of D such that: 1. The characteristics of D alone imply that the total current entering S is 0, and 2. Each device of N that is connected to S, with respect to D is not connected to D S, with respect to D. More specifically, the current balance equations for the devices that are connected to S, with respect to D are redundant with the equations in the characteristics of D that are sufficient to imply that the total current entering S is 0. Proof: Suppose that there is a subset, S, of the terminals of a device D in a network and that properties 1 and 2 in the statement of the theorem are true. Let A be the set of devices that are connected to S, with respect to D. Let B be the set of all devices in N, not including D and not including the devices in A. I assert that there is no link from any device in A to any device in B. Suppose this is not true. Then there is a device, x, in B that has a link from one of its terminals to a terminal, a, of a device in A. Terminal a is connected to S, with respect to D. This would mean that x is connected to S,

with respect to D. Hence x is in A and cannot be in B, contrary to assumptions. It is established that there is no link from any device in A to any device in B. By property 2 above, there is no link from any device in A to any terminal of D other than those in subset S. Similarly it is easy to show that there is no link from any terminal in S to any device in B. If there were such a link then some device in B must actually be in A and could not be in B. It follows that the devices in A have no links to any terminals outside of A except for terminals in S. Terminals in S have no links to any terminals outside of S except to devices in A. The current balance equations for all of the devices in A all added up must reduce to an equation that exactly says the sum of the currents leaving the terminals in S is 0. This is because for all links entirely within A, the link currents appear exactly twice in the equations, once with each sign. When we add up the equations these all cancel out. The links between devices in A and terminals in S have currents that all appear exactly once in these equations. When the equations are all added up we get the equation that says the sum of the currents in links between A and S is 0. There are no links from terminals in S to anywhere else outside of S. Hence this is exactly an equation that says the total current leaving S is 0. We have shown that if we have N, D and S with properties 1 and 2 then the equations of the topology are redundant with the characteristics of D and specifically that the current balance equations for the devices in A are the equations from which we can show that the total current entering S is 0. Hence there is no need to be able to conclude from the device characteristics of D that this is true. We would like very much to be able to say that D being internally disconnected and the network suitably maintaining this disconnect is the only way the characteristics of D can be redundant with the topology. The above theorem would then be an if and only if theorem. It is almost true, but unfortunately not quite true. There is also a bizarre situation in which the characteristics of D imply that some linear combination of currents entering a subset, S, of the terminals of D equals 0. This linear combination could be other than just the sum of the currents entering the terminals in S. Hence D is not necessarily internally disconnected. If it is connected to a network in just the right way, the characteristics of D can be redundant with the topology. Theorem: If D is a device in a network, N, and the equations of the characteristics of D are redundant with the current balance equations of the topology of N, then there is a subset, S, of the terminals of D such that the characteristics of D imply that a linear combination of the currents entering terminals in S is 0. Let the terminals in S be divided into groups, S1, S2,, SK, such that the linear combination of currents has the same coefficient for currents entering terminals in the same group. Currents entering terminals in different groups appear in the linear combination with different coefficients. Then the devices connected to Si, with respect to D are not connected to D - Si, with respect to D. Note that if we could have asserted that all the coefficients were the same, then we would have what we would like. But, we cannot show that the coefficients will all be the same. Proof: Let E be an equation, derivable from the characteristics of D, that is redundant with the topology of N. Then E is exactly the sum of cj ej where ej is a current balance equation of the topology of N, and cj is a constant. j runs from 1 to some number J. A linear combination of current balance equations will have the form, some linear combination of link currents = 0. Hence E must be of the form, some linear combination of currents = 0. These currents can only be currents entering a subset of the terminals of D. Let S be the set of terminals of D whose currents have non-zero coefficients in E. This is the first part of the theorem. Divide the terminals of S up into groups S1, S2,, SK, such that the linear combination of currents has the same coefficient for currents entering terminals in the same group. Currents entering terminals in different groups appear in the linear combination with different coefficients. Let Ai be the subset of devices of N that are connected to Si, with respect to D. Suppose Ai were connected to D - Si, with respect to D. This can be only if there is either a link from Ai to D - Si, or else there is a link from Ai to some other device so the trail eventually leads to D - Si. If there was a link from Ai to some other device, then this device too would be connected to Si, with respect to D, and hence would be in Ai. So there cannot be a link from Ai to some other device. There must then be a link from Ai to D - Si. I assert that the equations, ej, must include current balance equations from all devices in Ai, and further, the coefficients of all of these current balance equations, cj must be the same. First suppose there was a device left out. One of the left out devices, x, must have a link to an included device or to a terminal in Si. If it connects to a terminal in Si, then this link contributes to the current entering this terminal so this link current must appear and must have the same coefficient as the currents entering terminals in Si. If it has a link to a device whose current balance equation is included, this link current would appear just once in the set of equations, cj ej. This current would not be cancelled out. But the characteristics of D could not involve such a current. Hence, the current balance equation must be included. It must have the same coefficient as all the others or this link current will not cancel out. But this means that the device with a link to D - Si must have its current balance equation in cj ej too. This will mean that the current in the link to D - Si must occur just once in cj ej, so it does not cancel out. Besides that, it must have the same coefficient as all the other current balance equations for terminals in Si. This means the terminal in D - Si is actually in Si, and cannot be in D - Si, as was supposed. This proves the theorem.

Notice that if the device characteristic that is redundant with the topology is a linear combination of terminal currents with different coefficients, so this is not a simple case of an internally disconnected device, then the network must be quite special. There must be a set of devices that connect with terminals with a certain coefficient, and this set of devices is totally isolated from all devices that connect to terminals with a different coefficient. We get an isolated group of devices for each different coefficient value. Notice that the theorem only says that we know the conditions under which the device characteristics are not redundant with the topology. Even if a device characteristic is not redundant with the topology it can still be inconsistent with the topology. For example, connect one terminal of a resistor, to one terminal of a current source to produce such a case. We dont have much to say, in general, about this. We also have the question of whether the device characteristics are independent of each other. Devices can be connected together so that their characteristics will be redundant or inconsistent, or so that their characteristics will be independent. For example, 2 voltage sources can be connected in parallel. If they happen to have exactly the same strength, then they are redundant. If they are not the same strength, then they are inconsistent. Similarly, you may choose to put current sources in series. Two diodes in series pointing the same direction are clearly redundant in the off state. It seems hard to say, in general, if device characteristics will be independent, redundant or inconsistent. It depends on how the devices are interconnected.

6.3.1 Summary
If the network is fully connected and simply connected and not disconnected by an internally disconnected device that the network does not connect around, then the equations of the topology are independent and we get as many equations in each state as there are variables. It is assumed that one current balance equation has already been discarded and replaced by an equation arbitrarily assigning a voltage to one node. This is not quite completely true. There could be a more bizarre case as we mentioned. If the network is not fully connected, then the equations of the topology are redundant with the effect that additional node voltages will be free parameters that can be arbitrarily assigned. One node voltage can be arbitrarily fixed in each disconnected piece. If the network is multiply connected, then there are more variables than equations and there is a link current that is a free variable that can be arbitrarily assigned. A network could be not fully connected and multiply connected. If there is an internally disconnected device and the network does not connect its disconnected parts, then the device characteristics of this device are redundant with the equations of the topology. A node voltage will be a free parameter that can be arbitrarily assigned. Of course, a device can have any number of internally disconnected parts and there could be any number of internally disconnected devices in a network. These are the topological situations. These are either completely topological phenomena such as not fully connected or multiply connected networks, or things closely related to the topology like internally disconnected devices. Besides this there is a whole range of non-topological situations which we say nothing at all about in general. These include device characteristics inconsistent with the topology, and device characteristics either redundant with or inconsistent with other device characteristics.

7. A Circuit Analysis Program

In this section we will outline how a simple program can be written to do circuit analysis.

7.1 Description
The program will read an input text file that describes the network. An obvious format for the input is a list of devices, say one per line, and a list of links, one per line, and a designation of which node is ground (arbitrarily set to 0 volts). The program will then analyze the network and output a (possibly empty) list of states in which there were solutions. In each state for which there is a solution, if the solution is unique, it will output the voltage at each node and the current in each link. For each device, the input line can start with the type of the device (voltage source, resistor, transistor, etc.) and then have a list of the terminals in a standard order. A terminal may be named simply with a number. After the list of terminals, the line should contain the values of any parameters that the device has in a standard order. For example, the line NPN 12 13 14 150.0 would indicate the presence of a device that is an NPN Transistor. The emitter is terminal 12, the base is terminal 13, the collector is terminal 14, and it has a Beta of 150. A link can be represented with a line containing the key word Link, followed by the two terminal numbers that it links, in from, to order. For example Link 53 14 indicates the presence of a link from terminal 53 to terminal 14. The ordering of the terminals defines the direction of a positive current in this link. Finally, the line Ground 8 indicates that the node to which terminal 8 belongs has a voltage of 0. The program could easily accept these input lines in any order, and it may be useful that the user of this program can arrange the lines to try to make the most sense of the network. The program can count the total number of terminals in all of the devices, T. It then knows that there will be T unknown variables and T equations. It can also count the number of links, L. There will be L unknown currents and T-L unknown voltages. This works only if the network is simply connected, which is an entirely reasonable restriction. It is quite possible to extend this algorithm to not require the network to be simply connected. The reader can easily see how to do it, but this is beyond the scope of this paper. The program will want to keep the links in an ordered list so there is a concept of the jth link, and therefore of the jth current variable. There are T-L nodes. The program will want to build an ordered list of nodes so there is a concept of the jth node, and therefore of the jth voltage variable. A good way to do this is with a (T-L) X T matrix. Initialize it to 0. Note the highest terminal number by scanning the devices. Use a do loop to go from 1 to the highest terminal number. For each number, check to see if it really exists in some device. Remember, there is no requirement that the terminal numbers that the user picked be dense. A particular number may not be a terminal. Skip the number if it is not a terminal. Then check to see if the number belongs to a node that you already have. If it does not, you have found a new node. Start a new row in the matrix for it. Place the terminal number in column 1 of this row of the matrix. Now scan all links. You are looking for a link that has either a first terminal or a second terminal that matches some terminal in this row of the matrix. If you find such a link, then look at the other terminal. If this terminal matches a terminal in this row of the matrix then skip it. If it does not, add it to the row of the matrix. You will have to scan the entire list of links over again. The process stops, for this node, when you have done a complete scan of the links without adding anything to the row of the matrix. You now have the complete list of terminals that are part of this node, in this row of the matrix. Now proceed to look at the next potential terminal number. Each row of the matrix will now have a list of all terminals that belong to a node, with the lowest numbered terminal in the node in column 1. The set of rows is a complete ordered list of the nodes. It will be convenient to have the ordered list of links numbered 1 to L, and the ordered list of nodes numbered L+1 to T. The program will determine the states that it must consider by the list of device types. Internally the program will keep an ordered list of devices that have more than one state. The state of the network can then be represented by an ordered list of integers, one integer for each device with more than one state. The program will go systematically through all possibilities for the states of the network. For a given state, the programs main task is to fill in a T X T matrix and a vector of length T. This matrix and vector represent the full list of equations for the network in this state. Each row in the matrix and entry in the vector represents one equation. Each column in the matrix represents one unknown variable. Columns 1 to L represent the link currents 1 to L. Columns L+1 to T represent the node voltages L+1 to T. The number at row i, column j in the matrix, mi,j, is the coefficient of the jth variable in the ith equation. The ith entry in the vector is the constant part of the equation. The program begins in a state by zeroing the matrix and the vector. Next, the program has a do loop to go through all the devices. The do loop is set up to skip the first device. This is the redundant equation that it chooses to throw away. For each other device, it will fill in a row of the matrix. The row number will be just the device number. For this, the devices

are numbered from 0, but the rows are numbered from 1. Device 0 has no row. For each terminal of the device, i, scan the list of links. If the device terminal matches the first terminal of link j, then subtract 1 from mi,j. If the device terminal matches the second column of link j, then add 1 to mi,j. Note that it is possible that a link goes from one terminal on a device to another terminal of the same device. In that case you will both add 1 and subtract 1 from mi,j, leaving it 0, which is the right thing to do. Entry i in the vector will remain 0 (the sum of the appropriate currents = 0). For row D of the matrix (D is the number of devices), find the Ground line. Get the terminal number of ground. Search the nodes matrix to find what node the grounded terminal belongs to. Say it is j where the nodes are numbered from L+1 to T. Put a 1 in mD,j. Entry D in the vector remains 0 (the voltage of this node = 0). Here you could easily implement a feature to be able to set this node to any desired voltage, not just 0. The remainder of the rows will be filled in with device characteristic equations. Scan the devices one by one. The device type determines how many equations the device will have and the device type along with its assumed state determines what they are. The tie point has no equations. The 2 terminal devices have 1 equation. The three terminal devices have 2 equations, and the 4 terminal devices have 3. This program will do only piecewise linear devices, so the equations will be linear. This means that every device characteristic will be of the form, some linear combination of voltages and currents = some constant (possibly 0). This is representable by putting coefficients in row i of the matrix and the constant in entry i of the vector, where i is the equation. A row of the matrix and a vector entry is used for each equation. When we presented device characteristics, we did not present them all in homogeneous form. For example the resistor characteristic was presented as Vi - Vj = R Ii. You will want to rewrite this as Vj -Vi + R Ii = 0, or some variation on this. If the device characteristic involves the current entering a terminal of the device, get the terminal number in question. Then all links must be scanned. If the terminal matches the first terminal in link j, then subtract 1 from mi,j. If the terminal matches the second terminal in link j, then add 1 to mi,j.. The characteristic may indicate that the current entering the terminal is multiplied by a parameter, e.g., the resistance, if the device is a resistor. If this is the case, then multiply mi,j by that parameter. If the device characteristic involves the voltage at a terminal, search the nodes matrix to find out which node the terminal belongs to. Assume this is equation i and the terminal belongs to node j, where the node numbers run from L+1 to T. Then an entry will be made in mi,j. In general the voltage is to be multiplied by a parameter. Use that value, otherwise it is 1. Then pay attention to whether the voltage should be added or subtracted, to set the sign. For all devices, the voltages will all appear in pairs, one to be added and one to be subtracted. This is because characteristics will involve only the difference in voltage between two terminals. The characteristic may say the linear combination of currents and voltages should equal a parameter or constant. For example, for a current source it should equal the strength of the current source. For a voltage source it should equal the strength of the voltage source. For a diode in the on state it should equal 0.75. These values are put in entry i of the vector. At this point, the matrix and vector are complete. Any desired linear equation solution routine may now be called to solve the equations. There are many available. It is quite desirable that the routine used is robust, in that it will not terminate, crash, or otherwise cause trouble regardless of the input it is given. It is also desirable for it to be capable of reporting that the equations were inconsistent, or redundant. If the equations were consistent and independent it will return a unique solution vector. One more task left. Assuming that a solution was obtained, the solution vector must be checked against the inequalities for each device in the assumed state. These inequalities will all be of the form some linear combination of currents entering some terminal or voltage at some terminal must be greater than, greater than or equal to, less than or less than or equal to some parameter or constant. The current entering a terminal is found by the now completely familiar process of scanning the links and adding in or subtracting the correct current from the solution vector. The voltage is found by determining what node the terminal belongs to and selecting the voltage from the solution vector. If a solution was found and the inequalities for the states all are observed, then there is a solution in this state. The states of all devices with multiple states should be reported and all link currents and all node voltages should be reported. Then continue on with other states. There may very well be solutions in multiple states. The flip-flop is a classic example of a circuit with solutions in multiple states and that is the whole basis for its usefulness. When all possible states have been tried, the analysis is complete. It there are many solutions to the equations, then it is actually more complicated. In this case, some solutions in the space of solutions to the equations may observe the inequalities, while other solutions in the space of solutions to the equations do not. You may pick a typical solution that does not observe the inequalities and be tempted to declare that there are no solutions, when in fact, had you picked a different typical solution to the equations it would have been consistent with the inequalities. In general, the problem of solving a linear system (an arbitrary collection of linear equations and linear inequalities in a set of variables) is a considerably more difficult mathematical problem than just linear equations. The right way to do this in the program is to represent not only the equations but the inequalities as well in matrix form and to call a general linear system (equations and inequalities) solving subroutine. Such subroutines are not that easy to find. For the student program, this point has been ignored so that readily available linear equation solvers can be used and the student does not have to solve the more challenging problem of solving a general linear system (with inequalities) himself. The result is that the student program will sometimes declare that there is no solution when, in fact, there are many solutions. This cant be helped without the ability to correctly analyze general linear systems.

7.2 Example
Consider the following circuit:

Input to the program would be this NPN 9 6 7 50.0 NPN 5 2 4 50.0 R 1 10 4.7E+3 R 3 11 4.7E+3 V 12 8 5.0 Link 9 5 Link 5 12 Link 1 7 Link 3 4 Link 1 2 Link 3 6 Link 8 11 Link 11 10 Ground 12 Here the betas of the two transistors are both 50.0. The program determines from the 5 lines that declare devices that there are 12 Terminals. It counts the Link lines and determines that there are 8 links. It then computes that there are 12 - 8 = 4 nodes. It then allocates storage for a matrix of 4 rows and 12 columns. To be simple this could have been a statically allocated matrix that is maybe 100 X 200, for example, of which we know we will use 4 X 12, at most, in this run. This will be the nodes matrix and the program will fill it out to look like this:

1 3 5 8

7 4 9 11

2 6 12 10

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

There will be T = 12 total unknowns and T = 12 equations in each state. Allocate a 12 X 12 array and a 12 entry vector. Again, for simplicity, the array may be just using part of a much bigger statically allocated array. Now the 5 devices are scanned. Each NPN has 4 states each, unless we choose to not implement the reverse active state (a not unreasonable choice), in which case they have 3 states each. The other three devices have only 1 state each. Hence, 16 or 9 states will be tried. For each state, equations will be set up and solved. We will look at just one state here as an example. The state we will look at is the first NPN (9 6 7 ) is cutoff, and the second NPN (5 2 4) is saturated. The matrix will look like this: +1 0 0 0 0 0 0 0 0 0 0 0 -1 0 0 +1 0 0 0 0 0 0 0 0 -1 0 0 0 0 +1 0 0 +1 0 -1 0 0 0 0 0 0 +1 -1 0 0 0 0 0 0 0 0 0 -1 0 0 +1 0 0 0 0 0 +1 -1 0 0 0 0 0 0 0 0 +1 -1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +1 +1 -1 0 0 0 0 0 0 0 0 0 0 -1 0 -1 0 0 0 0 0 +1 0 0 -1 0 0 0 -1 0 0 0 0 0 0 0 0 0 +1 +1 +1 0 0 0 0 0 0 0 0.75 0.75 0 0 5.0

0 -4700 0 -4700 0 0 0 0 0

0 -4700 0 -4700 0

Columns 1 - 8 are for the 8 link currents in the same order as the input link declarations. Columns 9 - 12 are for the 4 node voltages in the same order as in the nodes matrix, that is column 9 is node 1 and column 12 is node 8, with nodes 3 and 5 in between. Rows 1 - 4 are the current balance equations from the network topology. NPN 9 6 7 is considered device 0 and there is no equation for it. Row 1 is for NPN 5 2 4 and the rows are in the same order as the input device declarations down to row 4 which is for V 12 8. These four rows will be identical in all states, of course. Row 5 is for the ground declaration. It is the only row in which the sum of the numbers in columns 9 - 12 is not zero. The ground declaration is the only equation in which the voltages do not appear as the differences between 2 voltages. Rows 6 - 12 are the device characteristics, in the order in which the devices appear in the input. Two rows for each of the 2 NPNs and one row for each of the remaining 3 devices. The 4 rows for the NPNs will be different in different states. The three other devices only have one state so those three rows will remain the same in all states. Notice that the two rows for the second NPN have nonzero entries in the constant vector. Both are 0.75. These two equations express that certain voltage differences are 0.75 volts. The other device with a constant is the 5.0 V voltage source that is represented in the last row. This matrix and vector are now ready to be submitted to a linear equation solving subroutine. In this example, the routine will find that this matrix and vector has a unique solution which is:

Current 9 5 = 0.0 Current 5 12 = 1.968E-3 Current 1 7 = 0 Current 3 4 = 1.064E-3 Current 1 2 = 0.9043E-3 Current 3 6 = 0 Current 8 11 = 1.968E-3 Current 11 10 = 0.9043E-3 Voltage 1 = 0.75 Voltage 3 = 0 Voltage 5 = 0 Voltage 8 = 5.0 Now the inequalities must be checked. For the first transistor, the three terminals are looked up in the nodes matrix to find what nodes they belong to. Then we must have

V3 - V5 < 0.75 V3 - V1 < 0.75

The program now knows Voltage 3, Voltage 5 and Voltage 1 from the solution of the equations so these inequalities are just explicitly checked. We see that the inequalities are indeed satisfied. For the second transistor, all the inequalities involve currents. The current entering the emitter is set to 0. The links are searched to find any links with 5 as the second terminal. For each such link the current in that link, now known from the solution of the equations, is added to the current entering the emitter. The links are searched to find any links with 5 as the first terminal. For each such link, the current in that link is subtracted from the current entering the emitter. The program will find the current entering the emitter, terminal 5, is -1.968E-3. Similarly, the program finds the current entering the base, terminal 2, is 0.9043E-3. And the current entering the collector, terminal 4, is 1.064E-3. Then the program directly verifies that 0.9043E-3 > 0 1.064E-3 < 50.0 X 0.9043E-3 -1.968E-3 < 0 In the last inequality, I assume that this program assumes the reverse beta is 0 for simplicity. The program could easily be made to accommodate nonzero values for reverse betas if you want to. As was pointed out before, if there is actually a whole space (larger than 1) of solutions to the equations, and the solving routine has merely returned an arbitrary typical solution, then if the inequalities are not satisfied by this solution, it is not conclusive. It is possible that a different solution to the equations would be consistent with the inequalities. It is mathematically much more challenging to determine if any solution to a set of linear equations, when there is a whole space of solutions, is consistent with a set of inequalities. In this simple student program we ignore this issue. It can be correctly handled if you are so lucky as to find a general linear system (arbitrary equations and inequalities) solving subroutine. Then just represent the inequalities in matrix form as well as the equations and let the general linear system solver do its thing. This is a very simple circuit analysis program to be sure. Even at this level, it can be quite useful. From this base it can be extended to be much more sophisticated. For example, the matrix could be extended to twice as many columns. With this, there are now 2 columns for each current and voltage. Now you can represent the first derivative of each current and voltage as well as the function. This should now go to a differential equation solving routine rather than to a linear algebraic equation solving routine. Initial values are required for numerical solution of the differential equations. The initial values can be obtained by first doing the simple analysis described here with all derivatives set to 0. This is the, so-called, steady state solution. Then the differential equation solver is called. Now the network can contain inductors and capacitors and voltage sources and current sources can be functions of time. This is a comparatively simple extension once the static analysis program is in hand.

8. Estimating
The term estimating is not quite the right description of what we want to do here. In fact, the methods discussed here frequently get exact solutions to networks. Sometimes the solutions are only approximations but that is not the key. Often the answers are exact. What we really want to do here is be able to solve a large variety of even fairly complex networks very quickly with nothing more than a pencil and a simple calculator. Frequently the calculator isnt really needed. It turns out that it is actually quite easy but probably takes some practice. Lets consider the following network, which is actually pretty typical of small problems that you may want to analyze quickly.

This network contains 3 transistors. Even at only 3 states per transistor there are potentially 27 states to consider. It has 8 nodes so there are 8 unknown voltages. There are 15 links so there are 15 unknown currents. We have 27 different problems to solve, each one with 23 equations and 23 unknowns, not to mention the inequalities! This sounds like a daunting problem! In fact, with a little practice this network can be solved completely with only 2 approximations, which will be quite good, with nothing more than a pencil, in about one minute. You can have the exact answer in about one more minute. In fact, if you have to draw the circuit on paper with a pencil and then solve it using only that pencil, it should probably take no longer to solve it than to draw it. By this time we should know a few facts so well that we do not need to think about them. First, if we have a bunch of 2 terminal devices linked together in a single line, like a train, then the currents in all the links are equal and in the same direction. This is a very simple consequence of the topology condition that the total current entering each device must be zero (whatever goes in one terminal must come out of the other). Even if the line of devices is closed to form a loop, all the link currents are the same. Hence, whenever we have a linearly linked set of 2 terminal devices we can just write the common current value and a direction with an arrow anywhere along the train and it is understood that this is the current in all of those links. Even if there are devices with more than 2 terminals, if we know that the currents entering all terminals but 2 are 0, these can be considered just like 2 terminal devices and included in the train. This is convenient for example for MOSFETs in which the gate current is always zero so the current entering the drain is always the same as the current leaving the source. Suppose that there is a train of linearly linked devices as discussed above, but there are more links going off at various points like branches from the trunk of a tree. If you can show that the currents in the branches are zero, then we still have the same current in all the links along the trunk of the tree. For estimating, we dont want to write equations. We will determine voltages and currents one by one and just write them on the diagram as we determine them. Back to the example. Get the easy things first. Node 12 has the ground symbol on it so we immediately know that if there is any solution at all this node must be at 0 Volts. Write 0 V near that node. From the voltage sources, it is now immediately obvious that node 2 must be 2.1 V, node 5 must be 2.0 V and node 9 must be 5.0 V, unless there is no solution at all. Write these by those nodes. Now consider transistor 1, 2, 3. It is useful to define the states on and off for a transistor. Off is exactly the cutoff state, and on means active or saturated (or reverse active if we consider that). We can now suppose that transistor 1, 2, 3 is off. Then current (1, 17) is zero. Now consider transistor 4, 5, 6. Suppose it is off. Then current (4, 17) is zero. This makes the current entering terminal 17 zero and the voltage at node 1 must be 0. But node 5 is at 2.0 V. There is no state for the transistor in which the base is more than 0.75 V above the emitter, and it certainly is not so in cutoff. Transistor 4, 5, 6 cannot be off (starting with the assumption that transistor 1, 2, 3 is off). Hence transistor 4, 5, 6 is on. If this is so we can conclude that node 1 is at 1.25 V (2.0 0.75). Now look at transistor 1, 2, 3. Its base to emitter voltage is 0.85 V (2.1 1.25). There is no state in which this voltage can be higher than 0.75 V. We can conclude that it is not possible that transistor 1, 2, 3 is off. Hence it is on. Since we know that transistor 1, 2, 3 is on, node 1 is at 1.35 V (2.1 0.75). Write that by node 1. Transistor 4, 5, 6 now has a base to emitter voltage of 0.65 V (2.0 1.35). This means that transistor 4, 5, 6 is off. Current (4, 17) is 0. Write this on the diagram.

Since voltage 1 is 1.35, the current entering terminal 17 is 1.35 ma (1.35 V / 1 K Ohms). Since current (4, 17) is 0, this means current (1, 17) is 1.35 ma. Write this with an arrow.

We know transistor 1, 2, 3 is on but is it active or saturated? Suppose it is saturated. Then node 3 would be at 1.35 V (the same as node 1). Then current (18, 3) would be ((5.0 1.35)/1 K) 3.65 ma. The base current would be positive so current (1,17) would be more than 3.65 ma. But we know it is 1.35 ma. So transistor 1, 2, 3 is not saturated, it is active. In the active state the base current is the collector current/Beta. All three transistors have Betas of 50. The base current is only 2% of the collector current. It is a good first approximation to call the base current 0, so current (18, 3) is the same as current (1, 17), that is 1.35 ma. Then the Base current, (13, 2), would be 1.35/50 or 0.0270 ma. This means the collector current (18, 3) is more like 1.323 ma. Now if we want this exactly, we have the simple equation: X + 50 * X = 1.35 where X, is the base current. From this we see that the exact base current is 1.35/51 = 0.02647058823529 and the real collector current is 1.323529411765 not the 1.323 ma we estimated. For this a calculator is handy. Up until now there was no need even for a calculator. The approximation is quite good. It is simple to get the voltage at node 3 (5 1.323 ma X 1K). This brings us to transistor 4, 5, 6. We know it is off. We can immediately mark current (15, 5) and (20, 6) zero.

Suppose transistor 7, 8, 9 was off. Then current (20, 8) would be zero. This means the current entering terminal 20 is zero which means the voltage at node 8 is 5.0 V. Similarly, current (7, 23) is zero so node 7 is at 0.0 V. There is no state of the transistor in which the base to emitter voltage is above 0.75 V, so transistor 7, 8, 9 is not off. It is therefore on. Assume transistor 7, 8, 9 is saturated. Then node 7 is at 5.0 V (the same as the collector). Node 8 must then be at 5.75 V. Current (20, 8) must be positive, hence terminal 21 is higher than 5.75 V. But we know it is at 5.0 V. Transistor 7, 8, 9 is not saturated, it is active. Again, a good starting approximation is that current (20, 8) is 0. Then node 8 is at 5.0 V, and node 7 is at 4.25 V. Current (7, 23) is 4.25 ma. Now as a refinement, current (20, 8) is .085 ma., since the Beta is 50. This means node 8 is really closer to 4.915 V and node 7 is at 4.165 V. If we want this exactly we have the equation: (X + 50 * X) * 1K = 5.0 X * 1K 0.75 or 2 * X + 50 * X = 4.25 ma or 52 * X = 4.25 ma where X is the base current. From this we find the base current, (20, 8) is 0.08173076923077 ma. The collector current is then 50 times this much or 4.086538461538 ma. The emitter current, (7, 23), is the base current plus the collector current or 4.168269230769 ma. Node 8 is at 4.918269230769 V. Node 7 is 0.75 less than this or 4.168269230769 V. This is nicely consistent with 4.168269230769 ma X 1 K Ohm. Our estimated node 7 voltage was 4.165 V. Not too bad. Again, the estimate is easy enough to do without even a calculator. The exact answer, needing a divide by 52, is easier with a calculator.

2.1 V

Estimating works easily because the equations we are thinking about are sparse. Sparse means that most of the equations actually involve few of the many variables in the problem. It is easy to see that this is so by looking at the matrix we developed as an example in the section on writing a circuit analysis program. If you look there, you see the matrix has many 0s in it. Most lines in the matrix have only a small number of non-zero entries. What estimating is doing is looking for the equation with the fewest unknowns in it. Typically we can find an equation with only 1 unknown. If we find an equation with only 1 unknown it is trivial to solve this equation. Then we can put this value in all the other equations that involve this variable, reducing the number of unknowns in all of them by 1. This makes it likely that we can now find another equation with only 1 unknown and do the same thing again. Occasionally we cannot find an equation with only 1 unknown. This happened twice in the example we just did. In those cases we could only find equations with 2 unknowns. We then either approximated one variable so we could solve for the other, or else we had to actually resort to writing a simple equation and solving it. In practice you can go from one equation with only 1 variable to the next equation with only 1 variable in it most of the time. It is ironic that classical circuit analysis used elaborate schemes to write the equations for a network so that they would naturally produce a smaller but denser set of equations compared with the methods in this paper. This was done because at this older time, the equations would have to be solved by hand. It was thought that you wanted the smallest possible set of equations if you were going to solve them by hand. But in fact, schemes that lead you to dense equations make estimating virtually impossible. Estimating, going from 1 equation with a single variable to the next with a single variable, is the really quick way to solve the network by hand. But it relies on thinking of the network as a larger number of very sparse equations. The sparser the better! One of the motivating factors for the approach in this paper was to have a view of networks that naturally leads to fast, easy estimating. (The other motivation was to avoid the elaborate schemes that were classically used to write equations.) I could not leave this without pointing out that there are some networks that are not very amenable to our estimating approach. The example, widely used for eons, of the simple network that does not accommodate shortcut analysis methods is the bridge.

It turns out that there are some shortcuts that work on the bridge, but they are beyond the scope of this paper. You will, from time to time, come across possibly even fairly small networks that you cant estimate reasonably. Sometimes you pretty much have to write down the equations and solve them. The great majority of networks that you are routinely faced with can be estimated very easily.