You are on page 1of 6

2012 IEEE 30th VLSI Test Symposium (VTS)

978-1-4673-1074-1/12/$31.00 2012 IEEE

On the Parametric Failures of SRAM in a 3D-Die Stack
Considering Tier-to-Tier Supply Cross-talk

Wen Yueh, Subho Chatterjee, Amit Trivedi, and Saibal Mukhopadhyay
School of ECE, Georgia Institute of Technology
777 Atlantic Dr. NW, Atlanta, GA 30332
{wyueh3, subho.chatterjee, atrivedi31, saibal}

Abstract This paper analyzes the supply crosstalk between logic
cores and SRAMs on separate tiers in a 3D die-stack using a
distributed RLC based 3D power grid model. The analysis shows
that due to the supply cross-talk power variation in cores
modulates the performances and parametric failures in SRAM.
Keywords parametric failure, 3D integration, Power Delivery
Network, static random access memory (SRAM) .
The high density Through-Silicon-Via (TSV) based 3D
integration has the potential to significantly improve the die-to-
die communication bandwidth, system performance, and
reduces the design footprint [8]. Consequently, the TSV based
3D integration has received significant attention in the
microprocessors, embedded systems, and FPGA applications
[4]. Significant research efforts have been directed to develop
TSV technologies, TSV-aware physical design tools, analyze
the defect behavior of TSVs, and pre/post-bond test methods
for TSV based 3D-ICs [16]. The impact of 3D die-stacking on
the parametric failures (due to variations in circuit delay and
noise margin) has received relatively less considerations. The
parametric failures are primarily due to manufacturing
variations in the transistor parameters (e.g. threshold voltage)
and they influence the reliability of ICs in nanometer
technology nodes [6,13,14]. Hence, understanding the impact
of 3D stacking on the parametric failures is critical.
This paper studies the effect of TSV based 3D integration
on the variation in parametric failures of the static random
access memory (SRAM). The stacking of logic cores and
SRAM has emerged as a key application of the 3D integration.
However, the impact of 3D stacking on SRAM robustness is
less understood. We specifically consider the 3D stacking
effect on the supply noise profile of the SRAM tier and the
consequent effects on SRAM stability. The power delivery
networks (PDN) of the tiers in a 3D stack is highly coupled as
the power and ground (P/G) TSVs reduce the electrical
impedance between the 2D supply grids of each tier [7]. Hence,
the logic cores (aggressor) active power injects supply noise to
the PDN of the SRAM tier (victim), which ultimately affects
the parametric failures on the SRAM. We define this
phenomenon as the tier-to-tier supply cross-talk. Understanding
the tier-to-tier supply cross-talk between a heterogeneous stack
of SRAM die and logic die is thus crucial to designing reliable
systems. To the best of our knowledge, this paper is the first
effort modeling and characterizing the SRAM stability
including the 3D inter-tier supply cross-talk.
We develop a supply cross-talk aware stability analysis
methodology for the 3D die-stacked SRAMs (Fig. 1). Our
approach first evaluates the supply noise (IR-drop and high
frequency noise) of a 3D stack of cores and SRAMs. The
supply noise estimation is coupled to SRAM parametric failure
analysis considering the random dopant fluctuation induced
threshold voltage (I
) variations. The developed methodology
is used to analyze the impact of the 3D die-stacking on SRAM
stability considering the power variation in low-frequency and
high-frequency. Our analysis shows the presence of strong
correlation between the power dissipation in cores and the
stability of SRAM in a 3D stack due to the supply cross-talk.
We observe that due to the supply cross-talk, both low-
frequency power variations and high-frequency current noise in
the cores affect the SRAM stability. We study the implications
of different PDN options on the stability of the SRAM under
supply cross-talk. We observe that in a pin-limited package, the
non-shared (cores and SRAM does not share PDN and P/G
pins/C4 bumps) PDN, although eliminate the cross-talk,
degrades the supply noise in the processor. The shared PDN,
on the other hand, degrades the stability of the SRAM due to
the supply cross-talk. We further observe that show a higher
TSV density in a shared PDN benefits the processor core, and
creates a higher supply cross-talk reducing the SRAM stability.
Our analysis shows the need for an accurate consideration of
the supply cross-talk to ensure robustness of a processor-
memory 3D sta.
The analysis of 3D PDN has received significant attention
in the recent literatures. Ahmad et al. has developed efficient
PDN simulation methods [10]. Authors have observed that, at
higher TSV density, although IR drop reduces, the quality
factor of the RLC tank increases. This effect produces higher
anti-resonances in the high frequency range. They have also
analyzed the reliability of the 3D PDN considering the TSV
failure due to mechanical stress. Authors have shown that
higher TSV density potential reduces the 3D PDNs mean time
to failure (MTTF). Zhou et al. studied the use of hybrid decaps
(metal-insulator-metal (MIM) decaps and traditional MOS-
CAP) for 3D stacks [15]. Healy et al. and Tsioutsios et al.
studied the use of cluster of smaller TSVs for improving the
impendence property of the 3D die-stacks [2,12]. Healy further
introduced the delayed core turn-on policy and further reduced
the IR-drop by over 37%. These works identify the correlation
between TSV densities and noise levels on the system level.
Hearly also studied the core last (i.e. core closer to heat sink),
core first, and core interleaved configurations. Pak et al. studied
PDN of a 3D-stack of GPU cores and DRAM [7]. The analysis
shows that increasing the P/G TSV count only improves the
impedance in a limited frequency range and the effect can be
Figure 2. The overall fault simulation flow for suppl
SRAM stability analysis
IR d
SRAM cell
level netlist
Read time
SRAM parametric
3D IC specific
Parametric failures
Monte Carlo
New failure
model specific
to 3D ICs
outside of the operating frequency. This stud
supply noise in the DRAM could be limited by
regardless of the number of P/G TSVs.
This paper builds on the PDN modelin
previous literatures to analyze the tier-to-tier
impact on the parametric yield of a 3D stack.
works on 3D stack of logic cores and S
However, these analyses focus on the
manufacturing aspects and not the interference
cross-talk. Hence, these analyses may not
SRAM parametric failures due to such effect.
tier-to-tier cross-talk effect on the SRAM st
therefore, a unique contribution from this pape
The goal of this work is to simulate the S
failure in a 3D die-stack considering the tier-to
supply noise. Since the power dissipation in
higher than the SRAMs, we consider the c
aggressor and SRAM tier as the victim. Our
framework estimates the supply noise of the S
power dissipation in the processor cores an
effect on SRAM failures. The overall simulatio
in Fig. 1. The 3D PDN is modeled in the flow
physical design parameters such as organizat
density of P/G TSVs etc. The power variatio
fed to the PDN model to estimate both low-fre
and high-frequency voltage variations (Ld
model is based on distributed RLC grid (detail
and HSPICE is used as the simulator. The e
noise in the SRAM tier is used to simulate the
under threshold voltage variations. We consi

Parameters R (ohm)
PCB 94 (s)
166.6 (p)
PKG 1000 (s)
541.5 (p)
BUM 40 m
GRID 28.1 m
TSV 7.735
Figure 1. The modeling of the 3D PDN: (
PDN, and (c) on-chi

ly cross-talk aware
drop & Ldi/dt
ower grid
3D stack
dy shows that the
y the cores PDN
ng efforts in the
cross-talk and its
There are related
SRAM [1,4,6,8].
architecture or
e from the supply
predict the 3D
. Considering the
tability in 3D is,
RAM parametric
o-tier coupling of
n cores is much
core tiers as the
r fault simulation
SRAM tier due to
nd evaluates the
on flow is shown
w considering the
tion of the stack,
on of the cores is
quency (IR drop)
di/dt). Our PDN
ls described later)
estimated voltage
e SRAM stability
ider read margin,
write margin, and read time as th
write, and access failures. The M
SRAM are performed considering
and the voltage noise estimated f
spatial correlation is performed betw
the victim SRAM blocks.
A. Modeling the 3D Power Grid
For a 2D design, a planar power
power to the SRAM cells. The P
composed of multiple planar power
vertical P/G TSVs (Fig. 2). One 2D
SRAM array and the second 2D g
cores. The current consumptions o
modeled as distributed current sour
the SRAM is modeled as 10% of pr
2D grid design is motivated from th
The RLC network uses an equivale
derived from the lumped impedan
processor. The grid has 48x48
corresponding 48x48 grid nodes for
is 144 mm
and form unit cell of
m. Note this model does not sugg
L (H) C (F)
21 p 240

120 p 26

72 p
3.1 f 93.8
5.710 p 313.2 f

(a) model parameters, (b) off-chip
ip 3D PDN
he metrics for read disturb,
Monte-Carlo simulations of
random process variations
from the PDN analysis. A
ween the aggressor core and
r grid delivers the necessary
PDN in a 3D die-stack is
r meshes connected through
D grid provides power to the
grid provides power to the
f the cores and SRAM are
rces. The power density of
rocessor power density. The
he work of Gupta et al [3].
ent distributed power mesh
nce model of a Pentium 4
grid nodes for Vdd and
r ground. The die dimension
dimension 250 m by 250
gest the grid metal to metal

Figure 3. Metrics of dynamoc read margin to evaluate the effect of high-
frequency noise
m -
pitch is 250 m, rather we develop an equivalent model with
resolution of 250 m by 250 m for the current density
calculation. The lumped resistance and inductance scale well to
the 50 m grid pitch modeling used by Pak et al. [10]. The off-
chip impedances are modeled with RLC ladders (Fig. 2b). The
first segment of the ladder models the board level lump
impedance and the second segment of the ladder modes the
package impedance. The package ladder is evenly distributed
to the points on the on-die grid with partially-lumped solder
bump impedance.
The 3D grid network uses similar planar distributed grid
structure but have vertical P/G TSV connections for each
stratum. Half of the equivalent P/G TSV structure is shown on
the bottom-left 3D grid edge in Fig. 2c. The physical geometry
of the P/G TSV is defined as 50 m in length, liner thickness of
100 nm, 10m in diameter. The minimum pitch is assumed to
be 100 m, and the corresponding TSV density would be 100
. In the grid design, this is equivalent to roughly
maximum six TSVs per unit grid. Due to the TSV count is
higher than the grid nodes, the TSV impedance is lumped to an
equivalent model during the analysis. The corresponding TSV
resistance and capacitance are extracted from 3D TCAD
simulation. The TCAD simulation accurately accounts for the
MOS capacitance of the P/G TSVs. The details of the P/G TSV
modeling can be found in [11]. The TSV inductance is
referenced from the work of Katti et al. [5]. The 3D as well as
the 2D equivalent impedance used throughout the paper is
given in Fig. 2a.
B. Modeling the Parameteric Stability of SRAM
In SRAM parametric analysis, the predictive 32 nm
technology models are used for the simulation [14]. We
evaluate the traditional 6-T cell parameters. We considered the
following metrics to evaluate parametric stability:
The static read margin: The read margin is estimated as
the difference between the voltage rise at the node storing
0 (V
) and trip point of the inverter associated with the
node storing 1 (V
). The read margin is used to predict
the read disturb failure.
The bit-line write margin: The write margin is measured
as the maximum voltage at the low-bit line that results in
successful write operations (the weak-write test). The write
margin (and time) is associated with write failure.
The read time: The read time is measured as the time
required developing 100mV voltage differential across the
bit-lines. The read time is related to the access failure.
The detail measurement methods can be found in many
literatures [9,13]. Monte-Carlo simulations considering process
variations and grid voltage estimated from the PDN analysis
are performed using HSPICE for failure analysis. We assume
all cells within a grid node have same operating V
C. Modeling High-Frequency Noise Effects on SRAM
For high-frequency noise, we observe the difference
between the two internal storage voltages I

and I

read operation under transient supply noise (Fig. 3). Different
noise amplitudes are injected according to the droop on
corresponding grid points. The simulation aims to determine if
the internal capacitance of the cell responds to a high frequency
supply noise. In our 3D PDN analysis framework, the supply
noise is created through injecting current transitions on the core
A. Analysis of Voltage on SRAM Stability
Fig. 4 shows the statistical variations in the read time,
read margin, and write margin of SRAM as a function of the
supply voltage. As expected, we observe that a lower supply

(a) (b) (c)
Figure 4. The effect of supply voltage reduction on SRAM stability metrics: (a) read margin, (b) write margin, and (c) read time

voltage significantly degrades the read time (increases), read
margin (reduces), and write margin (reduces). We further
observe that the worst-case values considering process
variations degrade at a much faster rate than the nominal (or
average) values. Hence, the parametric failures will increase
significantly at a lower supply voltage.
B. PDN Design Options and Voltage Noise in SRAM Tier
We first consider the implication of sharing the PDN
between core and SRAM tier. In a non-shared PDN, the core
tier (assuming it is further from the pins/C4 bumps) will
receive power through dedicated TSVs. The memory tier will
be directly connected to the P/G pins (C4 bumps). The non-
shared PDN structure avoids the problem of supply crosstalk
by isolating the PDN on each tier. However, in a 3D stack of
processor and SRAM the total number of P/G pins does not
scale with the number of tiers. This is because the pin density
per unit silicon area (i.e. the number of pins for a same size
processor dies) may not increase in a 3D stack. Increasing the
total number of power pins of the 3D stack (to accommodate a
separate P/G for SRAMs) will increase the system footprint.
Therefore, under a constant chip footprint (same as the 2D
logic processor) constraint, a separate P/G network for SRAM
will result in a reduced number of pins to the processor.
Fig. 5 shows the supply impedance as a function of
frequency for the shared and non-shared PDN conditions. In
this analysis we have considered a power sources in the core
layer (as shown in Fig. 5). We clearly observe that the
impedance of the PDN of the core tier is much higher in the
non-shared PDN stack. This is because of the reduced number
of P/G pins available to the core tier. Moreover, in the shared
PDN, there are more parallel resistive paths between the power
source (less horizontal impedance) and the P/G pins which also
reduce the low-frequency impedance. The high-frequency
impedance of the shared grid is lower as well. This is because
for a shared grid with one power source (the core), the decap
on the SRAM tier is also visible to the core tier, thereby
reducing the high-frequency impedance. Hence, the non-shared
PDN, although eliminate the cross-talk, increases the supply
noise of the core tier. Sharing the PDN reduces the supply
noise in the core in a P/G pin limited 3D stack. Conversely, the
coupling between cores and the SRAM tier is more significant
in a shared 3D PDN design and needs careful analysis.
We have also evaluated two types of organizations in a
shared PDN: (1) the core tier is further away from the pins
without the direct access to the solder bumps (the core last
configuration), and (2) the core first configuration where the
cores are closer to the solder bumps. For both of the above
cases we consider different density of the P/G TSVs. The
estimated low-frequency voltage noise in the SRAM tier
(maximum IR drop) is shown in Fig. 6. We first observe that at
a higher TSV density the voltage drop at the core tier reduces
(i.e. supply voltage increases) for both the core last and core
(a) (b)
Figure 7. The supply voltage with worst ir drop in the SRAM tier
considering (a) non-shared PDN and small SRAM power, (b) shared PDN
with core power of 30W at the chip center.

Figure 6. The top figure illustrates the tier arrangements for the shared and
non-shared PDN frequency response below. Blue dots are connections to the
logic tier and gray dots are to the SRAM tier through TSVs.
Shared 3D PDN Inde. 3D PDN Traditional 2D PDN
Mem. logic

Figure 5. The top figure illustrates c-first (core first) and c-last (core last)
arrangements for the legends. The core/memory organizations and TSV
densities on the IR drop is illustrated accordingly.
3D PDN C-last 3D PDN C-first
Bottom view
To pins

first configuration. However, higher TSV density reduces the
impedance between two tiers and increases the supply cross-
talk. Consequently, the IR drop in the SRAM tier increases (i.e.
voltage of the SRAM tier reduces) i.e. stability of SRAM
degrades as the P/G TSV density connecting the tiers increases.
We further observe that voltage noise for the SRAM in core
last and core first configurations are almost identical at 100
(Fig. 5). Therefore, for the rest of the paper we only
simulate the core first configuration (cores closer to the P/G
C. Analysis of IR Drop in Shared PDN
The IR drop of conventional SRAM is less of a problem
than high activity logic cores. Fig. 7a shows an example the IR
drop of an independent 3D memory stack design. Fig. 7b
shows the shared 3D version that a noticeable IR drop occurs in
the grid center due to power consumption form the processor
tier. While the maximum IR drop location coincides vertically
with the current drawn location, there are SRAM blocks in in
the neighborhood also suffers from IR drop due to this source.
This shows the lateral propagation of the noise injected in the
SRAM tier from the core tier. The strength of the noise
degrades in the SRAM tier as we move far from the location
vertically aligned with the power source in the core tier. As the
SRAM density in current technologies is very high, a large
number of SRAM cells can be affected due to the generation
and propagation of the supply cross-talk voltage noise.
D. SRAM Modeling with RDF and Supply Coupling
We now combine the supply drop estimated from the PDN
simulation with failure estimations for SRAM considering
random process variations. Fig. 8 shows the variations in the
read/write margin (Fig. 8a) and read performance (Fig. 8b) as a
function of the lateral distance in the SRAM tier from the
power source in the core tier. We consider variation in both the
nominal values as well as 5 worst-case values (x - So, x =
mcon, o = stonJorJ Jc:iotion)to better understand the
failure behavior. The maximum degradation in the failure
metrics occur at the SRAMs locations vertically aligned to the
power sources as expected. The 5 worst-case margins degrade
at a much higher rate. Fig. 8c lists the comparison of the
simulation considering grid effect and the one without. The
percent error differences are significant when analyzing an
SRAM on a shared 3D PDN.
The supply cross-talk generates a strong correlation
between the SRAM stability and power dissipation in the core
tier. A higher power dissipation in the core tier results in a
larger voltage drop in the SRAM tier. This is illustrated in Fig.
9. The higher voltage drop translates to a reduced margin and
performance as well. Therefore in a 3D static we observe a
unique correlation between power in the core tier and
operational reliability and speed of SRAM. Note the power
dissipation in the logic core is time-varying due to variation in

(a) (b) (c)
Figure 8. The effect of IR drop: (a) the effect of distance on read/write margin, (b) the effect of distance from power source on read time, and (c) the effect of the
PDN on the SRAM stability.

Figure 9. The effect of variations in the power dissipation in the core tier on:
(a) worst voltage drop (IR drop) in each tier, and (b) read/write margin and
read time

the workload or application dependent power profile.
Consequently, we expect a time-varying failure rate on the 3D
SRAM tier.
E. SRAM High Frequence Coupling
We apply high-frequency current transition in the core tier.
The voltage droop propagates from the center of the logic core
to the edge of the chip as well as travel through TSVs and
inject noise to the other tier. The transient voltage variation in
the SRAM tier due to a current noise in the core tier is shown
in Fig. 10a. A triangle current pulse is used to generate 10%
droop in shared logic core. Fig. 10b shows the voltage at the
first droop at different location versus the lateral distance of the
location from the current source in the core tier. The shared 3D
PDN on the core tier shows a lesser first droop magnitude
under the same current profile. In the independent 3D PDN
case, the noise is relatively higher but the droop is marginally
more localized. In the shared case, the droop profile in the core
and the SRAM tier follows each other with the SRAM tier
having marginally lower noise than the cores in regions close to
the current source (Fig. 10b). The dynamic read stability metric
of the SRAM (as defined in Fig. 3) is estimated with the supply
noise during reading and the results are is shown in Fig. 10c.
Note a higher value of min (I


) implies a better read

stability under transient noise. We observe that a shorter pulse
width of the transient supply noise has lower impact on the
dynamic read stability.
We have developed a supply cross-talk aware failure
analysis methodology for SRAM in a 3D stack of processor
and SRAM. Our methods simultaneously consider process
variations in transistors and supply variations in the SRAM tier
due to supply cross-talk. Our analysis shows that the supply
cross-talk can adversely impact the stability and parametric
failures in SRAM and neglecting this effect can lead to
significant error in the failure analysis of 3D SRAM. We
further observe that the impact of the supply cross-talk on
SRAM stability is strongly correlated to the power variations in
the core. Hence, an integrated analysis of the entire 3D stack is
necessary to understand the robustness of the 3D system.
Future work in this area needs to consider design approaches to
reduce the coupling and develop design methods for the SRAM
to maintain stability under the time-varying supply noise
injected by the cores.
This work is supported in part by Semiconductor Research
Corp (#1836.075), National Science Foundation (CNS-
1054429 and CCF-0917000), Intel Corp, and IBM Faculty
[1] A. Al Maashri et al., "3D GPU architecture using cache stacking:
Performance, cost, power and thermal analysis," in IEEE Int. Conf. on
Comput. Design, Oct. 2009, pp.254-259.
[2] M.B. Healy et al., "A novel TSV topology for many-tier 3D power-
delivery networks," in DATE, Mar. 2011, pp.1-4.
[3] M.S. Gupta et al., "Understanding voltage variations in chip
multiprocessors using a distributed power-delivery network," in DATE,
Apr. 2007, pp.1-6.
[4] P. Jacob et al., "Predicting the performance of a 3D processor-memory
chip stack," IEEE Des. Test Comput., vol.22, no.6, pp. 540- 547, Nov.-
Dec. 2005
[5] G. Katti et al., "Electrical modeling and characterization of through
silicon via for three-dimensional ICs," IEEE Trans. on Electron Devices,
vol.57, no.1, pp.256-262, Jan. 2010
[6] S Ozdemir et al., "Quantifying and coping with parametric variations in
3D-stacked microarchitectures," in DAC, June 2010, pp.144-149.
[7] J.S. Pak et al., "PDN impedance modeling and analysis of 3D TSV IC by
Using proposed P/G TSV array model based on separated P/G TSV and
chip-PDN models," IEEE Trans. Compon. Packag. Manuf. Technol.,
vol.1, no.2, pp.208-219, Feb. 2011
[8] K. Puttaswamy et al., "Implementing caches in a 3D technology for high
performance processors," in ICCD, Oct. 2005, pp. 525-532
[9] D. Mukherjee et al., Static Noise Margin Analysis of SRAM Cell for
High Speed Application, Int. J. Computer Science Issues, Vol.7, no. 5,
Sep. 2010
[10] A. Shayan et al., "3D stacked power distribution considering substrate
coupling," in ICCD, Oct. 2009, pp.225-230.
[11] A. Trivedi et al., "Impact of Through-Silicon-Via Capacitance on High
Frequency Supply Noise in 3D-Stacks," in EPEPS, Oct. 2011, in press.
[12] I. Tsioutsios et al., "Physical design tradeoffs in power distribution
networks for 3-D ICs," in ICECS, Dec. 2010, pp.430-433.
[13] J. Wang et al., "Analyzing static and dynamic write margin for
nanometer SRAMs," in ISLPED, Aug. 2008, pp.129-134.
[14] W. Zhao et al., "New generation of Predictive Technology Model for
sub-45nm early design exploration," in 7th Int. Symp. on Quality
Electronic Design, Mar. 2006, pp.6-11.
[15] P. Zhou et al., "Congestion-aware power grid optimization for 3D
circuits using MIM and CMOS decoupling capacitors," in ASP-DAC,
Jan. 2009, pp.179-184.
[16] A. W. Topol, et al., "Three-dimensional integrated circuits," IBM J. of
R&D, v.50 n.4/5, July 2006, pp.491-506.

(a) (b) (c)
Figure 10. The effect of the high-frequency noise: (a) transient waveform of supply noise in the SRAM tier, (b) first droop versus lateral distance in the SRAM tier
from source in the core tier, and (c) dynamic read margin versus distance from source