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Lecture1
VLSI Technology, and Device Models and Characterization
Masud H. Chowdhury Electrical and Computer Engineering University of Illinois at Chicago
Silicon VLSI Technology
Ingredient:
– – – – – – – – – – Silicon Polysilicon Oxide (SiO2) Impurities (Diffusion and Implant) Metal (Cu, Al) pnjunction Diode BJT (NPN and PNP) MOSFET (NMOS and PMOS) JFET Resistor, Inductor and Capacitor Diffusion and Well Poly and Metal (Metal 1, Metal2 …….) Buried Channel Contact and Via
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Devices and Components:
Layers:
– – – –
BJT and MOSFET
E n p B E p n p C n C
B
Source Gate Drain
Polysilicon SiO2
Source
Gate
Drain
n+ p
n+ bulk Si
p+ n
p+ bulk Si
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Device Modeling
What is Modeling? Device models represent the functional relationship among the terminal electrical variables of the devices The electrical characteristics and the corresponding models depend upon a set of parameters What are parameters and variables used in the modeling? Geometrical or process variables
width, length, thickness, etc. of the devices
Design variables dependent on device physics
intrinsic and parasitic capacitance, resistance, conductance, etc
Why Device Models are Needed? Design and analysis of integrated circuits depend on utilizing suitable models Accuracy of the analysis and simulation depend on the accuracy of the models Higher accuracy requirement leads to higher complexity of the models
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Device Modeling
Setting the parameters and variables? Circuit designers can control and set the design parameters Circuit designers can not change most of the process parameters once the process has been specified. However, their observation and experience can be shared with process engineers to help specify the process to be used for a particular design Accuracy of the Models: For most physical device only a good approximation of the actual relationship of the electrical variables can be obtained. Tradeoffs must be made between the quality of approximation and its complexity The required accuracy and the intended use of the models are factors the engineers consider when making these tradeoffs What are the types of modeling? Device modeling can be of two types
DC model or large signal model  normally used in digital design and analysis AC model or small signal model – normally used in analog design and analysis
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DC or Large Signal Models: Large signal models are developed to calculate total currents and voltages in the transistor circuits These models are mathematical or numerical relationships that relate actual terminal voltages and currents of the device at DC and low frequencies These models are valid for a wide range of terminal voltages and currents, and at frequencies where the difference between the actual and DC solution is deemed negligible for the problem under investigation AC or Small Signal Models: Most circuits perform their task over a limited excitation range, which is typically specified in terms of a maximum input signal excursion about some nominal point. The points (nodal voltages and branch currents) about which the circuit operates are termed bias points or quiescent points (Qpoints). Internal to the circuits these input variations cause excursion around the quiescent point. Often these inputs are sinusoids of small amplitude compared to the supply voltages providing power to the circuit An analysis how these small sinusoids propagate through the circuit is termed small signal analysis or ac analysis. How small the signals should be to be considered small signals depend on the circuit topology, device characteristics, and Qpoint.
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Device Modeling
Use of Device Models: Large signal models are generally used in digital design where the devices normally act as switches. Analog circuits often operate with very small signals compared to bias voltages and currents in the circuit. In these circumstances small signal models can be used to calculate circuit gain and terminal impedances without the necessity of including the bias quantities. Often analog designers require both small and large signal characteristics. The performance specification of analog design can be expressed in terms of small signal characteristics, whereas knowledge of the large signal characteristics is necessary for biasing (setting the quiescent point) To simplify the calculation of circuit gain and terminal impedances, small signal models of MOSFET can be used
Device Modeling
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BJT for Analog and MOSFET for Digital – Why?
MOSFET for Digital IC: Provide very high density Low power consumption Quiescent power dissipated by the base current of BJT limited the integration density as IC became more complex Vacuum tubes were replaced due to high power consumption. For the same reason BJT started loosing favor as compared MOSFET MOSFET offers the advantage of almost zero control current while idle Low power consumption of MOSFET allows very high integration Improvement of silicon processes made MOSFETs more popular due to simpler fabrication process, and lower cost and area per device BJT for Analog IC: For stand alone analog IC BJT still offers many advantages Transconductance per unit bias current is much higher in BJT For many systems where analog techniques are used in some parts of the integrated circuits, and digital on other parts, BJTs are often preferred for analog part and MOSFETs for the digital part.
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MOSFET in Analog Design
For lower cost and better portability, higher integration density and lower power consumption have become two most important design matrices for current integrated circuit designs. To achieve these goals process technologies to provide both BJT and MOSFET in the same process have been developed However, these mixed process technologies are complex and more expensive than pure MOS processes. This economic consideration drive integrated circuit manufacturers to use all MOS processes in many practical cases
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Large Signal Behaviors and Models of MOSFET
Consider the NMOS transistor with the given biasing condition: The width (X) and the charge (Q) per unit area of the depletion layer under + the oxide is given by S D V G
GS
⎛ 2εφ ⎞ X =⎜ ⎜ qN ⎟ ⎟ ⎝ A⎠
1/ 2

n+
n+
Q = qN A X =
2 qN A εφ
n c h a n n e l p  s u b s tra te B
D e p le tio n R e g io n
φ is the potential in the depletion region at the oxidesilicon interface, ε is the permittivity of silicon, and NA is the doping density When the surface potential reaches a critical value ( twice the Fermi level φf) a phenomenon known as inversion occurs. In the presence of the inversion layer and without a substrate bias the depletion layer has a constant charge density Qb0 With positive substrate bias VSB the charge density will be Qb
Qb 0 = 2 qN A ε 2φ f
Qb = 2 qN A ε ( 2φ f + V SB )
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Large Signal Behaviors and Models of MOSFET
The gate source voltage required to produce an inversion layer is called the threshold voltage (Vt) given by:
V t = V t 0 + γ ( 2φ f + V SB − 2φ f )
S + V GS G D
Here
γ =
1 C ox
2 qεN A
n+
n+
n c h a n n e l
and
C ox =
ε ox
t ox
D e p le tio n R e g io n p s u b s tra te B
Let us now consider the bias condition as shown below: Cutoff Region: VDS VGS S ID G • ID = 0 for VGS ≤ Vt D • MOSFET is OFF – V(y) + n+ n+ Pinchoff Condition: y L • VGS > Vt • VDS = (VGS – Vt) = VDSAT psubstrate
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Large Signal Behaviors and Models of MOSFET
Linear or Resistive Region: – With VGS > VT, and VDS < VGS  VT, current ID can be given by
2 V DS ⎤ W ⎡ ID = k ⎢ (V GS − V T )V DS − ⎥ L ⎣ 2 ⎦ Here ' n
k n' = μ n c ox = μ n
ε ox
t ox
(process
trancond.
)
W = width of the channel μ n = electron mobility
& L = length of the channel
ε ox = perm. of gate oxide & t ox = oxide thickness
c ox = oxide cap. per unit area
Saturation Region: – With VGS > VT, and VDS >= VGS – VT , current ID is given by
ID k n' W = (V GS − V T ) 2 2 L
[
]
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Large Signal Behaviors and Models of MOSFET
• Channel Length Modulation Effect: – Ideal model predicts that drain current is independent of VDS in the pinchoff region – However, the depletion layer between the physical pinchoff point and the drain expands with the increase of VDS – If this depletionlayer width is Xd, the effective channel length is Leff = L – Xd – Consequently, the effective length of the channel is decreased leading to higher drain current as shown below. Depletion layer expands with VDS
k' W (VGS − Vt )2 ID = 2 Leff
– Since XD (and Leff) is function of VDS in saturation, ID varies with VDS. This effect is called channel length modulation. This effect can be observed as shown below: '
dLeff ∂I D k W I dX d =− = D (VGS − Vt ) 2 ∂VDS dVDS Leff dVDS 2 L2 eff
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Large Signal Behaviors and Models of MOSFET
• Channel Length Modulation Effect: – For MOSFET device a special parameter known as −1 Early voltage (VA), is ⎛ dX d ⎞ ID defined as follows: ⎜ ⎟
VA = ∂I D / ∂V DS = Leff ⎜ ⎟ ⎝ dV DS ⎠
– The parameter used for characterizing channel length modulation (λ) is the 1 reciprocal VA: λ= VA – After including the effect of channel length modulation in the IV model the saturation current can be expressed as follows:
ID ⎛ k' W V (V GS − V t ) 2 ⎜ 1 + DS = ⎜ 2 L VA ⎝ ⎞ k' W ⎟= (V GS − V t ) 2 (1 + λ V DS ) ⎟ 2 L ⎠
– The above results can be used to form a large signal model of an NMOS device – Here ID is given by the models derived above
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Small Signal Element  Transconductance
• • • • Consider the MOS transistor with the bias voltage as shown: The quiescent drain current ID is in saturation if VGS>Vt and VDD>VGSVt If a small signal input voltage vi is applied in series with VGS and produce a small variation in drain current id, the total current: Id = ID + id Transconductance: – The transconductance quantifies the drain current variation with a gatesource voltage variation while keeping the drainsource voltage constant:
gm = ∂I D W = k ' (VGS −Vt )(1+ λVDS ) ∂VGS L W W (VGS −Vt ) = 2k ' I D L L
for λVDS <<1 gm = k '
– gm is proportional square root of the bias current – gm depends on device geometry
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Small Signal Element  Transconductance
• Transconductance:
gm = ∂I D W = k ' (VGS − Vt )(1 + λVDS ) ∂VGS L W W (VGS − Vt ) = 2k ' I D L L for λVDS << 1 gm = k '
•
Another important factor is the ratio of the transconductance to the bias current:
gm 2 2 = = I D VGS − Vt Vov ....... Vov ⇒ over drive of MOSFET
– Typically overdrive Vov for MOSFET is chosen to be high to make the transistor faster, leading to low transconductance per given bias current – For analog application of MOS devices low transconductancetocurrent ratio is a challenge, because high quality analog circuits require high value of this ratio
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Limitation of Small Signal Analysis
• Transconductance:
gm = k ' W W (VGS − Vt ) = 2k ' I D L L
– The transconductance calculated in the above expression is valid for smallsignal analysis only – To determine the limitation of this analysis let us consider the total current in the above circuit:
k' W k' W 2 Id = (VGS + vi − Vt ) = (VGS − Vt ) 2 + 2(VGS − Vt )vi + vi2 2 L 2 L k' W I D + id = I D + 2(VGS − Vt )vi + vi2 2 L ⎡ ⎤ vi W id = k ' (VGS − Vt )vi ⎢1 + ⎥ L ⎣ 2(VGS −V t) ⎦
[
]
[
]
if the magnitude of the small − signal input vi is much less than 2Vov id ≈ g m vi
– If the magnitude of the smallsignal input vi is less than 20% of Vov, the small signal analysis is accurate within about 10%.
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GatetoChannel Capacitance: • The intrinsic capacitance due to MOS gate and channel structure can be approximated as a simple parallel plate capacitance given by Cgc = CoxWL • The gate of a MOSFET is separated from the channel by a thin oxide, which has a per unit area capacitance equal to Cox = εox/tox • However, the bottom plate of this capacitor depends on the mode of the operation of the transistor. So the capacitance varies in both magnitude and in its division, depending on the operation region and terminal voltage • In linear region a conducting channel exists from source to drain. Symmetry dictates that the capacitance is evenly distributed between drain and source. Hence Cgs = Cgd = CoxWL/2 • In saturation the channel is pinchedoff at the drain end. The capacitance Cgd between gate and drain is approximately zero. All the capacitance is therefore between gate and source, which is approximately given by: Cgs = (2/3)CoxWL
G CGC S D S G CGC D S
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Small Signal Elements – Intrinsic Cgs and Cgd
G CGC D
Input and Output Resistance
• Input Resistance:
– MOSFET gate is insulated from the channel. – At low frequency gate current is almost zero – Consequently, the input resistance is almost infinite
•
Output Resistance:
– Due to channel length modulation drain current (ID) in saturation region increases with the increase of drain voltage (VDS). Δ V DS – Small signal output resistance is defined as: ro = ΔID
The change in drain current Δ I D due to a change Δ V DS can be given by ΔI D = ∂I D Δ V DS ∂ V DS
– After simplification we get:
Δ V DS V 1 = A = = ro ΔID ID λID
– Here ro is the small signal output resistance
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Basic Small Signal Model
• • • • Combination of the above elements produces the small signal model for an NMOS transistor in saturation or active region. This model is called hybridπ model This model predicts that when gatesource voltage is increased the incremental current id flowing from drain to source increases. Since DC current ID also flows from drain to source in an NMOS, increasing the gatesource voltage also increases the total current Id.
•
This model is also valid for PMOS model.
– Here also the incremental current id flowing from drain to source increases with gatesource voltage. – However, the DC current ID in PMOS flows from source to drain, since source acts as the source for holes. Therefore, id flows in the opposite direction of ID, reducing the total drain current Id.
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Including Non Ideal Behavior in Small Signal Model
• Body Effect
• • • • • Drain current depends on two voltage: VGS and VBS. VGS controls channel conductivity VBS controls threshold voltage, which changes drain current when VGS is fixed Body acts like second gate This is called body effect
•
Transconductance terms required to model transistor:
– Transconductance associated with the main gate (gm) – Transconductance associated with the body or second gate (gmb)
ID k' W = (V GS − V t ) 2 (1 + λ V DS ) 2 L
g mb =
– Here
∂I D ∂Vt W = −k ' (VGS − Vt )(1 + λVDS ) ∂VBS L ∂VBS
⇒ ∂Vt γ =− = −χ ∂VBS 2 2φ f + VSB
Vt = Vt 0 + γ ( 2φ f + VSB − 2φ f ) Here,
χ is the rate change of Vt w.r.t. VSB
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Including Non Ideal Behavior in Small Signal Model
• Transconductance terms required to model transistor: – Therefore, transconductance associated with the body or second gate (gmb) can be expressed as:
g mb If g mb
γk ' (W / L)(VGS − Vt )(1 + λVDS ) = 2 2φ f + VSB λVDS << 1 γk ' (W / L)(VGS − Vt ) k ' (W / L) I D = =γ 2(2φ f + VSB ) 2 2φ f + VSB
– The ratio gmb/gm is an important quantity:
g mb γ = =χ gm 2 2φ f + V SB The value of
χ typically
in the range
of
0 .1 − 0 .3
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Including Non Ideal Behavior in Small Signal Model
• Parasitic Elements in Small Signal Model – Sourcebody junction capacitance (Csb) – Drainbody junction capacitance (Cdb)
⎛ VSB ⎞ ⎛ VDB ⎞ ⎜1+ ⎟ ⎜1+ ⎟ ⎜ ψ ⎟ ⎜ ψ ⎟ 0 ⎠ ⎝ ⎝ ⎠ • Here Csb0 and Cdb0 are the sourcebody and drainbody junction capacitance0 when VSB and VDB are 0.\ Csb = Csb0
1/ 2
and Cdb =
Cdb0
1/ 2
• ψ0 is the built in potential of the junction
– Gatebody capacitance (Cgb)
• It models parasitic oxide capacitance between gate contact material and the substrate outside the active device area • It models coupling from polysilicon and metal interconnects to the substrate
– Gatedrain capacitance (Cgd)
• Although this component is considered zero for saturation region, there will be a component due to overlap capacitance between gate and drain
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Including Non Ideal Behavior in Small Signal Model
• After Including all the parasitic elements small signal model for MOS transistor will be as shown below:
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Reference Books
• Analysis and Design of Analog Integrated Circuits (4th Edition) (Hardcover) by Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer • VLSI Design Techniques for Analog and Digital Circuits (McgrawHill Series in Electrical Engineering) by R.L. Geiger, P.E. Allen and N.R. Strader, McGrawHill, 1990 (ISBN 0070232539)
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