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MSP430 Teaching Materials

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Lecture 8 Direct Memory Access (DMA) & Communications Introduction


Texas Instruments T I t t Incorporated I t d University of Beira Interior (PT)
Pedro Dinis Gaspar, Antnio Esprito Santo, Bruno Ribeiro, Humberto Santos y of Beira Interior, , Electromechanical Engineering g g Department p University www.msp430.ubi.pt >> Contents
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Contents (1/2)
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Direct Memory Access (DMA) capability DMA configuration and operation: Block diagram Features System and DMA interrupts DMA transfers DMA Registers

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Contents (2/2)
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Communication Introduction Communications system model Transmission mode Serial communications Synchronous and asynchronous serial communications Peripheral Interface Serial (SPI) protocol I2C (Inter-Integrated g Circuit) protocol MSP430 communications interfaces
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DMA capability (1/3)


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The MSP430 has been q g low p power; ; requiring

designed

for

applications

When the application requires data-handling, the direct y access ( (DMA) ) capability p y included in some memory devices is useful: 5xxx; FG4xx(x); F261x; F16x(x) and F15x; Among g these: MSP430FG4618 ( (Experimenters p board). ) DMA automatically handles data; DMA does not require CPU intervention; DMA helps reduce the power consumption (CPU remains sleeping).

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DMA capability (2/3)


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Concept of DMA: move functionality to peripherals: Peripherals P i h l use l less current t than th the th CPU; CPU Delegating control to peripherals allows the CPU to shut down ( (saves p power); ); Intelligent peripherals are more capable, providing a better opportunity for CPU shutoff; DMA can be enabled fo for repetitive epetiti e data handling, handling increasing inc easing the throughput of peripheral modules; Minimal software requirements q and CPU cycles. y

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DMA capability (3/3)


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The following TI Application Reports cover the use of the DMA controller for different applications applications, with the aim of lowering power consumption: Streamlining the mixed-signal path with the signal-chainon-chip MSP430F169 <slyt078.pdf> Interfacing the MSP430 with MMC/SD Flash Memory Cards <slaa281b.pdf> Digital FIR Filter Design Using the MSP430F16x <slaa228 pdf> <slaa228.pdf> Using the USCI I2C Master <slaa382.pdf>
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DMA configuration and operation (1/9)


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Block diagram:

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DMA configuration and operation (2/9)


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DMA controller features: Three independent transfer channels; Configurable (ROUNDROBIN bit) DMA channel priorities: Default: DMA0DMA1DMA2; DMA Transfer cycle time: Requires only two MCLK clock cycles per transfer; Each byte/word transfer requires: 2 MCLK cycles after synchronization; 1 MCKL cycle of wait time after transfer.

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DMA configuration and operation (3/9)


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DMA controller features: Block sizes up to 65535 bytes or words; Configurable g edge/level-triggered g / gg transfer ( (DMALEVEL bit). ) Byte or word and mixed byte/word transfer capability: Byte-to-byte; B t t b t Word-to-word; Byte-to-word y (upper ( pp byte y of the destination word is cleared); Word-to-byte (lower byte of the source word is transferred).

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DMA configuration and operation (4/9)


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DMA controller features: Four addressing modes for each DMA channel are independently configurable (DMASRCINCRx and DMADSTINCRx control bits): Fixed address to fixed address; Fixed address to block of addresses; Block of addresses to fixed address; Block of addresses to block of addresses.

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DMA configuration and operation (5/9)


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DMA controller features: Six transfer modes (each channel is individually configurable by the DMADTx bits):
DMADTx 000 001 010, 011 100 101 110, 111 Transfer mode Single transfer Block transfer Burst-block transfer Repeated single transfer Repeated block t transfer f Repeated burst-block transfer Description Each transfer requires a trigger l bl block ki is transferred f d A complete with one trigger CPU activity is interleaved with a block transfer Each transfer requires a trigger A complete block is transferred with ith one trigger t i CPU activity is interleaved with a block transfer DMAEN after transfer 0 0 0 1 1 1

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DMA configuration and operation (6/9)


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System interrupts: DMA transfers are not interruptible by system interrupts interrupts, but system ISRs can be interrupted by DMA transfers; Onl Only NMI inte interrupts pts can be gi given en priority p io it over o e the DMA controller (ENNMI bit is set). If the ENNMI bit is not set, system interrupts remain pending until the completion of the transfer. transfer

DMA controller interrupts: Each DMA channel has its own DMAIFG flag that is set when the corresponding p g DMAxSZ register g counts to zero ( (all modes); If the corresponding DMAIE and GIE bits are set, an interrupt request is generated.
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DMA configuration and operation (7/9)


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DMA controller interrupts: The MSP430FG4618 implements the interrupt vector register DMAIV; All DMAIFG fl flags are prioritized i iti d and d combined bi d t to source a single interrupt vector; DMAIV is used to determine which flag requested an interrupt.

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DMA configuration and operation (8/9)


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DMA transfers: USCI_B I2C module with DMA: Two trigger sources for the DMA controller; Triggers a transfer when new I2C data is received and when data is required for transmit. ADC12 with DMA: Automatically moves data from any ADC12MEMx register to another location. location DAC12 with DMA: Automatically moves data to the DAC12_xDAT register.

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DMA configuration and operation (9/9)


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DMA transfers: DMA with flash memory: Automatically moves data to the Flash memory; Performs the data move data word/byte to the Flash; The write timing control is done by the Flash controller; Write transfers to the Flash memory succeed if the Flash controller set-up is done before the DMA transfer and if the Flash is not busy.

All DMA transfers: Occur without CPU intervention; Operate independently of any low-power modes; Increase throughput of modules. modules
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15

DMA Registers (1/11)


UBI

DMACTL0, DMA Control Register 0 (FG4618)


15 14 13 12 11 10 9 8

Reserved
7 6 5 4 3

DMA2TSELx
2 1 0

DMA1TSELx

DMA0TSELx

All DMAxTSELx registers are the same.

DMAxTSELx 0000 0001 0010


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Transfer triggered when DMAREQ = 1 (DMAREQ = 0 automatically when the transfer starts) <Timer_A> when TACCR2 CCIFG = 1 (CCIFG = 0 automatically when the transfer starts) If CCIE = 1, CCIFG wont trigger a transfer <Timer_B> when TBCCR2 CCIFG = 1 (CCIFG = 0 automatically when the transfer starts) If CCIE = 1, 1 CCIFG wont trigger i a transfer f
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DMA Registers (2/11)


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DMACTL0, DMA Control Register 0 (FG4618) (continued)


DMAxTSELx Transfer triggered <USART0>: when URXIFG0 = 1 (URXIFG0 = 0 automatically when the transfer starts) If URXIE0 = 1, 1 URXIFG0 flag fl wont t trigger t i a transfer t f <USCI_A0>: when UCA0RXIFG = 1 (UCA0RXIFG = 0 automatically ( y when the transfer starts) ) If UCA0RXIE = 1, UCA0RXIFG flag wont trigger a transfer <USART0>: when UTXIFG0 =1 (UTXIFG0 = 0 automatically when the transfer starts) If UTXIE0 = 1, UTXIFG0 flag wont trigger a transfer <USCI_A0>: when UCA0TXIFG = 1 (UCA0TXIFG = 0 automatically when the transfer starts) UCA0TXIE = 1, UCA0TXIFG flag wont trigger a transfer <DAC12> when DAC12_0CTL DAC12IFG = 1 (DAC12IFG = 0 automatically when the transfer starts) If DAC12IE = 1, DAC12IFG wont trigger a transfer
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0011

0100

0101
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DMA Registers (3/11)


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DMACTL0, DMA Control Register 0 (FG4618) (continued)


DMAxTSELx Transfer triggered <ADC12> when ADC12IFGx = 1 (corresponding ADC12IFGx flag for single-channel conversions, and the ADC12IFGx for the last conversion for sequence q conversions) ) (All ADC12IFGx = 0 automatically when the associated ADC12MEMx register is accessed by the DMA controller) <Timer_A> when TACCR0 CCIFG = 1: CCIFG = 0 automatically when the transfer starts If CCIE = 1, CCIFG flag wont trigger a transfer <Timer_B> when TBCCR0 CCIFG = 1 (CCIFG = 0 automatically when the transfer starts) If CCIE = 1, CCIFG wont trigger a transfer <USART1>: when URXIFG1 = 1 (URXIFG1 = 0 automatically when the transfer starts) If URXIE1 = 1, URXIFG0 flag wont trigger a transfer

0110

0111 1000

1001

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DMA Registers (4/11)


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DMACTL0, DMA Control Register 0 (FG4618) (continued)


DMAxTSELx 1010 1011 1100 Transfer triggered gg <USART1>: when UTXIFG1 =1 (UTXIFG1 = 0 automatically when the transfer starts) If UTXIE1 = 1 1, UTXIFG0 flag wont won t trigger a transfer <Hardware Multiplier> when the hardware multiplier is ready for a new operand <USCI_B0>: when UCB0RXIFG = 1 (UCB0RXIFG = 0 automatically when the transfer starts) If UCB0RXIE = 1, UCB0RXIFG flag wont trigger a transfer <USCI_B0>: when UCB0TXIFG = 1 (UCB0TXIFG = 0 automatically when the transfer starts) UCB0TXIE = 1, UCB0TXIFG flag wont trigger a transfer when the DMAxIFG = 1: DMA0IFG triggers channel 1 DMA1IFG triggers channel 2 DMA2IFG triggers channel 0 (None of the DMAxIFG = 0 automatically when the transfer starts) When an external trigger DMAE0 = 1
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1101

1110

1111
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DMA Registers (5/11)


UBI

DMACTL1, DMA Control Register 1 (FG4618)


15 14 13 12 11 10 9 8

0
7

0
6 5

0
4

0
3

0 0

0
2 DMAONFETCH

0
1 ROUNDROBIN

0
0 ENNMI

Bit 2

DMAONFETCH

1 0

ROUNDROBIN ENNMI

Description DMA on fetch: DMAONFETCH = 0 DMA transfer occurs immediately DMAONFETCH = 1 DMA transfer t f occurs on next t instruction i t ti fetch f t h after ft the trigger Round robin: ROUNDROBIN = 0 DMA channel priority is DMA0 DMA1 DMA2 ROUNDROBIN = 1 DMA channel priority changes with each transfer Enable NMI when ENNMI = 1, allowing NMI interrupt to interrupt a DMA transfer

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20

DMA Registers (6/11)


UBI

DMAxCTL, DMA Channel x Control Register (FG4618)


15 14
6 DMASRCBYTE

13

12
4

11
3

10
2

9
1 DMAABORT

8
0

Reserved
7 DMADSTBYTE

DMADTx
5 DMALEVEL

DMADSTINCRx
DMAEN DMAIFG DMAIE

DMASRCINCRx
DMAREQ

Bit 14-12

DMADTx

Description p DMA transfer mode: DMADT2 DMADT1 DMADT0 DMADT2 DMADT1 DMADT0 DMADT2 DMADT1 DMADT0 DMADT2 DMADT1 DMADT0 DMADT2 DMADT1 DMADT0 DMADT2 DMADT1 DMADT0 DMADT2 DMADT1 DMADT0 transfer DMADT2 DMADT1 DMADT0 transfer

= = = = = = =

000 001 010 011 100 101 110

Single transfer Block transfer Burst block transfer Burst-block Burst-block transfer Repeated single transfer Repeated block transfer Repeated burst-block

= 111 Repeated burst-block

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DMA Registers (7/11)


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DMAxCTL, DMA Channel x Control Register (FG4618) (continued)


15 14 6 DMASRCBYTE 13 12 4 11 3 10 2 9 1 DMAABORT 8 0

Reserved
7 DMADSTBYTE

DMADTx
5 DMALEVEL

DMADSTINCRx DMAEN DMAIFG DMAIE

DMASRCINCRx DMAREQ

Bit 11-10

DMADSTINCRx

Description DMA destination address increment/decrement after each byte or word transfer: When DMADSTBYTE = 1, the destination address increments / decrements by one When DMADSTBYTE = 0, the destination address increments/ d decrements t b by two. t DMADSTINCR1 DMADSTINCR0 = 00 Address unchanged DMADSTINCR1 DMADSTINCR0 = 01 Address unchanged DMADSTINCR1 DMADSTINCR0 = 10 Address decremented DMADSTINCR1 DMADSTINCR0 = 11 Address increment
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DMA Registers (8/11)


UBI

DMAxCTL, DMA Channel x Control Register (FG4618) (continued)


15 14 6 DMASRCBYTE 13 12 4 11 3 10 2 9 1 DMAABORT 8 0

Reserved
7 DMADSTBYTE

DMADTx
5 DMALEVEL

DMADSTINCRx DMAEN DMAIFG DMAIE

DMASRCINCRx DMAREQ

Bit 9-8

DMASRCINCRx

Description DMA source address increment/decrement after each byte or word transfer: When DMASRCBYTE = 1, the source address increments/decrements by one When DMASRCBYTE = 0, the source address i increments/decrements t /d t b by t two. DMASRCINCR1 DMASRCINCR0 = 00 Address unchanged DMASRCINCR1 DMASRCINCR0 = 01 Address unchanged DMASRCINCR1 DMASRCINCR0 = 10 Address decremented DMASRCINCR1 DMASRCINCR0 = 11 Address increment
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DMA Registers (9/11)


UBI

DMAxCTL, DMA Channel x Control Register (FG4618) (continued)


15 14 6 DMASRCBYTE 13 12 4 11 3 10 2 9 1 DMAABORT 8 0

Reserved
7 DMADSTBYTE

DMADTx
5 DMALEVEL

DMADSTINCRx DMAEN DMAIFG DMAIE

DMASRCINCRx DMAREQ

Bit 7 6 5 4 3 2 1 0
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DMADSTBYTE DMASRCBYTE DMALEVEL DMAEN DMAIFG DMAIE DMAABORT DMAREQ

Description DMA destination length (byte or word): DMADSTBYTE = 0 Word DMADSTBYTE = 1 Byte DMA source length (byte or word): DMASRCBYTE = 0 Word DMASRCBYTE = 1 Byte DMA level: DMALEVEL = 0 Edge sensitive trigger (rising edge) DMALEVEL = 1 Level sensitive trigger (high level) DMA enable when DMAEN = 1 DMA interrupt flag DMAIFG = 1 when interrupt pending DMA interrupt enable when DMAIE = 1 DMA Abort DMAABORT = 1 when a DMA transfer is interrupted b NMI by DMA request DMAREQ = 1 starts DMA
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DMA Registers (10/11)


UBI

DMAxSA, DMA Source Address Register (FG4618) 32 32-bit bit register points to the DMA source address for single transfers or the first source address for block transfers. DMA DMAxDA, DA DMA D Destination i i Add Address Register R i (FG4618) 32-bit register points to the DMA destination address for single g transfers or the first source address for block transfers. For both F b th registers i t (DMAxSA (DMA SA and d DMAxDA): DMA DA) Bits 3120 are reserved and always read as zero; Reading or writing to bits 19-16 19 16 requires the use of extended instructions; When writing to DMAxSA or DMAxDA with word i t instructions, ti bit bits 19 19-16 16 are cleared. l d
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DMA Registers (11/11)


UBI

DMAxSZ, DMA Size Address Register (FG4618) The 16-bit DMA size address register defines the number of bytes/words of data per block transfer: DMAxSZ decrements with each word or byte transfer; When DMAxSZ = 0, it is immediately and automatically reloaded with its previously initialized value. DMAIV DMAIV, DMA Interrupt Vector Register (FG4618) 16 bit DMAIV value only uses bits 3 to 1 (other bits = 0); DMAIV content provides the interrupt source priority: DMAIV = 02h: DMA channel 0 (highest priority); DMAIV = 04h: DMA channel 1; DMAIV = 06h: DMA channel 2; DMAIV = 0Eh: Reserved (lowest priority).
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Introduction
UBI

An important feature of modern microprocessor based y is their communication capability, p y, that is, , their systems ability to exchange information with other systems in the surrounding environment; At the low level, communications interfaces are used to download a firmware update or to set up local configurations (e (e.g. g turn features on or off) off), amongst other tasks; At a higher level, communication interfaces are used to exchange information in distributed applications.

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Communications system model (1/2)


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Digital communication devices: Transmitter: Has the task of putting the information into the appropriate pp p format for subsequent q transmission; ; Receiver: Is responsible for collecting the message that has been sent and e extracting t acting the o original iginal info information; mation Communication medium: The physical medium through which the information flows and is commonly implemented as: Twisted pair wire; Fibre optic cable; Radio frequency transmission.
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Communications system model (2/2)


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Devices participating in a digital communication system: DTE: DTE D Data t T Terminal i lE Equipment; i t DCE: Data Communications Equipment.

Transmitter Transmission medium

Receiver

DTE

DCE

DCE

DTE

Receiver

Transmitter

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Transmission mode (1/5)


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Communications between digital devices can be divided into two types : Parallel communications; Serial communications.

Parallel communications: The physical transmission medium has independent signal lines in numbers equal to the transmitted digital word bits; The information transmitted at any given instant is the data word d formed f d by b the h logical l l levels l l on the h various signal ll lines.

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Transmission mode (2/5)


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Parallel communications: Example: E l Ch Character t ASCII W parallel ll l transmission. t i i

Information flow
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Transmission mode (3/5)


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Serial communications: Physical transmission medium needs only one signal line; The information transmitted is provided by the transmitter as a sequence of f bits, bit sent t at t the th rate t established t bli h d between b t the transmitter and the receiver; Additional information is needed to enable the synchronization between the receiver and transmitter: Start bit: Added to the beginning of the information transmitted, so that the receiver can identify the beginning of a new transmission; Stop bit(s): Added to the end of the information transmitted to indicate that the data value is complete.
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Transmission mode (4/5)


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Serial communications: Example: E l Ch Character t ASCII W serial i l transmission: t i i

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Transmission mode (5/5)


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Advantages and disadvantages of parallel and serial communication:


Characteristic B s line Bus Sequence Transmission rate Bus length Cost All Parallel One line per pe bit bits of one simultaneously word One line Sequence of bits Low Short and long distances Low Serial

High Short distances High

Asynchronous transmission Synchronisation between needs start and stop bits Critical the different bits is Synchronous transmission characteristics demanding needs some other synchronisation h
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Serial communications (1/3)


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The start bit identifies the beginning of a data transfer and is generated by a high high-to-low to low transition on the bus; Following the start bit are the data bits. In this example, the ASCII code for the text transfer uses seven data bits; The error-checking bit (parity bit) is sent after the data bits; To terminate the transmission, one or two stop bits are issued; Using seven data bits, the complete message can use one or two stop bits. Using eight data bits, only one stop bit is available for transmission. transmission
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Serial communications (2/3)


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Parity bit: Used U dt to verify if th the integrity i t it of f information i f ti transmitted; t itt d The bit is added by the transmitter and indicates whether the total sum of the numbers "1" in the message data is odd or even; The transmissions can be configured for odd or even parity.

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Serial communications (3/3)


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Baud rate example: The Th t transmission i i of f W W: Character uses seven data bits; Four bits are used for control, making a total of 11 bits. This corresponds to 11 baud; If the characters are transmitted at a rate of 10 characters per second, the baud rate will be: 10x11 = 1100 baud/s.

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37

UBI

Synchronous and asynchronous serial (1/2) / ) communications (

Serial communications may be: Asynchronous: where the transmission rate (baud rate) is fixed by the transmitter and the receiver works at the same baud rate, using the transmitted start bit to synchronize the start of a new message; Synchronous: where there is a separate synchronization clock signal connected between the receiver and the transmitter. transmitter Synchronous communications: Normally one unit assumes the role of master and one or more of the other units take the role of slaves; The clock signal g g generated by y the master is used by y the slave units to transfer data in/out of the TX and RX registers; It is possible for a device to transmit and receive simultaneously.
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38

UBI

Synchronous and asynchronous serial (2/2) / ) communications (

Asynchronous communications: Characterised Ch t i d by b the th absence b of f any synchronization h i ti clock l k signal between the units; The transmission in this mode does not allow simultaneous transmission and reception, that is, when one device transmits the other devices just listen. listen

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39

UBI

Serial Peripheral Interface (SPI) protocol (1/2) ( / )

The Serial Peripheral Interface ( SPI) bus is a standard form of synchronous serial communication; Developed p by y Motorola; ; Operates in full duplex mode; Master/Slave relationship; Communications are always initiated by the master. Low cost.
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UBI

Peripheral Interface Serial (SPI) protocol (2/2) ( / )

Supports only one master; Can support more than a slave; Short distance between devices, e.g. on a printed circuit boards (PCBs); Special attention needs to be observed to the polarity and phase of the clock signal; The master sends data on one edge of clock and reads d data on the h other h edge. d Therefore, h f i can send/receive it d/ i at the same time.

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41

I2C (Inter-Integrated Circuit) protocol (1/3)


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Multi-master synchronous serial computer bus; Invented by Philips Semiconductors; Developed with the main objective of establishing links between integrated circuits and to connect low-speed peripherals; Based on a two bi-directional open-drain lines pulled up with resistors: SDA: Serial Data; SCL: Serial clock. Typical voltages used are +5.0 V or +3.3 V, although systems with other voltages are possible.
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42

I2C (Inter-Integrated Circuit) protocol (2/3)


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Communications is always initiated and completed by the master, which is responsible for generating the clock signal; In more complex applications, applications I2C can operate in multimulti master mode; The slave selection by the master is made using the seven-bit address of the target slave; The master (in transmit mode) sends: Start bit; 7-bit 7 bit address of the slave it wishes to communicate with; A single bit representing whether it wishes to write (0) to or read (1) from the slave; The h target slave l will ll acknowledge k l d its address. dd
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I2C (Inter-Integrated Circuit) protocol (3/3)


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Example of an I2C communication system:

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MSP430 communications interfaces (1/2)


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Equipped with three serial communication interfaces: USART (Universal Synchronous/Asynchronous Receiver/Transmitter): UART mode; SPI mode; d I2C (on F15x/F16x only). USCI (Universal Serial Communication Interface): UART with Lin/IrDA support; SPI (Master/Slave, (Master/Slave 3 and 4 wire modes); I2C (Master/Slave, up to 400 kHz). USI (Universal Serial Interface): SPI (Master/Slave, 3 & 4 wire mode); I2C (Master/Slave, (Master/Slave up to 400 kHz). kHz)
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MSP430 communications interfaces (2/2)


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Comparison between the communication modules:


USART UART: - Only one modulator - n/a - n/a - n/a SPI: - Only one SPI available - Master and Slave Modes - 3 and 4 Wire Modes (on 15x/16x only) - Master and Slave Modes - up to o 400kbps 00 bp
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USCI UART: - Two modulators support n/16 timings - Auto baud rate detection - IrDA encoder & decoder - Simultaneous USCI_A USCI A and USCI_B (2 channels) SPI: - Two SPI (one on each USCI_A and USCI_B) - Master and Slave Modes - 3 and 4 Wire Modes I2C: - Simplified interrupt usage - Master and Slave Modes - up t to 400kbps 400kb
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USI

SPI: - Only one SPI available - Master and Slave Modes I2C: - SW state machine needed - Master and Slave Modes
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I2C: