ESc201:IntroductiontoElectronics

Sequential Circuit Design -1 Fli Flop Flip Fl / Latch L t h

Dr. K D K. V V. S Srivastava i t Dept. of Electrical Engineering IIT Kanpur

1

Digital Circuits

Combinational Circuits
X CC Y W

Sequential Circuits
X CC Z

Storage elements

Output p is determined by y current values of inputs only.

Output is determined in general by current values of inputs and past values of inputs/outputs as well.
2

NOR SR Latch
R
1 0

Q = 1; Q = 0 Set State Q = 0; Q = 1 Re set State

S 1

R 0

Q 1

Q 0

State SET

NOR SR Latch
Reset
R

Q = 1; Q = 0 Set State Q = 0; Q = 1 Re set State

0 S Set

S 1 0

R 0 1

Q 1 0

Q 0 1

State SET RESET

HOLD State
R

1 0
Q

1 0 S 0
Q

S 1 0 0 1

R 0 1 0 1

Q 1 0 Q 0

Q 0 1 Q 0

State SET RESET HOLD INVALID

5

0 Q Both the outputs are well defined and 0. The first problem is that we do not get complementary output.
Q

1
S

A more serious problem occurs when we switch the latch to the hold state by changing RS from 11 00 . Suppose the inputs do not change simultaneously and we get the situation 11 01* 00
R

1
Q

1 Q=1

0
6

1
Q

1 Q=1

S Suppose th the i inputs t change h as RS = 11 10* 00

R

0
Q

0 Q=0

So although output is well defined when we apply RS = 11, it becomes unpredictable once we switch the latch to hold state by applying RS = 00. That 7 is why RS = 11 is not used as an input combination.

The error can occur also due to unequal gate delays.

R

1
1

0
1

0 0
1

Q S

Suppose gate gate-1 1 is faster On the other hand suppose that gate-2 is faster. 1
1

Q=1

0
1

0
1

0
2

Q S

1
8

Again the output is unpredictable in general

Q=0

NAND Latch
S Q

S 0 1 1 0

R 1 0 1 0

Q 1 0 Q 1

Q 0 1 Q 1

State SET RESET HOLD INVALID

RS NAND Latch with Enable

S

1
Q

EN

0 1
Q

Hold State

S
Q

Enable 0 1

S R x x 1 0 0 1 0 0 1 1

Q Q Q Q 1 0 0 1 Q Q 0 0

State Hold Set Reset Hold Invalid

EN

1
R

1 1

10

D latch
S EN R Q Q D
1 1 1

S EN

Q Q

1 0

R 0

Enable 0 1 1 1 1

S R x x 1 0 0 1 0 0 1 1

Q Q Q Q 1 0 0 1 Q Q 0 0

State Hold Set Reset H ld Hold Invalid

D EN

Q Q

If EN = 1 then Q = D otherwise the latch is in Hold state

11

Problem with Latch

1

zn

D clk

yn

Circuits are designed with the idea there would be single change in output or memory state t t in i single i l clock l k cycle. l

clk

y z

12

Edge Triggered Latch or Flip-flop

D clk Q

Clock

Positive edge triggered flipflop

13

Negative Edge Triggered Latch or Flip-flop

D clk Q

Clock

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Master-Slave D Flip-flop
D D D Q

master
EN EN

slave
Q

clk

Clock

Master Slave

clk

How do convert this into a positive edge triggered D flip-flop?

15

Positive edge triggered D Flip-flop

1

1
5

0 0
Q

0 1
clk
3

1 0
R

1 1

0
D

16

Positive edge triggered D Flip-flop

1

1 1 0

0 1
5

0 1
clk

1
3

1 0

1
D

17

Positive edge triggered D Flip-flop

1

0
5

1
Q

1
clk
3

1
R

1 0
D

0 1

18 A change in input has no effect if it occurs after the clock edge

JK Flip-flop

Q 0 0 0 0 1 1 1 1

J 0 0 1 1 0 0 1 1

K 0 1 0 1 0 1 0 1

Q(t+1) 0 Q(t + 1) = JQ (t ) + K Q(t ) 0 1 1 1 JK flip flop is refinement of RS flip 0 flop where indeterminate state of RS flip flop is defined in JK Flip Flop. 1 19 0

Toggle or T Flip-flop

Q 0 0 1 1

T 0 1 0 1

Q(t+1) 0 1 1 0

Q(t + 1) = T Q(t )

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Characteristic table
Given a input and the present state of the flip-flop, what is the next state of the flip-flop

D Flip-flop
D clk Q
Inputs p (D) ( ) Q(t+1) ( )

0 1

0 1

Characteristic equation:

Q(t + 1) = D
Q(t) 0 1 () Q(t)

JK Flip Flip-flop flop

Inputs J

K Q(t+1) 0 1 0 1

J clk K

0 0 1 1

Characteristic equation:

Q(t + 1) = JQ (t ) + K Q(t )
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Toggle or T Flip-flop
Inputs (T) Q(t+1)

T clk

0 1

Q(t) Q( ) Q(t)

Characteristic equation:

Q(t + 1) = T Q(t )

Excitation Table
What inputs are required to effect a particular state change Excitation Table
Inputs

Q 0 0 1 1

T 0 1 0 1

Q(t+1) 0 1 1 0

Q(t) 0 0 1 1

Q(t+1) 0 1 0 1

T 0 1 1 0
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Excitation Table
J K 0 1 0 1 Q(t+1) Q( ) Q(t) 0 1 Q(t)

Inputs Q(t) Q( ) 0 0 1 1 Q(t+1) Q( ) 0 1 0 1

J 0 1 X X

K X X 1 0

J clk K

0 0 1 1

Characteristic Table

E it ti Excitation Table T bl

Q 0 0 0 0 1 1 1 1

J 0 0 1 1 0 0 1 1

K 0 1 0 1 0 1 0 1

Q(t+1) 0 0 1 1 1 0 1 0
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Excitation Table
D clk Q
D 0 1 Q(t+1) 0 1

Characteristic Table

Q 0 0 1 1

D 0 1 0 1

Q(t+1) 0 1 0 1

Inputs Q(t) 0 0 1 1 Q(t+1) 0 1 0 1

D 0 1 0 1

Excitation Table
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Convert a D FF to JK FF
J
J D Q

K
X X 1 0

Q Q(t+1) D 0 0 1 1 0 1 0 1
0 1 0 1

0 1 X X

CC
K

clk

Inputs Q(t) 0 0 1 1 Q(t+1) 0 1 0 1

Inputs Q(t) 0 0 1 1 Q(t+1) 0 1 0 1

J 0 1 X X

K X X 1 0

D 0 1 0 1
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Excitation Table

Excitation Table

Convert a D FF to JK FF

J
J D Q

K
X X 1 0

Q Q(t+1) D 0 0 1 1 0 1 0 1
0 1 0 1

0 1 X X

CC
K

clk

1 1

1 1

D = Q.J + Q.K
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Convert a D FF to JK FF

D = Q.J + Q.K

Q 0 0 0 0 1 1 1 1

J 0 0 1 1 0 0 1 1

K 0 1 0 1 0 1 0 1

D
0 0 1 1 1 0 1 0

Q(t+1)
0 0 1 1 1 0 1 0

Inputs J

K Q(t+1) 0 1 0 1 Q(t) 0 1 Q(t)

0 0 1 1

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