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2010 IEEE Symposium on Industrial Electronics and Applications (ISIEA 2010), October 3-5, 2010, Penang, Malaysia

High Efficiency THIPWM Three-Phase Inverter for Grid Connected System

M.A.A. Younis 1 1 Dept. of Electrical Power Engineering, UNITEN, Selangor, Malaysia E-Mail: amahmoud@uniten.edu.my

AbstractThis paper presents a grid connected system. Three phase DC-AC inverters used to convert the regulated DC power to AC power suitable for grid connection. Third harmonic injection PWM (THIPWM) was employed to reduce the total harmonic distortion and for maximum use of the voltage source. DSP was used to generate the accurate THIPWM for grid connection, by synchronizing the inverter voltage with the grid voltage. The application of THIPWM to parallel connected inverter reduces the total harmonic distortion and increases efficiency of the inverter. Experimental results validate the developed model and the proposed system.

Keywords: Three-phase inverter, Third harmonic injection PWM, inverters parallel connection.

I. INTRODUCTION

To avoid introducing extra distortions to the grid power, the generated currents from these inverters should have low harmonics and a high power factor. Furthermore, when the output currents are in phase with the grid voltages, the maximum real output power is achieved by minimizing the reactive component [2]. The grid-connected inverters are desired to have high power-quality, high efficiency, high reliability, low cost, and simple circuitry. With development and utilization of an unstable DC voltage source recently, grid connected inverters are widely used as essential power electronic devices for a grid-connected system. With PWM control technologies, the AC side of the grid-connected inverter has the abilities of controllable power factor, sinusoidal output currents and bi-directional power transfer [3] [4]. The power rating of grid-connected inverter is usually high; therefore switching frequency of the inverter is usually low. The relatively low switching frequency may cause the current harmonic in the output current of the inverter to increase.

The third harmonic injection pulse width modulation method used to control the power factor of the inverter output current and voltage. However, it is very difficult to generate the correct third harmonic amplitude [6] [7]. Generation of sinusoidal PWM is not having the same difficulties but the generated AC voltage is 15% less the maximum voltage can be generated by using THIPWM. In hysteresis control the

N. A. Rahim 2 and S. Mekhilef 3 2, 3 Dept. of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia.

switching frequency varies significantly according to the power level and the DC link [8] [9].

This paper proposes a parallel system where individual inverters connect both DC and AC side directly without additional passive components. The direct connection would reduce the system size and cost. In section II, overall block diagram of the whole system is developed. To get regulated DC voltage at the input of the three phase inverter, PID controller used and its implementation id discussed in section III. Two parallel inverter connection as shown in Figure 1 and THIPWM development is discussed in section IV. The proposed solution for current sharing discussed in section V. however the system efficiency discussed in section VI. Proposed system synchronization with the grid connection developed in section VII. The prototype validation developed and discussed in section VIII. Section IX discuss the main point of contribution in this work

2010 IEEE Symposium on Industrial Electronics and Applications (ISIEA 2010), October 3-5, 2010, Penang, Malaysia High

Figure 1: parallel connected three-phase inverter system

II. Grid Connected System Block Diagram

The block diagram of the grid-connected system is shown in Figure 2. The regulated DC source supplies a power to three-

phase parallel-connected inverter. The parallel connected inverter is the main the concern of this paper. The Six-step modulation uses a sequence of six switch patterns for three- phase full-bridge inverter, to generate a full cycle of three- phase voltages.

978-1-4244-7647-3/10/$26.00 ©2010 IEEE

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Figure 2: The system block diagram along with the link for code composer studio, to automate

Figure 2: The system block diagram

along with the link for code composer studio, to automate code

generation, execution, and communication with the TI

evaluation boards by inserting blocks for optimized functions,

together with the appropriate board peripherals, into the model

[11]. Three ePWM blocks are used to obtain three-phase

THIPWM for the three-phase inverter. Each ePWM block

generates a switching signal for three legs of the inverter, as

shown in Figure 4.

The modulating signal data is generated by using equation 1

and saved in a lookup table. The carrier is provided by the

ePWM block, by applying a suitable PWM setting. The carrier

frequency is calculated from the following equations, when the counter setting is up/down.

TPWM = 2(TBPRD × TTBCLK )

=

1

(2)

FPWM

(3)

 

TPWM

SYSCLKOUT

 

TBCLK

 

(4)

=

 

HSPCLKDIV

×

CLKDIV

Where TPWM is the PWM interval, TBRD is the value saved in the TBPRD register, TTBCLK is the time of one clock cycle, and FPWM is the carrier frequency. The clock frequency is calculated by using equation 4, where SYSCLKOUT is the synchronous clock frequency, 100MHz; HSPCLKDIV is the

High Speed Time-Based Clock Prescale Bits selected to be

one of the following values 1, 2, 4, 6, 8, 10, 12, or 14. CLKDIV is the Time-Base Clock Prescale Bits to be selected as one of the following values 2, 2, 4, 16, 32, 64, or 128. The

PWM cycle (TPWM) is shown in Figure 5.

Figure 2: The system block diagram along with the link for code composer studio, to automate

Figure 4: Three-phase THIPWM Generation

To prevent a short circuit in the DC link at one leg of the inverter, the dead-time period during which both the upper and

III. Inverters in Parallel

In parallel operation, two or more inverters can be tied together to share a load. In this paper, a system of two units is discussed. Figure 3 shows two inverters connected directly at input and the output ends. THIPWM was considered, where

the modulating signal is generated by injecting the third harmonic component to the 50 Hz fundamental component as given in equation 1.

v

ra

=

1.15

sin

t

ω

+

0.19 sin 3

t

ω

V

rb

V

rc

=

=

1.15

sin

⎜ ⎛

t

ω

1.15

sin

⎛ ⎜

t

ω

2 π ⎟ ⎞ ⎠ 4 π ⎟ ⎞ 3 ⎠
2
π
⎟ ⎞
4
π
⎟ ⎞
3

3

+ 0.19 sin 3

t

ω

+

0.19 sin 3

t

ω

(1)

Use of the modulator given in equation 1 will produce THIPWM which maintain the peak of the line voltage equal to the DC voltage level.

Q 1 Q 3 Q 5 Id1+ R1 ID Ia1+ VA VB VC + + DC
Q 1
Q 3
Q 5
Id1+
R1
ID
Ia1+
VA
VB
VC
+
+
DC
DC-DC
IA+
source
-
converter
VDC
Id2+
Three-
Three-
-
Q 4
Q 6
Phase
Phase
Q 2
LC
RL
Filter
Load
Id2-
IA-
Q 1
Q 3
Q 5
R2
Ia2+
VA
VB
VC
Q 4
Q 2
Q 6
Six Patten
THIPWM
DSP
Control Circuit
TMS320F2808 eZdsp

Figure 3: current flowing in three-phase parallel inverters

The Embedded Target for the TI C2000 is used to construct system models and real-time control algorithms within the SIMULINK environment, by using blocks from the SIMULINK block library. The target for the TI C2000 is used

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the lower IGBT of the inverter phase leg are off, must be inserted to the switching signals[12]. The dead-time can cause waveform distortion and decrease the fundamental voltage.

V

CE

1

A

+ I

+

dA

R

11

A

assuming that

=

V

CE

1

B

+ I

+

dB

R

11 B

(7)

Dead-band (DB) module is used to create-dead time for the switches on the same leg . The DB module supports independent values for rising-edge (RED) and falling-edge (FED) delays. The amount of delay is programmed by using the dead-band rising-edge (DBRED) and dead-band falling- edge (DBFED) memory-mapped registers. These are 10-bit registers and their value represents the number of TBCLK periods a signal edge is delayed by. Equation 5 and 6 is used to calculate FED and RED, respectively [13]:

I

+

dA

=

I

+

dB

=

I

D

2

I

D

2

(

R

11

A

R

11

B

)

=

V

CE

1

B

V CE

1

A

or

R

11 A

=

2

(

V

CE

1

B

V CE

1

A

)

I

D

+ R

11

B

(8)

(9)

(10)

FED = DBFED × TTBCLK

RED = DBRED × TTBCLK

Carrier

peak

(5)

(6)

For the right value of R 1 and R 2 , each of them should be much smaller than the load resistance. The circuit will experience

similar current sharing in all the modes of operation as a result

the circulating current will be small.

The power dissipation and the efficiency in three-phase

inverter can be calculated as follow:

- P

AC

(11)

(12)

Modulating Carrier signal RED FED
Modulating
Carrier
signal
RED
FED

TPWM

time

P

  • =

P

 

D

DC

  • P AC

 

η =

p

DC

ePWM1A

ePWM1B

Where P D is the power dissipation of the inverter, P DC is the DC source power, and P AC is the inverter output power. Assuming ripple free current on the DC source, and unity power factor on the AC side the input power and the output power are calculated as

P

DC

=

I

DC

×

V

DC

P

AC ,3φ

= 3

I

ph

× V

ph

(13)

(14)

The inverter power dissipation mainly dissipated on the IGBT’s. The parallel connection improves the switch power dissipation which improves the inverter efficiency. Figure 7 shows a linear approximation of I C versus V CE (on) [1]. It’s shown clearly in the Figure that R EC affecting the voltage V CE , which ultimately affect the IGBT power dissipation.

Figure 5: Switching Interval with Dead Band Time

IV. Efficiency of parallel connected inverter Inverters with different ratings are sometimes connected in parallel especially for system upgrading or to enhance the power rating of any used inverter. In this case, it is desirable for the paralleled converters to share the currents equally. If the inverter uses non-identical IGBT'’s, current sharing and circulating current are to be considered. To study the current sharing and circulating current, Figure 6 shows one mode of operation, where the current I dA+ flowing through Q 1A and Q 1B . However the current I dA- flows back to the source through Q 6A and Q 6b .

the lower IGBT of the inverter phase leg are off, must be inserted to the switching

Figure 6: Current Path during One Switching Cycle

The Figure shows current sharing between Q 1A and Q 1B , with the addition of two series resistors. Current sharing depends on the IGBT’s Q 1A and Q 1B , If V CE1A not equal to V CE1B , I dA + will not be equal to I dB +. To maintain similar current sharing between the two inverters, series resistor R 1 and R 2 are added between each of the six legs and the common point as shown in Figure 3. R 1 box consists of three resistors, R 11 , R 12 , and R 13 . Similarly R 2 consists of R 21 , R 22 , and R 23 . Including the resistances R 11A and R 11B as shown in Figure 6 need satisfy the following condition:

V

CE ON

(

)

=

I

C

×

R

(

CE ON

)

+ V

CE ( Zero )

(15)

By connecting two inverters in parallel, in one switching cycle

two IGBT’s will be connected in parallel which will reduce

the current in each IGBT. And the equivalent resistance of two

IGBTs in parallel will be less. That is reduces the IGBTs power dissipation which will result in better efficiency for the inverter.

the lower IGBT of the inverter phase leg are off, must be inserted to the switching

Figure 7: Linear Approximation of I C versus V CE(on)

the lower IGBT of the inverter phase leg are off, must be inserted to the switching

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V. Grid Connection

This section introduces the three-phase grid connected inverter. Figure 2 shows the block diagram of the overall system connected to the grid. The inverter output voltage has the same frequency and amplitude with those of the grid voltage. The synchronization of the inverter output voltage with the grid voltage must be done in such a way that the two voltages are in phase. The waveform in Figure 8 shows the synchronization process. The signal from the grid is connected to the DSP analog-to-digital converter (ADC) through the voltage sensor after an offset signal was added to it. The DSP program will generate a synchronized THIPWM with a 50Hz fundamental frequency. The signal from the ADC was filtered by using a discrete first-order filter to detect an accurate zero. The detector detects positive zero then generates a square pulse with 50Hz frequency and a duty cycle of 98% to avoid the effect of zero negative detection. The signal will be sent to discrete variable transport delay which will decide the delay needed for power factor correction. After applying the needed delay to the signal, it triggers the THPWM generator to generate the synchronized PWM signal. Figure 9 shows the implementation of zero detecting for synchronization with the power factor correction.

VI. Result and discussion

A parallel connected system was designed and implemented to verify the above discussion. The parameters of the system are as shown in Table 1.

Table 1: System Components and Parameters

 

IGBT for inverter A is SSG60N60

V

CE(ON) =1.75V

IGBT for inverter B is IRGP50B60PD1 V CE (ON )

 

= 2V

Three-phase

LC at grid side L = 1 mH

 

C= 5 μF

inverter

Carrier frequency = 4.5 kHz

 
 

R1= 0.2

 

R1= 0.15

 

IGBT SSG60N60 with V CE(ON) =1.75V

Filter C = 220

μF

DC/DC converter

 

H/F transformer

Carrier frequency= 20 kHz SF-40 EE core from New Favor Industry

The generated three-phase THIPWM synchronized with the grid voltage shown in Figure 11. Figure 12 shows small phase

shift between the phase voltage and phase current on the inverters load side, Grid voltage Phase
shift between the phase voltage and phase current on the
inverters load side,
Grid
voltage
Phase a
Figure 8: Zero Detection for Voltage Synchronization
Phase b
Phase c
Figure 11: Three-phase THIPWM synchronized with the grid voltage (5V/div,
5ms/div)

Figure 9: Block Diagram of Synchronization and Power Factor Correction

The single line diagram of the inverter connected to the grid is shown in Figure 10, Where the grid voltage is stepped down to the level matching the inverter output voltage, through three phase transformer. S 1 connects the power to three phase load from the grid and the inverter. S 2 connects the inverter to the grid.

V. Grid Connection This section introduces the three-phase grid connected inverter. Figure 2 shows the block
V. Grid Connection This section introduces the three-phase grid connected inverter. Figure 2 shows the block
V. Grid Connection This section introduces the three-phase grid connected inverter. Figure 2 shows the block
V. Grid Connection This section introduces the three-phase grid connected inverter. Figure 2 shows the block
V. Grid Connection This section introduces the three-phase grid connected inverter. Figure 2 shows the block
V. Grid Connection This section introduces the three-phase grid connected inverter. Figure 2 shows the block
   
 
V. Grid Connection This section introduces the three-phase grid connected inverter. Figure 2 shows the block
 
V. Grid Connection This section introduces the three-phase grid connected inverter. Figure 2 shows the block
 
V. Grid Connection This section introduces the three-phase grid connected inverter. Figure 2 shows the block
 
V. Grid Connection This section introduces the three-phase grid connected inverter. Figure 2 shows the block

Figure 10: System Connection to the Grid

Phase voltage Phase current 12 >> 1) Ch 1 2) Ch 2 50 V 5 ms
Phase voltage
Phase current
12 >>
1) Ch 1
2) Ch 2
50 V
5
ms
1
5 A
5
ms
2

Figure 12: Phase Voltage and Phase Current on the Load Side (50V/div,

5A/div, 5ms/div)

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With the connection of two inverters in parallel the total harmonic distortion (THD) on the output voltage and current is less than on a single inverter. And efficiency improve by 0.7% Table 2 shows the phase voltage and phase current, the input power, the output power and the harmonic distortion in single and double inverters. Figure 13-16 shows a voltage and current comparison for single inverter and double inverter.

Table 2: Comparison between Parallel Inverters and Single Inverter in Input and Output Power, Current and Voltage THD.

 

Input

Output

Efficiency

Current

Voltage

power

power

THD

THD

(W)

Single

inverter

   
  • 930 1.42%

    • 909 1.43%

97.7%

   

Double

connecte

   
  • 945 1.36%

    • 930 1.28%

98.4%

   

d

inverter

Average input Input voltage current 1 > 2 > 1) Ch 1 100 Volt 5 ms
Average input
Input voltage
current
1
>
2 > 1) Ch 1 100 Volt
5 ms
2) Ch 2 2 Amp
5 ms

Figure 13: The inverter input average voltage and current with single inverter (100V/div, 2A/div, and 10ms/div)

1 > 2 > 1) Ch 1 100 Volt 2) Ch 2 5 Amp 10 ms
1
>
2
>
1) Ch 1 100 Volt
2) Ch 2 5 Amp
10 ms
10 ms
1

2

Figure 14: The inverter output voltage and current with single inverter (100V/div, 5A/div, and 10ms/div)

Average Average input current input voltage 1 > 2 > 1) Ch 1 100 Volt 2)
Average
Average
input current
input voltage
1
>
2
>
1) Ch 1 100 Volt
2) Ch 2 2 Amp
5 ms
5 ms
1
2

Figure 15: The inverter input average voltage and current with parallel

connected inverter (100V/div, 2A/div, and 10ms/div)

1 > 2 > 1) Ch 1 100 Volt 2) Ch 2 5 Amp 10 ms
1
>
2
>
1) Ch 1 100 Volt
2) Ch 2 5 Amp
10 ms
10 ms

Figure 16: The inverter output voltage and current with parallel connected inverter (100V/div, 5A/div, and 10ms/div)

To verify the grid connection capability of the inverter, the connection shown in Figure 10 was prepared. The grid voltage

and the inverter’s output voltage before the grid connection

and after the grid connection is shown in Figure 17.

12 >> 1) Ch 1 100 Volt 10 ms 2) Ch 2 100 Volt 10 ms
12 >>
1) Ch 1 100 Volt 10 ms
2) Ch 2 100 Volt 10 ms

Figure 17: Line Voltage on the Grid and the Inverter Output (100V/div,

10ms/div)

If the switches S 1 and S 2 are closed, both the inverter and the grid will share the current I inv and I grid to the load, as shown in

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Figure 18. If the switch S 1 opens, all the current produced by the inverter will feed the grid. Figure 19 shows the grid’s phase-voltage and the current I L .

Grid Current 1 > Inverter Current 2 > 1) Ch1 2 Amp 5ms 2) Ch2 2
Grid Current
1
>
Inverter Current
2
>
1) Ch1 2 Amp
5ms
2) Ch2 2 Amp
5ms
1

Figure 18: Grid Current and the Inverter Current Feeding the Load (2A/div,

5ms/div)

Grid Voltage Inverter Current 1 > 2 > 1) Ch1 100 Volt 2) Ch2 5 Amp
Grid Voltage
Inverter Current
1
>
2
>
1) Ch1 100 Volt
2) Ch2 5 Amp
5 ms
5
ms

Figure 19: Grid Phase Voltage and the Current Feeding the Grid (100V/div, 5A/div, 5ms/div)

VII. Conclusion

This paper presents a high efficiency THIPWM three-phase inverter for grid connected system. Parallel-connected three- phase inverter fed from regulated DC voltage source. The improvement of parallel connected inverter over single connected inverter is clearly shown by calculating the efficiency of the inverter in both cases. The efficiency of parallel connected inverter found to be higher as compared to the single inverter. The system suitability for grid connection is verified and the parallel-connected inverter shows its capability of injecting current to the grid while maintaining synchronization with the grid.

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