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Resumen: Camilo Ernesto Montes Navarro Nstor Moreno Caro Rafael Constante Salome Microprocesadores 2 Docente: Ing.

: Luis Acosta Galvn. Resumen: Overview of the CPU Design. The CPU is simply a dedicated microprocessor that only executes software instructions. Figure 12.1 shows an overview of a general purpose microprocessor. The following discussion references this diagram.

In designing a CPU, we must first define its instruction set, and how the instructions are encoded and executed. Once you have decided on the instruction set, you can proceed to design a data path that can run all instruction sin the instruction set. Creating the data path for a general purpose microprocessor is exactly the same as the creation of the data path for a dedicated microprocessor. However, other operations and data records that should be included in the data path for the general purpose microprocessor. These operations and records data according to the manner in which the general purpose microprocessor retrieves instructions from memory and executes them. In particular, a program counter (PC). There is an instruction register (IR) for storing the instruction that is retrieved from memory. Every time an instruction is fetched from a

memory location pointed to by the PC, the PC must usually be increased to the next memory location of the next instruction. Alternatively, if the instruction is a branch instruction, the PC must be loaded with a new memory address instead. The cycles of a general purpose microprocessor, have three main steps (instruction cycle): 1) get an instruction, 2) decodes the instruction, and 3) executes the statement. The EC-1 General-Purpose Microprocessor To maintain the Microprocessor Design Manual manageable, we have to maintain the small number of variables. Since these variables determine the number of input signals and states of finite state machine, therefore, these factors should be kept to a minimum. However, the construction of this equipment is shown how a general purpose microprocessor is designed, and how the different components are put together. Instruction Set The instructions that the EC-1 general purpose microprocessor can execute, and the corresponding encodings are defined in Figure 12.2. The Instruction column shows the syntax and the access key to be used for instruction when writing a program in assembly language. Coding column shows the binary encoding for instruction set and operation column shows the instruction operation. As we can see in Figure 12.2, the instruction set of our small team has only five instructions. To encode five instructions, the operation code (opcode) require three bits giving us eight different combinations. As shown in the column on the coding, the first three bits are the opcode instruction given. Encoding the three, 000, 001, and 010 are not defined, and can be used as a no operation instruction (NOP). Since the width of each instruction is eight bits, the last five bits are used for all instructions except for the instruction JNZ .Normally, for a more comprehensive set of instructions, these extra bits are used as operand bits to specify which records or other resources to use. In our case, JNZ instruction only uses the last four bits, designated as AAAA, to specify an address in the memory to jump. The order of entry on a 8-bit value, and stores it in the accumulator (A). The accumulator is an 8-bit register to perform data operations. The one instruction copies the contents of the accumulator to the output port. For the EC - 1, the contents of the accumulator is always available at the output port, so this OUT A statement is not really necessary.

Notations: A = accumulator. PC = program counter. aaaa = four bits for specifying a memory address. = dont cares. Figure 12.2. Instruction set for the EC-1.

Control Unit

Of the five instructions, only the JNZ instruction requires an extra clock cycle to complete its operation. This is because if the condition is tested true, the PC is loaded with a new address value. This new address value is actually loaded into the PC at the beginning of

the next clock cycle. So if we have the FSM go to the FETCH state in the next clock cycle, then the IR will be loaded with the memory from the old address, and not the new address. From the START state, the control unit goes to the FETCH state unconditionally. In the FETCH state, the IR is loaded with the memory content in the location specified by the PC by asserting the IRload signal. Furthermore, the PC is incremented by 1, and the result is loaded back to the PC by asserting the PCload signal. The DECODE state tests the three most significant bits of the IR, IR7-5, and goes to the corresponding state as encoded by the three bit opcode for executing the instruction. In the five execute states corresponding to the five instructions, the appropriate control signals for the Data path are asserted to execute that instruction. The JNZ instruction asserts the JNZmux signal to route the four address bits from the IR to the PC. Whether the PC actually gets loaded with this new address depends on the condition of the Aneq0 status signal. Hence, the PCload control signal is asserted only if Aneq0 is a 1. By asserting the PCload signal conditionally depending on the status signal Aneq0, the state diagram will require one less state, thus making the finite-state machine smaller, and making it into a Mealy FSM. Otherwise, the FSM will need two states for the JNZ instruction: one state for asserting the PCload signal when Aneq0 is true, and one state for de-asserting the PCload signal when Aneq0 is false. The next-state / implementation table for the state diagram, and the three excitation equations as derived from the implementation table are shown in Figure 12.4 (b) and (c) respectively. With eight states, three D flip-flops are used for the implementation of the control unit circuit. Notice that the derivation of the excitation equations is fairly straight forward since most of the entries in the table contain 0s. Only the decode state row contains different values. The output equations shown in Figure 12.4 (e) are derived directly from the output table in (d). Finally, we can derive the circuit for the control unit based on the excitation equations and the output equations. The complete control unit circuit for the EC-1 general-purpose microprocessor is shown in Figure 12.4