Vectored Interrupt Controller

2009-10

CHAPTER 1

INTRODUCTION
An AMBA based microcontroller typically consists of a high performance system bac bone bus! able to sustain the e"ternal memory band#idth! on #hich the C$% on-chip memory and other direct memory access &'MA( de)ices reside* +his bus pro)ides a high band#idth interface bet#een the elements that are in)ol)ed in the ma,ority of transfers also located on the high performance bus is a bridge to the lo#er band#idth A$B! #here most of the peripheral de)ices in the system are located )ectored interrupt controller is one of the high performance system bus sla)e* +he figure 1*1 sho#s an e"ample of AMBA based system*

A-M $rocessor

.ighband#idth -AM %A-+ $I/

B I ' 0

.ighperformance Memory interface

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Vectored Interrupt Controller

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'MA Controller

Vectored interrupt Controller
9eypad

+IM:-

1igure 1*12A typical AMBA system

+he A.B sla)e main function is an interface unit that allo#s A.B* 3ogic to initiate a data transfer on the A.B* +he A.B specifies the type transaction to be e"ecuted on the sla)e through a user friendly interface* A.B is optimi4ed to interface #ith VIC to initiate data transfer on the A.B* /nce the VIC recei)ed the re5uest from A.B bus! e"ecutes the transaction on the A.B #ith the A.B protocol*VIC A.B sla)e interface #ill handle only one response state interrupts*

At this point #e propose a )ectored interrupt controller #ith #hich ha)ing the follo#ing specifications  %ses the AMBA A.B protocol*  %p to 62 interrupt source*  .igh le)el sensiti)e! interrupt source type*  7upport for 62 )ectored interrupts*  1i"ed interrupt priority le)el*  1i"ed I-8 and 1I8 generation* DEPT OF E&C, SJCIT 2

Vectored Interrupt Controller
 7oft#are interrupts generation*  Interrupt enable*  -a# interrupt status*  Interrupt source get ac no#ledgment*  Memory space offset address start #ith 00*

2009-10

VIC can pro)ide an interrupt controller peripheral for AMBA based 7/Cs*VIC captures interrupt re5uests from 62 interrupt inputs* :ach interrupt input independently configures for le)el sensiti)e! interrupt re5uest and for acti)e high interrupt re5uests* VIC supports for fi"ed priority scheduling method to handle the interrupt re5uests* VIC support for ; 1I8 and 2< I-8 re5uests* VIC ac no#ledges the interrupt re5uests*

CHAPTER 2

BLOCK DIAGRAM OF VECTORED INTERRUPT CONTROLLER (VIC)
+he )ectored interrupt controller is mainly di)ided in to three bloc s namely 1* $eripheral interface 2* C$% interface 6* A.B sla)e interface +he Bloc diagram of )ectored interrupt controller is sho#n in figure 2*1

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1 Periphera I!"er#a$e +he $eripheral interface is composed of only one functional unit called Interrupt re5uest logic 2. SJCIT 4 .Vectored Interrupt Controller 2009-10 1igure 2*12Bloc 'iagram of Vectored Interrupt Controller 2.1 I!"err%p" Re&%e'" L()i$ +he interrupt re5uest logic recei)es the interrupt re5uests from the peripheral and combines them #ith the soft#are interrupt re5uests* It then ma es out the interrupt re5uests that are not enabled and steering logic is used to split the interrupt re5uest into fast interrupt re5uest and general interrupt re5uest t#o separate ac no#ledgements are send bac for fast interrupt re5uest* 2*2 CPU I!"er#a$e DEPT OF E&C.1.

ere it #as fi"ed priority logic for upper 2< bits of Intr=src and generates the nir5 signal #hich is acti)e lo# and selects the )ector address of the respecti)e peripheral from )ectored table to the C$%* 2.a. bits of Intr=src and generates the nfi5 signals #hich is acti)e lo# and selects the )ector address of the respecti)e peripheral from )ectored table to the C$%* 2.e An A. AHB .Vectored Interrupt Controller 2009-10 +he C$% interface consists of t#o sub bloc s namely 1I8 re5uest handling and I-8 re5uest handling* 2. SJCIT 5 .7:3 select signal from the decoder to determine #hen it should respond to a bus transfer* All other signals re5uired for the transfer! such as the address and control information! #ill be generated by the bus master* 2.2../.2.ere #e use fi"ed priority logic for lo#er .2 IR* re&%e'" ha!+ i!) .1 I!"err%p" Re&%e'" L()i$ DEPT OF E&C./ Periphera I!"er#a$e 2.B bus sla)e responds to transfers initiated by bus masters #ithin the system* +he sla)e uses a .1 FI* re&%e'" ha!+ i!) .

Vectored Interrupt Controller 2009-10 1igure 2*22 Interrupt re5uest logic +he interrupt re5uest logic recei)er the interrupt re5uest from the peripheral and combines them #ith the soft#are interrupt re5uests to either I-8 status or 1I8 status  -(#"0I!" &7oft#are Interrupt -egister (2 +he read and #rite soft#are register! #ith address offset 0"0<0! generates soft#are interrupt* 7oft I>+ is 62 bits register! setting a bit generation a soft#are interrupt mas ing* A high bit sets the corresponding bit in the VIC7/1+I>+ register a lo# bit has no effect  E!a1 e0 I!"&Interrupt :nable -egister(2 +he read #rite interrupt enable register! #ith address effect of 0"0<. SJCIT 6 .! enable the interrupt re5uest id mas ing lines by mas ing the interrupt sources for the I-8 interrupt Interrupt enable register is a 62 bits register #hich enable the interrupt re5uest lines setting a bit interrupt enabled! :nable interrupt re5uest to processor setting a bit 0 DEPT OF E&C.

Vectored Interrupt Controller

2009-10

interrupts are disabled! on reset all interrupts are disabled A high bit sets the corresponding bits in interrupt enable register! a lo# bit has no effect*  I!"0-"a"%' &Interrupt 7tatus -egister(2 It has an address offset of 0"0<<! pro)ides the status of the source interrupt! and soft#are interrupt to the interrupt controller* Int =7tatus is 62 bit register! sho#s the status of the interrupts before mas ing by the enable registers *A high bit indicates that the appropriate interrupt re5uest is acti)e before mas ing* Interrupt re5uest logic recei)es 62 Intr=src lines from C$% peripherals and

combines #ith the soft#are interrupt #hich are #ritten by C$% on 7oft=Int register and enable the user selected interrupts by gated enabling and separate the 62 re5uest lines into ; fast interrupt re5uest and 2< general interrupt re5uest and also encode the filtered output generates t#o separate re5uest id for 1I8?s and I-8?s*

2.2 CPU I!"er#a$e
2.2.1 FI* re&%e'" ha!+ i!)
+he 1I8 re5uest handling sho#n in figure 2*6 asserts the nfi5 signal* i*e* if 1I8=status is non4ero! set the nfi5 as lo#* It selects the )ectored address of the corresponding fast interrupt re5uest* 7end it to C$% through A.B sla)e interface* It #ill select the )ectored address from the )ectored address table! )ectored address table is the memory configuration space! #hich contain the subroutine of the each interrupt re5uest* +he )ectored addresses in the )ectored table are programmable* 1I8=status acts as a select line for )ectored address selection* nfi5 is acti)e lo# signal for C$%*

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Vectored Interrupt Controller

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1igure 2*621I8 re5uest handling

2.2.2 IR* Re&%e'" Ha!+ i!)
+he I-8 re5uest handling sho#n in figure 2*; Asserts the nir5 signal* i*e*! if ir5=status is non4ero! set the nfi5 as lo# and selects the )ectored address of the corresponding interrupt re5uest* 7end it to C$% through A.B sla)e interface* It #ill select the )ectored address from the )ectored address table! )ectored address table is the memory configuration space! #hich contain the subroutine of the each interrupt re5uest* +he )ectored addresses in the )ectored table are programmable* I-8=status acts as a select line for )ectored address selection* nir5 is acti)e lo# signal for C$%*

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Vectored Interrupt Controller

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1igure 2*;2I-8 re5uest handling

2.3 AHB - a.e I!"er#a$e
+he A.B sla)e sho#n in figure 2*@ maps the memory configaration space #ith the interrupt controller and perform the data transaction as A.B asserts its signal* In this bloc asserts .ready=out as high and .resp as /9AA! because #e designed Interrupt controller as a single sla)e*

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e -i)!a ' Na5e .a.4.I0.B sla)e interface 2.1 AHB .4 -i)!a De"ai ' 2. .C39* . SJCIT Input -eset controller 10 +he bus reset signal is acti)e .C39 T6pe Input -(%r$e Cloc source De'$rip"i(! +his cloc times all bus transfers* All signal timings are related to the rising edge of .Vectored Interrupt Controller 2009-10 1igure 2*@ A.-:7:+ DEPT OF E&C.

! indicates that a transfer is complete* Can be dri)en 3/B to e"tend a transfer* .I0.! indicates that a transfer is complete* Can be dri)en 3/B to e"tend a transfer* .I0.-:A'A=/%+ /utput 7la)e +ransfer done signal! generated by the VIC* Bhen .-:A'A=I> Input :"ternal sla)e +ransfer done signal! generated by an alternate sla)e* Bhen .! indicates that DEPT OF E&C.Vectored Interrupt Controller 2009-10 and is used to reset the system and the bus* .-:7$&120( /utput 7la)e +ransfer done signal! generated by the VIC* Bhen .7:3 Input 'ecoder :ach A. this signal indicates a #rite transfer and #hen 3/B a read transfer* .I0.+-A>7&120( Input Master Indicates the type of the current transfer! #hich can be >/>7:8%:>+IA3! 7:8%:>+IA3! I'3: or B%7A* .B sla)e has its o#n sla)e select signal and this signal indicates that the current transfer is intended for the selected sla)e* +his signal is simply a combinatorial decode of the address bus* .A''-&1122( Input Master 7ystems address bus* .B-I+: Input Master Bhen . SJCIT 11 .I0.

20( /utput Interrupt Controller Address bus! returns the address to I-8 peripherals at the time of ac no#ledgment* AC9=1 /utput Interrupt Controller Bhen .! Indicates the 1I8 interrupt peripherals* ac no#ledgment to AC9=I /utput Interrupt Controller Bhen .I0.4. SJCIT 12 .-'A+A&6120( /utput 7la)e -ead data bus! used to transfer data from bus sla)es to bus master during read operations +able 2*12 A.I0.20( /utput Interrupt Controller Address bus! returns the address to 1I8 peripherals at the time of ac no#ledgment* -87+=I'=I &.I0.B 7la)e 7ignals 2.Vectored Interrupt Controller 2009-10 a transfer is complete* Can be dri)en 3/B to e"tend a transfer* .!indicates interrupt the I-8 to ac no#ledgment DEPT OF E&C.2 Periphera I!"er#a$e -i)!a ' Na5e I>+-=7-C C61 interrupt linesD T6pe Input -(%r$e $eripheral De'$rip"i(! +his is a one bit signal from each peripheral* +he signal is acti)e . #hich indicates there is a interrupt from respecti)e peripheral* -87+=I'=1 &.

20( I-8=status &2<20( >1I8 >I-8 V:C+=A''-&6120( T6pe Input Input /utput /utput /utput -(%r$e $eripheral Interface $eripheral Interface Interrupt Controller Interrupt Controller Interrupt Controller De'$rip"i(! Indicates the I-8 signals status Indicates the I-8 signals status 1I8 re5uest to processor I-8 re5uest to processor Address bus !contains )ector address of interrupt to processor +able 2*67C$% Interface 7ignals CHAPTER ..Vectored Interrupt Controller 1I8=status &. CPU I!"er#a$e -i)!a ' Na5e 1I8=status &. AMBA -PECIFICATION /n-chip communication standard for designing high performance embedded microcontroller* DEPT OF E&C.20( I-8=status &2<20( /utput /utput $eripheral Interface $eripheral Interface 2009-10 peripherals* Indicates the 1I8 signals status Indicates the I-8 signals status +able 2*2 2$eripheral Interface 7ignals 2. SJCIT 13 ./.

SJCIT 14 .B(  +he ad)anced system bus &A7B(  +he ad)anced peripheral bus &A$B( 2009-10 A test methodology is included #ith the AMBA specification #hich pro)ides an infrastructure for modular macro cell test and diagnostic access* +he AMBA specification has been deri)ed to satisfy the re5uirements such as  +o facilitate the right first home de)elopments of embedded microcontroller product #ith one or more C$% or signal processors*  +o be the only independent and ensure that highly reusable peripheral and system macro cells can be migrated across a di)erse range of IC processes and be appropriate for full-custom! standard cell and get array technologies  +o encourage modular system design to impro)e processor independence! pro)iding a de)elopment road map for ad)anced cached C$% cores and the de)elopment of peripheral libraries  +o minimi4e the silicon infrastructure re5uired to support efficient on-chip and off-chip communication for both operation and manufacturing test An AMBA based microcontroller typically consists of high performance system bac bone bus! able to sustain the e"ternal memory based #idth! on #hich the C$% on-chip memory and other direct memory access C'MAD de)ices reside* +his bus pro)ides a high band#idth interface bet#een the elements that are in)ol)ed in the ma.Vectored Interrupt Controller +hree distinct buses are defined #ithin the AMBA specifications  +he ad)anced high performance bus &A.ority of transfers* Also located on the lo#er band#idth A$B! #here most of the peripheral de)ices in the systems are located* DEPT OF E&C.

igh performance  $ipelined operation  Multiple bus master  Burst transfers  7plit transaction An AMBA A.B is a ne# generation of AMBA bus #hich is intended to address the re5uirements of high-performance synthesi4able designs* It is a high-performance system bus that supports multiple bus masters and pro)ides high-band#idth operation* AMBA A.B design may contain one or more bus masters! typically a system #ould contain at least the processor and test interface* .B implements the features re5uired for high-performance! high cloc fre5uency systems including  .1 AMBA AHB A. SJCIT 15 ..o#e)er! it #ould also be common for a 'irect Memory Access C'MAD or 'igital 7ignal $rocessor C'7$D to be included as bus masters* DEPT OF E&C.Vectored Interrupt Controller 2009-10 1igure 6*12AMBA Based 7/C .

igh performance  $ipelined operation  Multiple bus master A typical AMBA A7B system may contain one or more bus mastersC 1or e"ample! at least the processor and test interfaceD* .Vectored Interrupt Controller 2009-10 . AMBA APB +he AMBA A$B appears as a local secondary bus that is encapsulated as a single A.B or A7B sla)e de)ice* A$B pro)ides a lo#-po#er e"tension to the system bus #hich builds on A..B or A7B signals directly* +he features of A$B are  3o# po#er*  3atched address and control  7imply interface  7uitable for many peripherals An AMBA A$B implementation typically contains a single A$B bridge #hich is re5uired to con)ert A.o#e)er! it #ould also be common for a 'irect Memory Access C'MAD or 'igital 7ignal $rocessor C'7$D to be included as bus masters* +he e"ternal memory interface! A$B bridge and any internal memory are the most common A7B sla)es* Any other peripheral in the system could also be included as an A7B sla)e* . SJCIT 16 .o#e)er! lo#-band#idth peripherals typically reside on the A$B* ..B or A7B transfers into a suitable format for the sla)e de)ices on the DEPT OF E&C.2 AMBA A-B A7B is the first generation of AMBA system bus* A7B sits abo)e the current A$B and implements the features re5uired for high-performance systems including  ..

/ The E8"er!a Me5(r6 I!"er#a$e 7pecific and may only here a narro# data path that may also support address access mode #hich allo#s the internal AMBA A.Vectored Interrupt Controller 2009-10 A$B* +he bridge pro)ides latching of all address! data and control signals! as #ell as pro)iding a second le)el of decoding to generate sla)e select signals for the A$B peripherals* AMBA A$B pro)ides the basic peripheral macro cell communication infrastructure* As a secondary bus from the higher band #idth pipelined main system bus such peripherals typically  ..B addressing supports #ider data transfer including F.ect! #hich may ta e one or more bus cycles* +he bus transfer is terminated by a completion response from the addressed sla)e* +he transfer si4es supported by AMBA A7B include byte C<-bitD! half #ord C1F.bitD and #ord C62-bitD AMBA A.B! A7B E A$B modules to be tested in isolation #ith system independent test sets*  B%' $6$ e2 A bus cycle is a basic unit of one bus cloc period and for the purpose of AMBA A.bit and 12<-bit transfers An AMBA A$B bus transfer is a read or #rite operation of a data ob.a)e interfaces #hich are memory mapped register*  .B or A$B protocol description is defined from rising edge transactions* Bus signal timing is referenced to the bus cycle cloc *  B%' "ra!'#er2 An AMBA A7B or A. SJCIT 17 .B bus transfer is a read #rite operation of a data ob.a)e no high band#idth interfaces*  Are accessed under programmed control .ect #hich al#ays re5uires t#o bus cycles  B%r'" (pera"i(!2 burst operation is defined as one or more data transactions initiated by a bus master! #hich ha)e a consistent #idth of transaction setup per transaction is determined by the #idth of transfer* >o burst operation is supported on the A$B* DEPT OF E&C.

0+! A-M9.Vectored Interrupt Controller 2009-10 CHAPTER / ARM INTERRUPT HANDLING Interrupts #hich are inds of e"ceptions are essential* It enables the system to deal #ith e"ternal e)ents by recei)ing interrupt signals telling the C$% that there is something to be done-instead of the alternati)e #ay of doing the same operation by the pooling mechanism #hich #astes the C$% time in looping fore)er chec ing some flags to no# that the e)ent occurred* App ie' "(7 A-M1020G22:! A-M102F:H-7! A-M116F! A-MI20+! A-MI:H-7! A-MI+'MI! A-MI+'MI-7! A-M920G922+! A-M92F:H-7! A-M9. SJCIT 18 .F:-7! A-M9FF:-7! A-M9+'MI %pon entry to the I-8 e"ception handler! the JIJ bit is set and further interrupts CI-8D cannot be recogni4ed by the core until the handler e"plicitly re-enables further interrupts by #riting to the C$7-* %pon entry to the 1I8 e"ception handler! both the JIJ bit and the J1J bit is set and further interrupts! fast or normal! cannot be recogni4ed by the core until the handler e"plicitly re-enables further interrupts by #riting to the C$7-* +he I-8G1I8 handler should not re-enable interrupts until it has ac no#ledged the interrupt to #hate)er is dri)ing the nI-8Gn1I8 input! other#ise the core #ill immediately reenter the interrupt handler* 'ue to a pipeline ha4ard on later A-M cores! #e should al#ays ensure that there is plenty of time bet#een the ac no#ledgement and the re-enabling of the interrupts* Consider the follo#ing piece of A-M code DEPT OF E&C.

instruction* +he ne"t instruction #ill ha)e already been decoded and enters the e"ecution stage of the instruction pipeline .r1! &r0( K ac * interrupt by #riting to the interrupt controller M7.ust as the flags are being changed* DEPT OF E&C.instruction* If an interrupt occurs as it is being enabled! the instruction follo#ing the M7.ence if the interrupt controller ta es longer than one A-M C39 cycle to clear the interrupt signals into the core! it #ill re-enter the interrupt e"ception handler* 1or this reason! A-M recommends that programmers ac no#ledge interrupts at the )ery beginning of the e"ception handler* +he e"ception handler should not re-enable interrupts until the )ery end of the e"ception handler unless nested interrupts are being used* If nested interrupts are being used! programmers should ensure that there is some padding bet#een the ac no#ledge and re-enable of interrupts to allo# time for the interrupt signals to change Interrupts are enabled by clearing the I Cfor I-8D or 1 Cfor 1I8D flags in the C$7#ith an M7.Vectored Interrupt Controller 7+.instruction #ill still be e"ecuted* +he reason is that the ne# flags are only a)ailable to the control logic at the end of the e"ecution stage of the M7.cpsr=c! r2K re-enable interrupt* 2009-10 /n the A-M9+'MI and later cores! the 7+. SJCIT 19 .instruction* .#rite to e"ternal memory may occur as little as one C39 cycle before the interrupts are re-enabled by the M7.

1.e i!"er#a$e 2.a.1 -"a"e +ia)ra5 1igure @*127tate transition diagram of A.B 7la)e interface* DEPT OF E&C. SJCIT 20 .Vectored Interrupt Controller 2009-10 CHAPTER 2 DE-IGN OF INTERRUPT CONTROLLER 2.1 AHB .

SJCIT 21 .trans! .B-I+: and register the current address*  RD0DATA7 -eads the current 'A+A from registered address as per the registered .addr and .Vectored Interrupt Controller 2009-10 +here are 6 states I'3:! B-='A+A and -'='A+A* A.B sla)e interface* .#rite indicates -ead or Brite transaction on A.sel! .B-I+: and register the current address* DEPT OF E&C.B bus*  IDLE7 'A+A read from registered address*  9R0DATA7 Brites the current 'A+A to the registered address as per registered .ready=in together 8ualifies the data transaction* .B bus asserts its signals to set the state of the A.

readyL1 E .#riteL1 . SJCIT 22 .selL0 E .B signals #hile transmitting from one state to other state* DEPT OF E&C.selL0 E .selL0 E .trans&1(L0 E.readyL1 E .readyL1 E .B 7la)e 7tate +ransition +able +able @*1 sho#s the state of all A.#riteL0 .trans&1(L0 .B='ata .-='ata Idle .Vectored Interrupt Controller 2009-10 C%rre!" '"a"e Idle Ne8" '"a"e .2 AHB .a.#riteL1 .-='ata .-='ata .B='ata .-='ata Idle .#riteL0 C(!+i"i(! Idle .readyL0 M .selL0 M .trans&1(L1 E.selL1 E .B='ata .selL0 M .trans&1(L0 E.#riteL1 .trans&1(L1 E.readyL1 E .1.readyL1 E .readyL1 E .e -"a"e Tra!'i"i(! Ta1 e +able @*12 A.#riteL1 2.trans&1(L1 E.trans&1(L0 .trans&1(L0 .B='ata .selL0 E .selL0 M .trans&1(L1 E.readyL0 M .readyL0 M .selL1 E .

1.B 7la)e timing diagram A.e Ti5i!) Dia)ra5 1igure @*22 A.B sla)e timing diagram in figure @*2 sho#s the timing analysis of A.a. SJCIT 23 .B signal transaction* 7etting .selL1! . AHB .transL10 or 11* DEPT OF E&C.Vectored Interrupt Controller 2009-10 2..

1 I!"err%p" C(!"r( er -"a"e Ma$hi!e 1igure @*62Interrupt controller state machine /nly t#o state -:7/3V: and 1/-BA-'* Interrupt controller enters the -:7/3V: state only #hen .2 I!"err%p" C(!"r( er 2. SJCIT 24 .reset is high C1D* RE-OLVE7 Interrupt re5uest from the peripherals are combined #ith soft#are interrupts! gated enable the interrupt re5uest as programmer #ish* %sing steering logic splits the interrupt re5uests into 1I8=status and I-8=status and assert the Ac =1 and Ac =I* FOR9ARD7 Assert the nfi5 and nir5 as per 1I8=status and I-8=status respecti)ely* DEPT OF E&C.Vectored Interrupt Controller 2009-10 2.2.

Vectored Interrupt Controller 2009-10 2.2.2 I!"err%p" C(!"r( er -"a"e Ta1 e PRESENT STATE CONDITION NE:T -TATE RESOLVE Ac =1L0 EAc =IL0 Ac =1L1 EAc =IL1 RESOLVE 1/-BA-' 1/-B/-' 1/-BA-' Int=Ac =1 L0 EInt=Ac =IL0 Int=Ac =1 L1 EInt=Ac =IL1 RESOLVE +able @*22Interrupt Controller 7tate +able 2. I!"err%p" C(!"r( er Ti5i!) +ia)ra5 DEPT OF E&C.2. . SJCIT 25 .

2 Interrupt controller timing diagram 2. -%55ar6 O# Re)i'"er' DEPT OF E&C..Vectored Interrupt Controller 2009-10 1igure @*. SJCIT 26 .

address for Int=src &I( Contains I7.address for Int=src &0( Contains I7. 0< 0C 10 1.( Vect=addr 1@ 6C -GB Contains I7.address for Int=src &.address for Int=src . 27 -GB Contains I7.address for Int=src &10( Vect=addr 11 2C -GB Contains I7.address for Int=src &F( Contains I7.( Contains I7.address for Int=src &16( Vect=addr 1.address for Int=src &6( Contains I7.address for Int=src &1F( Vect=addr 1I DEPT OF E&C. Vect=addr @ Vect=addr F Vect=addr I Vect=addr < Vect=addr 9 Vect=addr 10 00 0.address for Int=src &9( Contains I7. 1< 1C 20 2.address for Int=src &1. 2< -GB -GB -GB -GB -GB -GB -GB -GB -GB -GB -GB Contains I7..Vectored Interrupt Controller 2009-10 -:0I7+:- A''-:77 /117:+ +A$: ':7C-I$+I/> Vect=addr 0 Vect=addr 1 Vect=addr 2 Vect=addr 6 Vect=addr .address for Int=src &1@( Vect=addr 1F .address for Int=src &1( Contains I7. 6< -GB Contains I7. -GB Contains I7.address for Int=src &2( Contains I7. SJCIT .0 -GB Contains I7.address for Int=src &12( Vect=addr 16 6.address for Int=src &<( Contains I7.address for Int=src &@( Contains I7.address for Int=src &11( Vect=addr 12 60 -GB Contains I7.

address for Int=src &2<( Vect=addr 29 I.C -GB Contains I7. F0 -GB Contains I7.address for Int=src &29( Vect=addr 60 I< -GB Contains I7.address for Int=src &61( DEPT OF E&C.address for Int=src &2.address for Int=src &60( Vect=addr 61 IC -GB Contains I7.address for Int=src &21( Vect=addr 22 @< -GB Contains I7.( Vect=addr 2@ F.address for Int=src &22( Vect=addr 26 @C -GB Contains I7. -GB Contains I7. SJCIT 28 . -GB Contains I7.address for Int=src &1<( Vect=addr 19 .address for Int=src &2I( Vect=addr 2< I0 -GB Contains I7.address for Int=src &20( Vect=addr 21 @.< -GB 2009-10 Contains I7. -GB Contains I7.address for Int=src &2F( Vect=addr 2I FC -GB Contains I7.address for Int=src &2@( Vect=addr 2F F< -GB Contains I7.Vectored Interrupt Controller &1I( Vect=addr 1< .address for Int=src &19( Vect=addr 20 @0 -GB Contains I7.address for Int=src &26( Vect=addr 2.

-GB :nables the interrupt re5uest lines! #hich allo# the interrupts to reach the processor Int=7tatus << -/ 7ho#s the status of the ra# interrupt source inputs after mas ing by the enable register Int=ac <C -GB Ac no#ledgement from C$% to interrupt controller !as C$% has recei)ed the re5uest Vect=addr 1I8 90 -/ Contains the )alue of the respecti)e )ector address of nfi5 #hen nfi5 is high Vect=addr I-8 9. SJCIT 29 .I0. -/ Contains the )alue of the respecti)e )ector address of nir5 #hen nir5 is high +able @*62-egister 7pace of registers DEPT OF E&C.Vectored Interrupt Controller 7ft=Int <0 -GB 2009-10 7etting a bit . generates a soft#are interrupt for the selected source before interrupt mas ing* :nable=Int <.

SJCIT 30 .Vectored Interrupt Controller 2009-10 CHAPTER 3 CODING 3.20( r5stidf!r5stidiK reg ac f!ac i!nfi5!nir5K DEPT OF E&C.1 Veri () C(+e F(r I!"err%p" C(!"r( er module int=cntrChcl !hreset! int=src! nfi5!nir5!ac f!ac i! r5stidf!r5stidiDK GGprimary input input hcl !hresetK input &6120( int=srcK GGprimary outputs output ac f!ac i!nfi5!nir5K output &.

20( r5stidi=cntL00100K DEPT OF E&C.Vectored Interrupt Controller reg &.20( r5stidf=cntL00000K reg &. SJCIT 31 .20( r5stidf!r5stidiK GGreg &6120( )ect=addrf!)ect=addriK GGstates parameter -:7/3V:L1Jb0K parameter 1/-BA-'L1Jb1K 2009-10 GGe"ternal register reg &6120( soft=intK reg &6120( enbl=intK reg &6120( int=statusK reg &620( fi5=statusK reg &2I20( ir5=statusK reg int=ac =fK reg int=ac =iK reg &6120( )ectaddr &0261(K GGinternal register reg stateK reg &.

!iK integer fi5addrK integer ir5addrK 2009-10 GG combinatorial logic assign fltr=int=src=#irLCint=srcMsoft=intDEenbl=intK assign nfi5=#irLNCMfi5=statusDK assign nir5=#irLNCMir5=statusDK al#aysO Cposedge hcl or negedge hresetD begin ifCNhresetD begin statePL-:7/3V:K ac fPL1Jb0K ac iPL1Jb0K nfi5PL1Jb1K DEPT OF E&C.address assingment integer . SJCIT 32 .Vectored Interrupt Controller GGcombinatorial logic in)ol)ed #ire &6120( fltr=int=src=#irK #ire nfi5=#irK #ire nir5=#irK GG for forloop and for I7.

(DK nfi5PL1Jb1K nir5PL1Jb1K int=ac =iPL1Jb0K int=ac =fPL1Jb0K statePLCac fMMac iDQ1/-BA-'2-:7/3V:K end 2009-10 1/-BA-'2 begin ac fPL1Jb0K ac iPL1Jb0K DEPT OF E&C.Vectored Interrupt Controller nir5PL1Jb1K end else GGstate logic begin caseCstateD -:7/3V:2 begin ac fPLCMfltr=int=src=#ir&620(DK ac iPLCMfltr=int=src=#ir&612. SJCIT 33 .

L . P .K disable fi5=id=loopK DEPT OF E&C.Vectored Interrupt Controller nfi5PLNCMfi5=statusDK nir5PLNCMir5=statusDK stateLCint=ac =i EE int=ac =fDQ-:7/3V:21/-BA-'K end endcase end end GGencoder for re5uest id genaration al#ays OCposedge hcl D begin ifCstateLL-:7/3V:D begin int=statusLfltr=int=src=#irK fi5=statusLfltr=int=src=#ir &620(K ir5=statusLfltr=int=src=#ir &612.(K for C. SJCIT 34 2009-10 .(D r5stidfL.L0K . R 1D begin 2 fi5=id=loop ifCfltr=int=src=#ir&.K .

Vectored Interrupt Controller end for Ci L . SJCIT 35 .K i P 62K i L i R 1D begin 2 ir5=id=loopK ifCfltr=int=src=#ir&i(D r5stidiLiK disable ir5=id=loopK end fi5addrLr5stidfKGGinteger con)ertion ir5addrLr5stidiKGGinteger con)ertion end end endmodule 2009-10 DEPT OF E&C.

A''-K input &6120( .+-A>7! .7:3!r5st=idf!r5st=idiDK input .+-A>7K input .a.-:A'AI>! . SJCIT 36 .-:7:+K input .B-I+:! .C39K input .e module ahb=sla)e C.2 Veri () C(+e AHB .-:A'AI>K input &1@20( .C39! .B-I+:K input &120( .7:3K DEPT OF E&C.-:7:+! .-'A+A! .-:7$! .A''-! .B'A+AK input .Vectored Interrupt Controller 2009-10 3.-:A'A/%+! .B'A+A! .

-'A+A=#ireK #ire &6120( A''-K GGInternal registers used reg &1@20( . SJCIT 37 .Vectored Interrupt Controller input &.B 7la)e interface reg &120(7tateK DEPT OF E&C.-:A'A/%+K output &120( .-'A+AK output .-:7$K 2009-10 GG -egistered outputs reg &6120( .addr-egK reg .#rite-egK reg &6120( Bdata-egK reg &6120( -'A+A-egK GGused in 7tate machine for A.-'A+AK GGInternal #ires used #ire ValidK #ire &6120(.20(r5st=idiK output &6120( .20(r5st=idfK input &.

+-A>7 transfer type signal encoding2 Tdefine +->=I'3: 2Jb00 Tdefine +->=B%7A 2Jb01 Tdefine +->=>/>7:8 2Jb10 Tdefine +->=7:8 2Jb11 GG .-:7$ transfer response signal encoding2 Tdefine -7$=/9AA 2Jb00 Tdefine -7$=:--/.2Jb01 Tdefine -7$=-:+-A 2Jb10 DEPT OF E&C. SJCIT 38 .! B/-'=7IS: L 62K reg &B/-'=7IS:-120( configure=space &02A''-=7IS:-1(K integer Addr=integerK integer iK GG .Vectored Interrupt Controller parameter I'3:L2Jb00K parameter B-='A+AL2Jb01K parameter -'='A+AL2Jb10K 2009-10 GG 'efinition of Configuration memory space parameter A''-=7IS: L F.

+-A>7 .an idle or busy transfer should be ignored* assign Valid L CC.addr-eg PL V1FV1Jb0WWK .B transfers only ta e place #hen a non-se5uential or se5uential GG transfer is sho#n on . SJCIT 39 .+-A>7 LL T+->=>/>7:8 MM .-:A'AI> LL 1Jb1 EE C.Vectored Interrupt Controller Tdefine -7$=7$3I+ 2Jb11 2009-10 GG-----------------------------------------------------------------------------GG Valid A.-:7:+DD begin .+-A>7 LL T+->=7:8DD Q 1Jb1 2 1Jb0DK al#ays O Cnegedge .7:3 LL 1Jb1 EE .-:7:+ or posedge .C39D begin if CCU.B 7tate logic DEPT OF E&C.#rite-eg PL 1Jb0K 7tate PL I'3:K end else GG A.

addr-eg PL .A''-K . SJCIT 40 .B-I+:K end ifCValid LL 1 EE .B-I+: LL 1D 7tate PL B-='A+AK end B-='A+A2 begin DEPT OF E&C.#rite-eg PL .-'A+A PL -'A+A-egK 7tate PL -'='A+AK end else ifCValid LL1 EE .B-I+: LL 0D begin .Vectored Interrupt Controller begin caseC7tateD 2009-10 I'3:2 begin if CValidD begin .

-'A+A PL -'A+A-egK .B-I+: LL 1D 7tate PL B-='A+AK else ifCValid LL 0D 7tate PL I'3:K end 2009-10 -'='A+A2 begin ifCValid LL 1D begin .#rite-eg PL .B-I+:K end ifCValid LL 1 EE .A''-K .B'A+AK .Vectored Interrupt Controller ifCValid LL 1D begin Bdata-eg PL .B-I+:K DEPT OF E&C.addr-eg PL .A''-K .addr-eg PL .#rite-eg PL .B-I+: LL 0D 7tate PL -'='A+AK else ifCValid LL1 EE . SJCIT 41 .

-'A+A=#ire L configure=space&Addr=integer(K GG---------------------------------------------------------------------GGC/>1I0%-A+I/> M:M/-A 7$AC: MA$$I>0 GG---------------------------------------------------------------------- DEPT OF E&C. SJCIT 42 .-:7$ L T-7$=/9AAK GG-:A' 'A+A assignment assign .Vectored Interrupt Controller end ifCValid LL 1 EE .-:A'A/%+ L 1K GG .readyout assignment assign .response assignment assign .B-I+: LL 1 7tate PL B-='A+AK else ifCValid LL 0D 7tate PL I'3:K end endcase end end 2009-10 GG .B-I+: LL 0D 7tate PL -'='A+AK else ifCValid LL1 EE .

assignment from .addr-egK GG Chip select signal generation assign C7 LCNXA''-&1@2<(DK 2009-10 GG Brite enable signal generation assign B-en L .L .A''assign A''. SJCIT 43 .#rite-eg E C7K al#aysO Cposedge .C39 or negedge .Vectored Interrupt Controller GG A''.-:7:+D begin if CN.-:7:+D begin for CiL0K iPLF6K i LiR1D configure=space&i(PL62Jd0K end else begin configure=space&6I( PL configure=space&r5st=idf(K configure=space&6<( PL configure=space&r5st=idi(K Addr=integer L A''-&I22(KGGCon)ersion of Actual F-bit adress for the register to integer ifCB-en LL 1D begin ifCAddr=integer LL 6I EE Addr=integer LL 6<D DEPT OF E&C.

RTL -$he5a"i$ (# I!"err%p" C(!"r( er DEPT OF E&C..Vectored Interrupt Controller begin end else configure=space&Addr=integer( PL Bdata-egK end else -'A+A-eg PL. SJCIT 44 .-'A+A=#ireK end end endmodule 2009-10 3.

/ RTL -$he5a"i$ (# AHB .a.e I!"er#a$e DEPT OF E&C.Vectored Interrupt Controller 2009-10 3. SJCIT 45 .

Vectored Interrupt Controller 2009-10 CHAPTER 4 DEPT OF E&C. SJCIT 46 .

SJCIT 47 .Vectored Interrupt Controller 2009-10 -IMULATION RE-ULT4.1 I!"err%p" C(!"r( er 1igure I*12Interrupt handling from I-8 peripheral 1igure I*1 sho#s ho# )ectored Interrupt Controller handles an ir5 re5uest* re5uestidi! ac i and nir5 are are asserted as per the highest priority interrupt re5uest* re5uestidi is the uni5ue id peripheral #hose re5uest going to get the ser)ice from C$%* nir5 is acti)e lo# signal #hich interrupt?s the C$%* DEPT OF E&C.

Vectored Interrupt Controller 2009-10 1igure I*22Interrupt handling from 1I8 peripheral 1igure I*2 sho#s ho# )ectored Interrupt Controller handles an fi5 re5uest* re5uestifi! ac f and nfi5 are asserted as per the highest priority interrupt re5uest* re5uestidf is the uni5ue id peripheral #hose re5uest going get the ser)ice from C$%* nfi5 is acti)e lo# signal #hich interrupt?s the C$%* DEPT OF E&C. SJCIT 48 .

SJCIT 49 .Vectored Interrupt Controller 2009-10 1igure I*62Interrupt handling from I-8 and 1I8 peripheral 1igure I*6 sho#s ho# )ectored Interrupt Controller handles an ir5 re5uest and fi5 * re5uestidi! ac i! nir5! re5uestidf! ac f and nfi5 are got asserted as per the highest priority interrupt re5uest* re5uestidi and re5uestidf is the uni5ue id peripheral #hose re5uest going get the ser)ice from C$%* nir5 and nfi5 is acti)e lo# signal #hich interrupt?s the C$%* DEPT OF E&C.

B from Vectored Interrupt Controller* In order to read the 'ata .2 AHB .2A.-data bus* DEPT OF E&C.B 'ata -ead /peration 1igure I*.B signals are asserted to perform 'ata read through the A.Vectored Interrupt Controller 2009-10 4. sho#s ho# A.e 1igure I*.a.#rite must be lo#* 'ata read from the address #hich is specified on the .addr bus through . SJCIT 50 .

SJCIT 51 .Bdata bus* DEPT OF E&C.B to Vectored Interrupt Controller* In order to #rite the 'ata .B signals got asserted to perform 'ata #rite through the A.addr bus through .#rite must be high* 'ata #rite to the address #hich is specified on the .Vectored Interrupt Controller 2009-10 1igure I*@2A.B 'ata Brite /peration 1igure I*@ sho#s ho# A.

addr bus through .Vectored Interrupt Controller 2009-10 1igure I*F2 A.B signals got asserted to perform 'ata read through the A.B from Vectored Interrupt Controller* In order to read the 'ata . SJCIT 52 .#rite must be lo#* 'ata read from the address #hich is specified on the .-data bus* DEPT OF E&C.B 'ata -ead /peration 1igure I*F sho#s ho# A.

0.ecti)e of designing YA Vectored interrupt controller as AMBA A.* Memory space #ith the address <<h! <Ch! 90h are read only registers stores the status of interrupt controller! )ectored address of 1I8 and I-8 re5uest respecti)ely* DEPT OF E&C. to .ecti)e* Vectored interrupt controller #hat #e designed #ill send bac ac no#ledgement to the peripherals to guarantees the acceptance of interrupt re5uest* :ach peripheral #hich are interfaced #ith this )ectored interrupt controller is pro)ided #ith a uni5ue peripheral I' C-5st=idD* Vectored interrupt can ser)e t#o interrupt re5uest at a time! one 1I8 re5uest and one I-8 re5uest and it #ill gi)e t#o separate ac no#ledgements for both 1I8 and I-8 re5uests* 'ue to the parallel processing of 1I8 and I-8 re5uests the VIC has a lo# latency has a faster e"ecution speed* Be defined a memory space for registers and to store interrupt ser)ice routines! #ho?s offset address start from 00. CONCLU-ION Be started our design #ith the ob. SJCIT 53 .B mapped for fastest interrupt response! 3e)el 7ensiti)e interrupt input! soft#are interrupt generation! fi"ed hard#are priority! interrupt enabling and fi"ed 1I8 and I-8 generation* >o# #e finished our design #hich meets our ob.Vectored Interrupt Controller 2009-10 CHAPTER .B sla)eZ* 7upport for 62 interrupt source! A.

SJCIT 54 .1 FUTURE ENHANCEMENT  'aisy chain supporting2 +he daisy-chained VIC are responsible for bloc ing lo#er-le)el or e5ual-le)el interrupts* It operates in t#o modes VIC0 and VIC1* +o enable higher priority interrupts from the daisy-chained VIC1 to be ac no#ledged #hile ser)icing a lo#er le)el interrupt* Bhen implementing the daisy chain! #e ha)e to ensure the total propagation delay for VICI-8AC9 across the all the VICs is #ithin one cloc cycle  >ested interrupt handling +o pre)ent the loss and delay of high-priority interrupts! the system uses nested interrupts* >ested interrupts allo# interrupt re5uests CI-8sD of a higher priority to preempt I-8s of a lo#er priority* >ested interrupts are allo#ed in con.Vectored Interrupt Controller 2009-10 ..unction #ith the -eal-+ime $riority 7ystem* I7-s of a higher priority might preempt I7-s of a lo#er priority*  Multi domains interrupt handling*  $rogrammable 1I8 and I-8 generation* DEPT OF E&C.

SJCIT 55 .'3 7ynthesis 1st :dition!199< * @* http2GGinfocenter*arm*com F* http2GG###*arm*com DEPT OF E&C.'3 $rimer 6rd :dition! 2006* .Vectored Interrupt Controller 2009-10 BIBILOGRAPH< 1* A-M Corporation! $rime cell Vectored interrupt controller $3192! reference manual!2002 2* A-M Corporation !AMBA specification 6*0! reference manual!200F 6* H* Bas er!A Verilog .* H* Bas er!A Verilog .

SJCIT 56 .Vectored Interrupt Controller 2009-10 APPENDI: DEPT OF E&C.

Vectored Interrupt Controller 2009-10 DEPT OF E&C. SJCIT 57 .

Vectored Interrupt Controller 2009-10 DEPT OF E&C. SJCIT 58 .

SJCIT 59 .Vectored Interrupt Controller 2009-10 DEPT OF E&C.

Vectored Interrupt Controller 2009-10 DEPT OF E&C. SJCIT 60 .

SJCIT 61 .Vectored Interrupt Controller 2009-10 DEPT OF E&C.

Vectored Interrupt Controller 2009-10 DEPT OF E&C. SJCIT 62 .

SJCIT 63 .Vectored Interrupt Controller 2009-10 DEPT OF E&C.

Vectored Interrupt Controller 2009-10 DEPT OF E&C. SJCIT 64 .

Vectored Interrupt Controller 2009-10 DEPT OF E&C. SJCIT 65 .

Vectored Interrupt Controller 2009-10 DEPT OF E&C. SJCIT 66 .

Vectored Interrupt Controller 2009-10 DEPT OF E&C. SJCIT 67 .

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