VEHICLE TRACKING AND ACCIDENT WARNING SYSTEM USING GPS AND ITS IMPLEMENTATION IN FPGA

A PROJECT REPORT Submitted by Reg. No. 30607106033 30607106044 30607106068 Student’s Name HUBERT VIJAY A KARTHIKEYAN N PRABHU K

in partial fulfillment for the award of the degree of BACHELOR OF ENGINEERING IN ELECTRONICS AND COMMUNICATION ENGINEERING JEPPIAAR ENGINEERING COLLEGE, CHENNAI
ANNA UNIVERSITY: CHENNAI-600 025. APRIL 2011

ANNA UNIVERSITY
CHENNAI-600 025

JEPPIAAR ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
JEPPIAAR NAGAR, RAJIV GANDHI SALAI, CHENNAI-600 119

BONAFIDE CERIFICATE
Certified that this project report “VEHICLE TRACKING AND ACCIDENT WARNING IN SYSTEM FPGA” is USING the GPS bonafide AND work ITS of

IMPLEMENTATION

__________________________________________________________________ who carried out the project work under my supervision.

PROJECT GUIDE

HEAD OF THE DEPARTMENT

Submitted for the examination held on ____________________

INTERNAL EXAMINER

EXTERNAL EXAMINER

CERTIFICATE OF EVALUATION

S. No.

Name of the student/s who have done the project

Title of the project VEHICLE

Name of the Supervisor with Designation

1 2 3

HUBERT VIJAY A KARTHIKEYAN N PRABHU K

TRACKING AND ACCIDENT WARNING SYSTEM MR.B.ARUN VIJAYA KUMAR,

USING GPS AND ITS ASST.PROFESSOR IMPLEMENTATION IN FPGA

The Reports of the project work submitted by the above students in partial fulfillment for the award of Bachelor of Engineering / Technology Degree in Electronics & Communication Engineering of Anna University, Chennai were evaluated and confirmed to be reports of the work by the above students and then evaluated.

INTERNAL EXAMINER

EXTERNAL EXAMINER

Chinnadurai.B.D. B. Hon’ble.. the Secretary Dr.Tech.Vivek. Ph. M.D. Dr. the Principal Dr. We take this opportunity to express our sincere gratitude to our external guide Mr.A. B. Ph. .Arun VijayaKumar. Ltd. B.Professor for giving valuable suggestions for making this project a grand success. M.. JEPPIAAR.. Asst..... Sushil Lal Das. Project Guide.Ed. M.A.Phil.B.Sc (Engg). I also thank the teaching and non teaching staff members of the department of Electronics and Communication Engineering for their constant support. Ph. M. Regeena. We would also like to express our deep sense of gratitude to the Head of the Department and also to our guide Mr.D. D. the Director Dr. Chennai for giving us the opportunity to do this project under their esteemed guidance.L. P. Vi Microsystems Pvt.ACKNOWLEDGEMENT We are very much indebted to the Chairman. Ph.

The GSM technology is used to send the position of the vehicle as a SMS to those numbers. This is received by a GSM modem in the device and processed by the Spartan processor and the processor sends command to a GPS module in the device. the owner sends a request through a SMS. The GPS module responds with coordinates position of the vehicle. ambulance etc. with this equipment we can keep track of the vehicle by periodically sending SMS and the position of the vehicle is sent by the GSM modem as a SMS to the user. the accelerometer sensor detects the change in position and sends a signal to the processor. So the ambulance arrives in time and the police can arrive in time to clear the traffic. To know the position of the vehicle. This position is sent to the user as a SMS to the user with date. people lose their lives due to unavailability of proper medical facilities at the right time. The processor analyses the signal and finds there is an accident. Most of the companies wants to keep track of their vehicles. When there is an accident. police etc. It immediately sends the position of the vehicle and also the information that there is an accident. ambulance. This project senses any accident in the vehicle and intimates pre-programmed numbers like the owner of the vehicle. police. time.V ABSTRACT In highly populated Countries like India. This reduces the time taken by ambulance to arrive and also traffic can be cleared easily. during accidents. to pre-programmed numbers such as the owner of the vehicle. . And also the position of the vehicle can be obtained by the owner of the vehicle or anyone with proper permission by sending an SMS to a number. latitude and longitude positions.

2 BLOCK DIAGRAM OF THE SYSTEM 3. ABSTRACT LIST OF TABLES LIST OF FIGURES LIST OF ABBREVIATIONS 1 2 INTRODUCTION LITERATURE REVIEW 2. ISSAM W.3. V x xi xii 1 2 2 2 3 4 3 SYSTEM SUPPLY ARCHITECTURE AND POWER 5 3.1 SYSTEM OVERVIEW 3.3. SYAMSUDIN. PRAMANA 2.1 Linear Power Supply 3. AND RACHED N.3 POWER SUPPLY CIRCUIT 3. YAQZAN.1 INTRODUCTION 2.VI TABLE OF CONTENTS CHAPTER NO.2 Multi output Power Supply 5 5 6 7 8 .4 CONCLUSION TITLE PAGE NO. DAMAJ. ZANTOUT 2.2 PERSPECTIVE OF HAPSARI .3 PERSPECTIVE OF ADNAN I.

4 MAJOR COMPONENTS OF A GPS RECEIVER 5.2 GSM SPECIFICATIONS 4.6 RECEIVER OUTPUT 5.3.8 RECEIVER FEATURES 5.9 HARDWARE CONNECTION 5.1GSM OVERVIEW 4.VII 3.2 GPS PRINCIPLE 5.1 GPS BASICS 5.3 GPS RECEIVER 5.4 AT COMMANDS 10 10 10 11 12 14 14 14 15 16 16 17 18 19 22 23 5 GPS (GLOBAL POSITIONING SYSTEM) 5.5 FUNCTION OF GPS 5.7 GPS DEVICE 5.3 GSM MODEM 4.3 Regulator 9 4 GLOBAL SYSTEM FOR MOBILE(GSM) 4.10 TYPES OF ERRORS 6 SPARTAN 3E BOARD 6.1 CONCEPT OF FIELD-PROGRAMMABLE GATE 24 24 .

2 FEATURES OF SPARTAN 3E BOARD 6.3 ARCHITECTURE OF SPARTAN 3E BOARD 27 28 7 ACCELEROMETER SENSOR 7.7.7.3 VHDL 8.2 General Description of PCF 8591 7.4 FUNCTIONAL BLOCK DIAGRAM 7.7.5 THEORY OF OPERATION 7.1 Features of I2C bus 7.4 DESIGN FLOW IN VHDL .6 APPLICATIONS OF ACCELEROMETER SENSOR 7.1 XILINX SOFTWARE 8.4 Control Byte 33 33 33 33 34 35 36 37 38 39 39 39 40 40 40 40 41 8 DESIGN OF SYSTEM SOFTWARE 8.7.1 ACCELEROMETER BASICS 7.2 ADXL3XX 7.VIII ARRAY (FPGA) 6.3 Addressing 7.7 I2C BUS 7.3 FEATURES OF ADXL3XX 7.2 XILINX WEB EDITION 8.

5 CREATING A NEW PROJECT 8.IX 8.6 PROGRAM 42 43 83 84 9 CONCLUSION REFERENCES .

20 28 30 31 35 .2 6.X LIST OF TABLES TABLE NO.3 7. 5.1 6.1 6.1 TITLE GPS Receiver Characteristics DIP switch connections with FPGA LED pin connections with FPGA LCD pin connections with FPGA Pin Function Descriptions of ADXL335 PAGE NO.

6 7.4 6.3 6.5 6.4 3.2 3.2 6.2 7.XI LIST OF FIGURES FIGURE NO.3 7.2 6.1 7.1 3.4 8.1 5.1 5.3 3. 3.1 6.5 3.1 General Block Diagram Pin connections Block Diagram of Linear Power Supply Circuit Diagram of 5V Power Supply Multi Output Power Supply Regulator General Block Diagram of GSM MODEM GPS Principle GPS Device Example of a Logic Cell Logic Block Pin Locations Architecture of SPARTAN 3E Board SPARTAN 3E Board Pin Configuration of PCF 8951 Port Configuration of Spartan Processor Functional Block Diagram of ADXL335 Pin Configuration of ADXL335 Pin Configuration of IC 8951 Address Byte in I2C Design Flow in VHDL TITLE PAGE NO.6 4. 5 6 7 8 8 9 13 15 18 25 26 29 30 31 32 34 34 38 39 41 .

XII LIST OF ABBREVIATIONS GPS GSM SMS FPGA HDL VHDL AC DC IC TDMA FDMA GMSK LPC USB NMEA LUT CPLD VHSIC Global positioning system Global system for mobile Communications Short message service Field programmable gate array Hardware description language VHSIC Hardware description language Alternating current Direct current Integrated circuit Time Division multiple access Frequency division multiple access Gaussian Minimum Shift Keying Linear predictive coding Universal serial bus National Marine Electronics Association Lookup table Complex programmable logic device Very High Speed Integrated Circuit .

When there is any accident. this project came into existence. a luxury hotel in Singapore has been known to install vehicle tracking system in their limousines to ensure they can welcome their VIPs when they reach the hotel. Field Sales etc. Vehicle tracking systems have also been used in food delivery and car rental companies. an estimated 1. Police to clear the traffic. Field Service Management. To solve problems like these. . For example. In most of the accident cases. Ambulance to save the people can be informed by this device. This uses a GPS (Global Positioning System) to know the exact position of the vehicle with an accuracy of a few feet. the system sends automated messages to the pre-programmed numbers. A FPGA is used to control and co-ordinate all the parts used in this system. In case of any accident. Industries not traditionally known to use vehicle tracking systems have started to use it in creative ways to improve their processes or businesses. India's road accident records 16 % of the world's road accident deaths.2 million people lose their lives every year due to car accidents.1 CHAPTER 1 INTRODUCTION There is a drastic increase in the number of vehicles in these days which also cause a steep rise in the number of accidents with a lot of people losing their lives. the drivers use t he company‘s vehicles even for their own purposes and impact a loss to the company. an accelerometer sensor is triggered and it sends signal to the FPGA. This project is mainly used to track the position of the Vehicle by the owner or can also be used in the public transportation system by the people to know the location of the buses or trains. The hospitality industry has caught on to this technology to improve customer service. The FPGA circuit processes the input and sends the appropriate output according to the programming done. The owner of the vehicle. Stolen Vehicle recovery. This can also be used for other purposes such as asset tracking. According to the World Health Organization. We can send messages to any number of mobiles. the victims lose their lives because of the unavailability of medical facilities at the right time. Fleet management. GSM is used to receive SMS from the user and reply the position of the vehicle through a SMS. whereas India has only 1 % of the world's road vehicles. It is due to the increase in the number of vehicles without a subsequent increase in the road facilities required for it. In large companies with a large number of vehicles.

These components are controlled by a system which is designed using VHDL on Altera MAX plus I1 software.1 Overview: The papers published in IEEE journals regarding vehicle position tracking system and its implementation on Fpga has helped to develop this project by analyzing the defects and using the effective ways from all resources available. The designed system is implemented on Altera UPlX demohoard. 2. And also GPS system ensures maximum accuracy in finding the vehicular position ranging within few feets.2 CHAPTER 2 LITERATURE REVIEW 2. and it is implemented on FPGA chip Altera UPlX demoboard (Altera FLEX 10KEPF).2 Perspective of Hapsari . The concept of the reference papers and how it helped in designing this system is described in the following subsections. Syamsudin. In this way the author gets the position of the vehicle and send it to any user who gives the request for tracking. There are two testing and verification procedures of this system. . Using the mobile phone attached in the system . The objective of this project is to achieve a design of such system that can give information of the vehicle position every time there's a request for it. Safety and security is a major concern for all vehicle owners . Pramana: This project is referenced to the paper ―Design of vehicle position tracking system using short message services and its implementation on fpga‖ done by Arias Tanti Hapsari . Imron Pramana. In this reference paper author used ‗GPS module‘ to receive the vehicular position and. This vehicle tracking system ensures safety and security of vehicle by tracking its position and sending it to owner or any people whenever it is requested by them.the position of the vehicle is sent as ―short message service‖(SMS) to the requested people. ‗short messaging service via mobile phone‘ to receive user request and to send the vehicle‘s position. Eniman Y Syamsudin and.

fast. Zantout : Another paper referenced is‖ GPS-based Vehicle Tracking System-on-Chip‖. a more cohesive architecture.3 Perspective of Adnan I. This system is designed using a system-on-chip (SOC) replacement of the current microcontroller-based implementation. The reconfiguration of resources in different parallel topologies allows for a good matching with the inherent intrinsic parallelism of an algorithm or a specific operation. An application that needs real-time. Yaqzan. and Rached N. Reconfigurable systems enable extensive exploitation of computing resources. dataparallel. The introduction of a new paradigm in hardware design called Reconfigurable Computing (RC) offers to solve any problem by changing the hardware configurations to offer the performance of dedicated circuits. a faster processing time and an enhanced system interaction. the Base Station (BS) and the Mobile Unit (MU). It is a compiler. Damaj. The proposed SOC is built on a field programmable gate array (FPGA) promising a cheaper design. Issam W. It consists of two main parts. and reliable data processing is the global positioning system (GPS)-based vehicle tracking system (VTS). The BS consists of a PIC Microcontroller based hardware connected to the serial port of a computer. As the complexity of FPGA-based designs grow. One of the modern tools is Quartus II. a need for a more efficient and flexible design methodology is required. . Modern powerful reconfigurable systems are suited in the implementation of various data-stream. and other applications .3 2. simulator. Reconfigurable computing enables mapping software into hardware with the ability to reconfigure its connections to reflect thesoftware being run. The ability to completely reprogram the computer‘s hardware implies that this new architecture provides immense scope for emulating different computer architectures. The MU is a self-contained PIC Microcontroller based hardware and a GPS module. analyzer and synthesizer with a great capability of verification and is chosen to be used for this implementation.

There is also a GPS unit and RF transceiver.4 The latter would keep track of all the positions traversed by the vehicle and records them in its memory. 2. The system has a great storage capacity.4 Conclusion: With the help of advancement in technology using an FPGA controlled system we can easily track any object or vehicle which ensures safety for vehicle owners and also lots of uses for public transport system. and could perform a significant recording with a considerable sampling rate. . The mobile unit (MU) of the addressed Aram Locator consists of two communicating microcontrollers interfaced with memory.

Accident warning System is used to save the person‘s life by making the medical facilities arriving in time. 3. An accelerometer sensor is used to detect any accident which will trigger a signal in case of any accidents.2 Block Diagram of the System: GPS RECIEVER Request from user SIGNAL CONDITIONING CIRCUIT FPGA SPARTAN 3E GSM MODULE ACCLEROMETER SENSOR POWER SUPPLY CIRCUIT Response from the system Figure 3. the response is sent to user via a GSM modem. The Vehicular tracking System can be used by the owner of the Vehicle to track the position of the vehicle and also can be used by the people in public transportation Systems.1 System overview: This project is custom made for the heavily populated countries like India. A FPGA Spartan processor is used to coordinate all the parts in this system according to the program done.1 General Block Diagram . In public transportation System. Once the SMS is received from user. People can know the location of the buses or trains which will ease them.5 CHAPTER 3 DESIGN OF SYSTEM STRUCTURE AND POWER SUPPLY 3. The location of the vehicle can be known by using a GPS receiver.

Power Supply is the device that transfers electric power from a source to a load using electronic circuits. some power supplies require the following: electrical isolation between the source and load. Some of the requirements of power supplies are small size. lightweight.2 : Pin connections 3.6 Figure 3. and high power factor (PF) if the source is ac voltage. Then using diode rectifiers it is converted into suitable dc supply and given as input to the microprocessor and all other circuits in the equipment. Power supplies are used in many industrial and aerospace applications and also in consumer products. we use transformers to convert domestic ac voltage to 9V ac. Typical application of power supplies is to . low cost. In addition to these.3 Power Supply Circuit: In this block. Some special power supplies require controlled direction of power flow. low harmonic distortion for the input and output waveforms. and high power conversion efficiency.

and then a dc-to-dc converter can be used to get a controlled dc output. The step down transformer converts the AC input with the higher level to some lower level. theoretically zero noise. The ac source can be rectified with a bridge rectifier to get an uncontrolled dc.7 convert utility's AC input power to a regulated voltage(s) required for electronic equipment. Depending on the mode of operation of power semiconductors power supply can be linear or switching. . while the winding with less turns has lower voltage but higher current. A four-transistor converter (Bridge Rectifier) that can generate the highest output power than other types of rectifiers. so it follows that the power (V × I) on either side must be constant. They have very small output ripple. The regulator down-convert a DC voltage to a lower DC voltage of the same polarity. In these power supplies. The action of a transformer is such that a time-varying (AC) voltage or current is transformed to a higher or lower value. electrical isolation can only be provided by bulky line frequency transformers. as set by the transformer turns ratio.3.1 Linear Power Supply: A linear power supply is the oldest and simplest type of power supply.3 Block Diagram of Linear Power Supply The transformer does not add power. Figure3. large hold-up time (typically 1–2 ms). The filter circuit resists the unwanted AC signals. 3. and fast response. also referred to as a series regulator). A bridge rectifier converts the AC voltage into DC voltage. That is the reason that the winding with more turns has higher voltage but lower current. The output voltage is regulated by dropping the extra input voltage across a series transistor (therefore.

In multi output power supply a single voltage must be converted into the required system voltages (for example. +12V and -12V) with very high power conversion efficiency.4 Circuit Diagram for 5V power Supply 3.5 Multi Output power Supply . +5V.8 Figure 3.3.2Multi output Power Supply: It is also possible to generate multiple voltages using linear power supplies. Figure 3.

6 :Regulator . Negative voltage regulators are available. Figure 3.3. 12 and 15V) or variable output voltages. Most regulators include some automatic protection from excessive current ('overload protection') and overheating ('thermal protection'). They are also rated by the maximum current they can pass.9 3. mainly for use in dual supplies.3 Regulator: Voltage regulators ICs are available with fixed (typically 5.

This also facilitates the wide-spread implementation of data communication applications into the system. The GSM Association estimates that 80% of the global mobile market uses the standard. GSM also pioneered low-cost implementation of the short message service (SMS).10 CHAPTER 4 GLOBAL SYSTEM FOR MOBILE(GSM) 4. 400 and 450 MHz frequency bands are assigned in some countries. GSM differs from its predecessor technologies in that both signalling and speech channels are digital.5 billion people across more than 212 countries and territories. and also to network operators.The GSM uses Gaussian Minimum Shift Keying (GMSK) modulation method. also called text messaging. This ubiquity means that subscribers can use their phones throughout the world. notably Scandinavia) Modulation: Modulation is a form of change process where we change the input information into a suitable format for the transmission medium.GSM chose a . The GSM standard has been an advantage to both consumers. and thus GSM is considered a second generation (2G) mobile phone system. We also changed the information by demodulating the signal at the receiving end. GSM is used by over 1. 4. who can choose equipment from many GSM equipment vendors. which has since been supported on other mobile phone standards as well. who may benefit from the ability to roam and switch carriers without replacing phones. Access Methods: Because radio spectrum is a limited resource shared by all users.1 GSM overview: Global System for Mobile Communications (GSM) is the world‘s most popular standard for mobile telephony systems. enabled by international roaming arrangements between mobile network operators. a method must be devised to divide up the bandwidth among as many users as possible.2 GSM specifications: Frequency: 900 MHz or 1800 MHz (Some countries in the Americas including Canada and the United States use the 850 MHz and 1900 MHz bands.

4. A channel has two frequencies. Frequency Band: The uplink frequency range specified for GSM is 933 . just like a mobile phone. The purpose of LPC is to reduce the bit rate. Duplex Distance: The duplex distance is 80 MHz Duplex distance is the distance between the uplink and downlink frequencies. 80 MHz apart.915 MHz (basic 900 MHz band only).8 Kbps. Typically. The downlink frequency band 890 . and operates over a subscription to a mobile operator. One or more carrier frequencies are then assigned to each BS.833 K symbols/second. Channel Spacing: This indicates separation between adjacent carrier frequencies. this is 200 kHz. A GSM . A wireless modem behaves like a dial-up modem. Transmission Rate: The total symbol rate for GSM at 1 bit per symbol in GMSK produces 270. into eight time slots. A GSM modem can be an external device or a PC Card / PCMCIA Card. Each of these carrier frequencies is then divided in time. The gross transmission rate of the time slot is 22. The main difference between them is that a dial-up modem sends and receives data through a fixed telephone line while a wireless modem sends and receives data through radio waves. The LPC provides parameters for a filter that mimics the vocal tract.960 MHz (basic 900 MHz band only). They are separated in time so that the mobile unit does not receive and transmit at the same time. In GSM. The FDMA part involves the division by frequency of the total 25 MHz bandwidth into 124 carrier frequencies of 200 kHz bandwidth. One time slot is used for transmission by the mobile and one for reception. an external GSM modem is connected to a computer through a serial cable or a USB cable. leaving behind a residual signal. The signal passes through this filter. Speech is encoded at 13 kbps. Speech Coding: GSM uses linear predictive coding (LPC). using a TDMA scheme. From the mobile operator perspective. a GSM modem looks just like a mobile phone.11 combination of TDMA/FDMA as its method.3 GSM Modem: A GSM modem is a specialized type of modem which accepts a SIM card.

whereas others interpret it as "Attention Terminal" commands.12 modem in the form of a PC Card / PCMCIA Card is designed for use with a laptop computer. Like a GSM mobile phone. There are different views to understand the meanings of "AT". It should be inserted into one of the PC Card / PCMCIA Card slots of a laptop computer. writing and deleting SMS messages. Monitoring the signal strength. In addition to the standard AT commands. a GSM modem requires a SIM card from a wireless carrier in order to operate. Reading. 4. Some call it "Attention Telephone". SIM Phonebook management Fixed Dialling Number (FDN) Real time clock The number of SMS messages that can be processed by a GSM modem per minute is very low -. The commands are sent to the phone's modem.3. Monitoring the charging status and charge level of the battery. Sending SMS messages. Fortunately. Different manufacturers may have different sets of AT commands. writing and searching phone book entries. With the extended AT commands.. . Mobile device manufacturers may also give attention to operators to allow or not to allow some commands on phones. AT commands allow giving instructions to both mobile devices and ordinary landline telephones. These extended AT commands are defined in the GSM standards. you can do things like:         Reading. You can use a GSM modem just like a dial-up modem. GSM modems support an extended set of AT commands.1AT commands: AT commands are also known as Hayes AT commands. many AT commands are the same.only about six to ten SMS messages per minute. which can be a GSM modem or PC modem. Both GSM modems and dial-up modems support a common set of standard AT commands.

1 General Block Diagram of GSM MODEM .13 Figure 4.

Each of these 3.000. The U. Many GPS units show derived information such as direction and speed. calculated from position changes. The fundamental navigation principle is based on the measurement of pseudo ranges between the user and four satellites. anywhere on Earth." they usually mean a GPS receiver. The receiver uses the messages it receives to determine the transit time of each message and computes the distance to each satellite. When people talk about "a GPS.to 4. military developed and implemented this satellite network as a military navigation system.S. depending on which algorithm is used. These distances along with the satellites' locations are used with the possible aid of trilateration.14 CHAPTER 5 GPS (GLOBAL POSITIONING SYSTEM) 5. to compute the position of the receiver. A GPS receiver calculates its position by precisely timing the signals sent by GPS satellites high above the Earth. 5. but soon opened it up to everybody else.300 km). The orbits are arranged so that at anytime.range .000-pound solar-powered satellites circles the globe at about 12.2 GPS Principle: The GPS satellites act as reference points from which receivers on the ground detect their position. elevation information may be included. The Global Positioning System (GPS) is actually a constellation of 27 Earth-orbiting satellites (24 in operation and three extras in case one fails). direction and speed.1 GPS Basics: The Global Positioning System (GPS) is a space-based global navigation satellite system (GNSS) that provides reliable location and time information in all weather and at all times and anywhere on or near the Earth when and where there is an unobstructed line of sight to four or more GPS satellites. It is maintained by the United States government and is freely accessible by anyone with a GPS receiver.000 miles (19. making two complete rotations every day. Each satellite continually transmits messages that include the time the message was transmitted precise orbital information (the ephemeris) the general system health and rough orbits of all GPS satellites (the almanac). Ground stations precisely monitor the orbit of every satellite and by measuring the travel time of the signals transmitted from the satellite four distances between receiver and satellites will yield accurate position. This position is then displayed. there are at least four satellites "visible" in the sky. perhaps with a moving map display or latitude and longitude. Though three .

. Dual frequency observations are important for large station separation and for eliminating most of the error parameters. and some may also calculate altitude. although this is not considered sufficiently accurate or continuously available enough (due to the possibility of signal blockage and other factors) to rely on exclusively to pilot aircraft. Thus. The user segment is composed of hundreds of thousands of U.3 GPS Receiver: A GPS navigation device is any device that receives Global Positioning System (GPS) signals for the purpose of determining the device's current location on Earth. Figure 5. GPS devices are used in military. and allied military users of the secure GPS Precise Positioning Service.1 GPS Principle 5. Moreover the high frequency L1 and L2 carrier signal can easily penetrate the ionosphere to reduce its effect. and tens of millions of civil. the term ―pseudo ranges‖ is derived. commercial and scientific users of the Standard Positioning Service. aviation.15 measurements are sufficient. The secret of GPS measurement is due to the ability of measuring carrier phases to about 1/100 of a cycle equalling to 2 to 3 mm in linear distance. the fourth observation is essential for solving clock synchronization error between receiver and satellite. GPS devices provide latitude and longitude information.S. marine and consumer product applications.

Originally limited to four or five. its state. L2 being reserved for the American Army. 5.4 Major Components of a GPS Receiver: The main components of a GPS receiver are       Antenna with pre-amplifier RF section with signal identification and signal processing Micro-processor for receiver control.800 bit/s speed. using the RTCM SC-104 format. This data allows the receiver to calculate its position. They may also include a display for providing location and speed information to the user. allowing a very precise measure of time. the position of the other satellites. Data is actually sent at a much lower rate. data storage 5. the position of the satellite. data sampling and data processing oscillator Power supply User interface. tuned to the frequencies transmitted by the satellites. Every satellite makes a complete rotation of the Earth every 12 hours. As of 2006. which limits the accuracy of the signal sent using RTCM. Receivers with internal DGPS receivers can outperform those using external RTCM data. Every satellite thus sends ceaselessly a code of 1500 bits. and a highly stable clock (often a crystal oscillator). Each GPS satellite transmits radio signals that enable the GPS receivers to calculate where its (or your vehicles) location on the Earth and convert the calculations into geodetic latitude. containing numerous data such as the time at which the code is to be sent. receiver-processors. Every satellite possesses an atomic clock. longitude and . Many GPS receivers can relay position data to a PC or other device using the NMEA 0183 protocol. this has progressively increased over the years so that. 4 per orbit. even low-cost units commonly include Wide Area Augmentation System (WAAS) receivers.5 Function Of GPS: It is a "constellation" of twenty-four 20.. They emit on two different frequencies: L1: 1575 MHz and L2: 1227 MHz. GPS receivers may include an input for differential corrections. The satellites are distributed on 6 orbits. receivers typically have between 12 and 20 channels.. command and display panel Memory.16 GPS receivers are composed of an antenna.000km high GPS satellites. as of 2007. A receiver is often described by its number of channels: this signifies how many satellites it can monitor simultaneously. This is typically in the form of an RS232 port at 4.

A receiver needs signals from at least three GPS satellites to pinpoint your vehicle‘s position. there are various techniques available that substantially increase the SPS accuracy.7 meter vertical accuracy • 100 nanosecond time accuracy Published specifications for the Standard Positioning Service are: • 100 meter horizontal accuracy • 156 meter vertical accuracy • 167 nanoseconds time accuracy.Proprietary Format . Published specifications for the Precise Positioning Service are: • 17. although under certain conditions can be used by civilians who have specialized equipment. As we will see. even well beyond that which is offered by the PPS. NMEA (Nation Marine Electronics Association) ASCII Format Defines a set of standard messages. and the Precise Positioning Service (PPS). The Standard Positioning Service offers a base-line accuracy that is much lower than the PPS. The Precise Positioning Service is a highly accurate positioning. 2.Two levels of navigation and positioning are offered by the Global Positioning System: The Standard Positioning Service (SPS). A system based on GPS can only calculate its location but cannot send it to central control room. They cannot communicate back with GPS or any other satellite.17 velocity. 5. 1. but is available to all users with even the most inexpensive receivers.6 RECEIVER OUTPUT: Typically receivers provide two different formats. GPS Receivers commonly used in most Vehicle tracking systems can only receive data from GPS Satellites. velocity and timing service that is designed primarily for the military and other authorized users.8 meter horizontal accuracy • 27. In order to do this they normally use GSM-GPRS Cellular networks connectivity using additional GSM modem/module.

A full copy of this standard is available for purchase at their web site.sss GPS receiver gives the latitude. no of satellites on view etc… The National Marine Electronics Association (NMEA) has developed a specification that defines the interface between various pieces of marine electronic equipment.18 Typically Binary No limit on information transmitted Receiver output is related to position. The output in the following Position: Latitude: degrees: minutes: seconds Longitude: degrees: minutes: seconds Altitude m Velocity: Speed knots Heading degrees Time (UTC): Date dd/mm/yy Time hh/mm/ss.2 GPS Device . date.7 GPS DEVICE: Figure 5. 5. velocity and time. None of the information on this site comes from this standard and I do not have a copy. time. longitude. speed of the satellite. The standard permits marine electronics to send information to computers and to other marine equipment. Anyone attempting to design anything to this standard should obtain an official copy.

19 5. Antenna open short detection/protection Tracking sensitivity:-154dB-m Acquisition sensitivity –148dB-m 5v and 3. Very good acquisition and good tracking sensitivity.3volt option available. .8 RECEIVER FEATURES:       12 parallel channel L1 Band SPS GPS.

1 GPS Receiver Characteristics .20 Table 5.

The data is contained within this single line with data items separated by commas. Each sentence begins with a '$' and ends with a carriage return/line feed sequence and can be no longer than 80 characters of visible text (plus the line terminators). The data itself is just ASCII text and may extend over multiple sentences in certain specialized instances but is normally fully contained in one variable length sentence. The data may vary in the amount of precision contained in the message.21 Most computer programs that provide real time position information understand and expect data to be in NMEA format. Programs that read the data should only use the commas to determine the field boundaries and not depend on column positions. but I am not aware of any GPS products that require conformance to this version. For example time might be indicated to decimal parts of a second or location may be show with 3 or even 4 digits after the decimal point. but not including. These just specify some different sentence configurations which may be peculiar to the needs of a particular device thus the GPS may need to be changed to match the devices being interfaced to. There have been several changes to the standard but for GPS use the only ones that are likely to be encountered are 1. All proprietary sentences begin with the letter P and are followed with 3 letters that identifies the manufacturer controlling that sentence.3.01. (For GPS receivers the prefix is GP. There are standard sentences for each device category and there is also the ability to define proprietary sentences for use by the individual company.5 and 2. . In addition NMEA permits hardware manufactures to define their own proprietary sentences for whatever purpose they see fit. For example a Garmin sentence would start with PGRM and Magellan would begin with PMGN. velocity. Some GPS's provide the ability configure a custom set the sentences while other may offer a set of fixed choices. which may or may not be checked by the unit that reads the data. The idea of NMEA is to send a line of data called a sentence that is totally self-contained and independent from other sentences. Many GPS receivers simply output a fixed set of sentences that cannot be changed by the user. This data includes the complete PVT (position. I have no specific information on this version. All of the standard sentences have a two-letter prefix that defines the device that uses that sentence type.0 through 2. The current version of the standard is 3. The checksum field consists of a '*' and two hex digits representing an 8 bit exclusive OR of all characters between. the '$' and '*'. time) solution computed by the GPS receiver. There is a provision for a checksum at the end of each sentence. A checksum is required on some sentences.) This is followed by a three-letter sequence that defines the sentence contents.

The NMEA standard has been around for many years (1983) and has undergone several revisions.22 5. The interface speed can be adjusted on some models but the NMEA standard is 4800 b/s (bit per second rate) with 8 bits of data. The protocol has changed and the number and types of sentences may be different depending on the revision. then use the data for screen display. Generally time is sent in some field within each second so it is pretty easy to figure out what a particular GPS is doing. and one stop bit. The actual limit is determined by the specific sentences used. This standard dictates a transfer rate of 4800 b/s.8 Hardware Connection: The hardware interface for GPS units is designed to meet the NMEA requirements. They are also compatible with most computer serial ports using RS232 protocols.5. which transferred data at 1200 b/s. and then sample the data again. They recommend conformance to EIA-422. you can easily send enough data to more than fill a full second of time. Some programs cannot do this and these programs will sample the data stream. however strictly speaking the NMEA standard is not RS232. Some Garmin units and other . Some receivers also understand older standards. Note that. Depending on the time needed to use the data there can easily be a lag of 4 seconds in the responsiveness to changed data. Most GPS receivers understand the standard. Several second delays could make the entire system seem unresponsive and could cause you to miss your turn. For this reason some units only send updates every two seconds or may send some data every second while reserving other data to be sent less often. In addition some units may send data a couple of seconds old while other units may send data that is collected within the second it is sent. but this shows that it is easy to overrun the capabilities if you want rapid sentence response. at a b/s rate of 4800. The oldest standard was 0180 followed by 0182. This may be fine in some applications but totally unacceptable in others. NMEA is designed to run as a process in the background spitting out sentences which are then captured as needed by the using program. Some sentences may be sent only during a particular action of the receiver such as while following a route while other receivers may always send the sentence and just null out the values. Other difference will be noted in the specific data descriptions defined later in the text. Since an NMEA sentence can be as long as 82 characters you can be limited to less than 6 different sentences. which is called: 0183 version 2. All units that support NMEA should support this speed. Some receivers also understand an earlier version of 0183 called version 1. no parity. For example a car traveling at 60 mph will travel 88 feet in one second. At 4800 b/s you can only send 480 characters in one second.

and altitude along the signal path. but they can be reduced substantially with position fix averaging. An ephemeris error is a residual error in the data used by a receiver to locate a satellite in space. ephemeris data and ionosphere and tropospheric delay. Usually. temperature. Non-Correctable Errors Non-correctable errors cannot be correlated between two GPS receivers that are located in the same general area. Clock errors and ephemeris errors originate with the GPS satellite. Multi-path errors are caused by the receiver ―seeing‖ reflections of signals that have bounced off of surrounding objects. which are environmental. . Ionospheric delay is caused by the density of electrons in the ionosphere along the signal path. Therefore. two GPS receivers that are sufficiently close together will observe the same fix error. Correctable Errors Sources of correctable errors include satellite clock. Correctable errors are the errors that are essentially the same for two GPS receivers in the same area. Noncorrectable errors cannot be correlated between two GPS receivers in the same area. The amount of error and direction of the error at any given time does not change rapidly. The submeter antenna is multipath-resistant. SA may also cause a correctable positioning error.23 brands can be set to 9600 for NMEA output or even higher but this is only recommended if you have determined that 4800 works ok and then you can try to set it faster. If implemented. 5. which is unavoidably inherent in any receiver. and multipath errors. Setting it to run as fast as you can may improve the responsiveness of the program.9 Types of Errors: There are two types of positioning errors: correctable and non-correctable. Neither error can be eliminated with differential. A tropspheric delay is related to humidity. A clock error is a slowly changing error that appears as a bias on the pseudorange measurement made by a receiver. a tropospheric error is smaller than an ionospheric error. Sources of non-correctable errors include receiver noise. its use is required when logging carrier phase data. and the size of the fix error can be determined. Ionosphere delay errors and tropospheric delay errors are caused by atmospheric conditions.S Department of Defence to introduce errors into Standard Positioning Service (SPS) GPS signals to degrade fix accuracy. Another correctable error is caused by SA which is used by U.

offer advantages for many applications. Such devices blur the line between an FPGA. The most common analog feature is programmable slew rate and drive strength on each output pin. which may be simple flip-flops or more complete blocks of memory. the logic blocks also include memory elements. Another relatively common analog feature is differential comparators on input pins designed to be connected to differential signalling channels. Logic blocks can be configured to perform complex combinational functions. faster rates on heavily loaded pins on high-speed channels that would otherwise run too slow. In addition to digital functions. and field-programmable analog array (FPAA). The FPGA configuration is generally specified using a hardware description language (HDL). or merely simple logic gates like AND and XOR.24 CHAPTER 6 SPARTAN 3E BOARD 6. Architecture of FPGA: . partial re-configuration of the portion of the design and the low nonrecurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost). which carries digital ones and zeros on its internal programmable interconnect fabric. as they were for ASICs. but this is increasingly rare). In most FPGAs. FPGAs can be used to implement any logical function that an ASIC could perform. which carries analog values on its internal programmable interconnect fabric. allowing the engineer to set slow rates on lightly loaded pins that would otherwise ring unacceptably. similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration. A few "mixed signal FPGAs" have integrated peripheral Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip. and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together" —somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations.1 Concept of Field-programmable Gate Array (FPGA): A Field-programmable Gate Array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing —hence "field-programmable". and to set stronger. FPGAs contain programmable logic components called "logic blocks". some FPGAs have analog features. The ability to update the functionality after shipping.

. Figure 6. depending on vendor). in the figure example. all the routing channels have the same width (number of wires). I/O pads. FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of LUTs and IOs can be routed. This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs. entire or parts of the FA are put as functions into the LUTs in order to save space.1 Example of a logic cell ALMs and Slices usually contain 2 or 4 structures similar to the example figure. The LUTs are in this figure split into two 3-input LUTs. LE. In general. Generally.CLBs/LABs typically contain a few ALMs/LEs/Slices. In practice. CLB. manufacturers have started moving to 6-input LUTs in their high performance parts. or Logic Array Block. A typical cell consists of a 4-input Lookup table (LUT). claiming increased performance. Slice etc). a crossbar switch requires much more routing than a systolic array with the same gate count. Multiple I/O pads may fit into the height of one row or the width of one column in the array. The selection of mode is programmed into the middle mux. The output can be either synchronous or asynchronous. While the number of CLBs/LABs and I/Os required is easily determined from the design. a logic block (CLB or LAB) consists of a few logical cells (called ALM. depending on the programming of the mux to the right. with some shared signals.25 The most common FPGA architecture consists of an array of logic blocks (called Configurable Logic Block. the number of routing tracks needed may vary considerably even among designs with the same amount of logic.In recent years. their outputs are fed to the FA. In normal mode those are combined into a 4-input LUT through the left mux. An application circuit must be mapped into an FPGA with adequate resources. LAB. In arithmetic mode. and routing channels. a Full adder (FA) and a D-type flip-flop. For example. as shown below. Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit.

the user provides a hardware description language (HDL) or a schematic design. Then. they and other signals are separately managed. For this example architecture.Each logic block output pin can connect to any of the wiring segments in the channels adjacent to it. and other verification methodologies. the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA. schematic entry can allow for easier visualisation of a design. Similarly. This file is then . Once the design and validation process is complete. a technology-mapped netlist is generated. Figure 6. the locations of the FPGA logic block pins are shown below. Going from schematic/HDL source files to actual configuration: The source files are fed to a software suite from the FPGA/CPLD vendor that through different steps will produce a file. The user will validate the map. usually performed by the FPGA company's proprietary place-and-route software. The HDL form is more suited to work with large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. FPGA designing and Programming: To define the behavior of the FPGA. For example. while the output pin can connect to routing wires in both the channel to the right and the channel below the logic block. an I/O pad can connect to any one of the wiring segments in the channel adjacent to it.2 Logic Block Pin Locations Each input is accessible from one side of the logic block.26 Since clock signals (and often other high-fanout signals) are normally routed via specialpurpose dedicated routing networks in commercial FPGAs. simulation. place and route results via timing analysis. using an electronic design automation tool. The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route. However. an I/O pad at the top of the chip can connect to any of the W wires (where W is the channel width) in the horizontal channel immediately below it.

Then. Other predefined circuits are available from developer communities such as Open Cores (typically released under free and open source licenses such as the GPL. although in an attempt to reduce the complexity of designing in HDLs. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values backannotated onto the netlist.000-gate Xilinx Spartan-3E XC3S100E FPGA in a 144-Thin Quad Flat Pack package (XC3S100E-TQ144)     2. These predefined circuits are commonly called IP cores. Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. there are moves to raise the abstraction level through the introduction of alternative languages. which have been compared to the equivalent of assembly languages. there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process.160 logic cell equivalents Four 18K-bit block RAMs (72K bits) Four 18x18 pipelined hardware multipliers Two Digital Clock Managers (DCMs) * 32 Mbit Intel Strata Flash * 3 numbers of 20 pin header to interface VLSI based experiment modules * 8 input Dip Switches . National Instrument's Lab VIEW graphical programming language ( sometimes referred to as "G" ) has an FPGA add-in module available to target and program FPGA hardware. the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. The most common HDLs are VHDL and Verilog. BSD or similar license). To simplify the design of complex systems in FPGAs. an FPGA application developer will simulate the design at multiple stages throughout the design process.27 transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device like an EEPROM. and other sources.2 Features of SPARTAN 3E Board: * 100. The LabVIEW approach drastically simplifies the FPGA programming process. 6. In a typical design flow. after the synthesis engine has mapped the design to a netlist. and are available from FPGA vendors and third-party IP suppliers (rarely free and typically released under proprietary licenses).

Input Switches: The Spartan-3E Low Cost Kit has 8 way Dip switches for giving inputs to the FPGA i/o lines. Dip Switch connections with FPGA: Table 6.1 DIP switch connections with FPGA . Moving the power switch Up for Power On and down for power off. Configuration Switch: The Spartan-3E Low Cost Kit has a push button Switch to Configure the FPGA from Xilinx Serial Flash PROM.3 Architecture of Spartan 3E Board: Power Switch: The Spartan-3E Low Cost Kit has a slide power switch.28 * 8 output Light Emitting Diodes(LEDs) * On Board programmable oscillator (3 to 200 MHz) * 16x2 Alphanumeric LCD * RS232 UART * 4 Channel 8 Bit I2C based ADC & single Channel DAC * PS/2 Keyboard/Mouse * Prototyping area for user applications * On Board configuration Flash PROM XCF01S 6.

29 Figure 6.3 Architecture of SPARTAN 3E Board .

30

Figure 6.4 SPARTAN 3E Board

Output LEDs: The Spartan-3E Low Cost Kit has 8 individual surface-mount LEDs. The LEDs are labelled L3 to L10.The cathode of each LED connects to ground. To light an individual LED, drive the associated FPGA control signal High. LED connections with FPGA:

Table 6.2 LED pin connections with FPGA

31 Character LCD Screen: The Spartan-3E Low Cost Kit prominently features a 2-line by 16-character liquid crystal display (LCD). The FPGA controls the LCD via the 8-bit data interface.

LCD Connections with FPGA:

Table 6.3 LCD pin connections with FPGA Analog to digital converter & digital to Analog converter:

Figure 6.5 Pin Configuration of PCF 8591 The PCF8591 is a single-chip, single-supply low power 8-bit CMOS data acquisition device with four analog inputs, one analog output and a serial I2C-bus interface. Three address pins A0, A1 and A2 are used for programming the hardware address, allowing the use of up to eight devices connected to the I2C-bus without additional hardware. Address, control and data to and from the device are transferred serially via the two-line bidirectional I2C-bus. The functions of the device include analog input multiplexing, on-chip track and hold function, 8-bit analog-to-digital conversion and an 8-bit digital-to-analog conversion. The maximum conversion rate is given by the maximum speed of the I2C-bus.

32

Figure 6.6 : Port Configuration of Spartan Processor

and moving detection. so you need a A/D converter to read the acceleration value. The motion is detected in a sensitive portion of the accelerometer. and Z axis. Thus.000 g shock survival Excellent temperature stability BW adjustment with a single capacitor per axis RoHS/WEEE lead-free compliant . This motion is indicative of motion in the larger object or application in which the accelerometer is mounted.1 Accelerometer Basics: Accelerometers are sensors or transducers that measure acceleration.3 FEATURES OF ADXL3XX :       3-axis sensing Small. slope.2 ADXL3XX: 3 Axis Acceleration Sensor Board based on ADXL3XX from Analog devices. a sensitive accelerometer can quickly detect motion in the application. Accelerometers are useful in detecting motion in objects. A moving body possesses an inertia which tends to resist change in velocity.33 CHAPTER 7 ACCELEROMETER SENSOR 7. An accelerometer measures force exerted by a body as a result of a change in the velocity of the body. Accelerometers generally measure acceleration forces applied to a body by being mounted directly onto a surface of the accelerated body. 7. It is this resistance to change in velocity that is the source of the force exerted by the moving body.6 V 10. Output sensitivity could be select by simply set voltage level on few pins. User could get acceleration value of X.45 mm LFCSP Low power : 350 mA (typical) Single-Supply operation: 1. The output of MMA7260Q is analog mode. Y. And it is widely used in shock. It is a first generation 3 axis acceleration sensor. low profile package 4 mm × 4 mm × 1. This force is directly proportional to the acceleration component in the direction of movement when the moving body is accelerated.8 V to 3. 7.

2 Pin Configuration of ADXL335 .4 Functional Block Diagram: Figure 7.34 7.1 Functional Block Diagram of ADXL335 Pin Configuration: Figure 7.

The ADXL335 has a measurement range of ±3 g mini-mum. . The sensor is a polysilicon surface-micromachined structure built on top of a silicon wafer. It contains a polysilicon surface-micromachined sensor and signal conditioning circuitry to implement an open-loop acceleration measurement architecture. The accelerometer can measure the static acceleration of gravity in tilt-sensing applications as well as dynamic acceleration resulting from motion. Acceleration deflects the moving mass and unbalances the differential capacitor resulting in a sensor output whose amplitude is proportional to acceleration. The output signals are analog voltages that are proportional to acceleration. This filtering improves measurement resolution and helps prevent aliasing.1 Pin Function Descriptions of ADXL335 7. shock. Phase-sensitive demodulation techniques are then used to determine the magnitude and direction of the acceleration. The demodulator output is amplified and brought off-chip through a 32 kΩ resistor.35 Table 7. Deflection of the structure is meas-ured using a differential capacitor that consists of independent fixed plates and plates attached to the moving mass.5 THEORY OF OPERATION : The ADXL335 is a complete 3-axis acceleration measurement system. The user then sets the signal bandwidth of the device by adding a capacitor. The fixed plates are driven by 180° out-of-phase square waves. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces. or vibration.

Y. Capacitors must be added at these pins to imple-ment low-pass filtering for antialiasing and noise reduction. vibrometers. Setting The Bandwidth Using Cx. and computer hard disc drivers. Z) The tolerance of the internal resistor (RFILT) typically varies as much as ±15% of its nominal value (32 kΩ). And Cz : The ADXL335 has provisions for band limiting the XOUT. and vibration monitoring. there is no quantization error or nonmonotonic behavior. and scientific applications including inertial navigation. tilt sensing. A disk drive employs an accelerometer to detect disturbances affecting an actuator arm while attempting to maintain a head over a centreline of a track.0047 μF for CX. YOUT. Cy.6 Applications of Accelerometer Sensor:        Tilt-sensing applications Mobile devices Gaming systems Disk drive protection Image stabilization Sports and health devices Accelerometers have uses in many commercial. and CZ is recommended in all cases. and temperature hysteresis is very low (typically less than 3 m g over the −25°C to +70°C temperature range). As a result.36 Performance : Rather than using additional temperature compensation circuit. Z)) or more simply F–3 dB = 5 μF/C(X. Y. platform stabilization. vehicle air bag systems. smart detonation systems for bombs and missiles and machine vibration monitors. 7. A minimum capacitance of 0. ride comfort control. vehicular safety systems such as airbags. military. CY. . anti-lock brake systems (ABS).  Accelerometers find use in automobile suspension systems. innovative design techniques ensure that high performance is built in to the ADXL335. The equation for the 3 dB bandwidth is F−3 dB = 1/(2π(32 kΩ) × C(X. The output of the accelerometer is used as a feed-forward compensation signal in a servo control system to effectively reject the disturbance. and the bandwidth varies accordingly. and ZOUT pins.

such as a car. to monitor the forces being applied to an apparatus or device. bus. Accelerometers are widely used to monitor the vibration of electrical motors. For those that do there is a 400 kbit fastmode and since 1998 . fast mode plus a transfer rate between this has been specified. and the like. The original communication speed was defined with a maximum of 100 kbit per second and many applications don't require faster transmissions.37  Accelerometers have been employed to help determine the acceleration or deceleration of a ship or plane. pumps and the like in industrial applications. accelerometers may be deployed in wire line applications. accelerometers are often used in seismic applications to gather seismic data. provide an  advance warning of problems such as excessive wear or an approaching bearing failure. 7. particularly in rotating machinery. especially in continuous production operations.a high speed 3. Recently. In the area of oilfield investigation and earth formation characterization.7 I2C BUS: The I2C bus was designed by Philips in the early '80s to allow easy communication between components which reside on the same circuit board.4 Mbits option available. The accelerometer is placed within the implantable medical device.  An accelerometer can measure changes in a patient's physical activity. The name I2C translates into "Inter IC".   Accelerometers are used as a GPS-aid to obtain position information when the GPS receivers lose their line-of-sight with the satellites. Electromechanical accelerometers have been used in washing machines to detect an unbalanced load by sensing the sharp accelerations and decelerations of the spinning tub as it rocks back and forth. In particular. Changes in vibration levels. logging while drilling applications or using coiled tubing.   Accelerometers are also used to detect and record environmental data. Philips Semiconductors migrated to NXP in 2006. train. Sometimes the bus is called IIC or I²C bus. . The physical changes are detected by the accelerometer and algorithmically interpreted by circuitry within the pulse generator to produce a modified therapy that is correct for the current activity level.

Most significant features include:   Only two bus lines are required No strict baud rate requirements like for instance with RS232. Simplicity and flexibility are key characteristics that make this bus attractive to many applications. but also to connect components which are linked via cable.3 : Pin Configuration of IC 8591 . the master generates a bus clock  Simple master/slave relationships exist between all components Each device connected to the bus is software-addressable by a unique address  I2C is a true multi-master bus providing arbitration and collision detection 7.1 FEATURES OF I2C BUS:             Single power supply Operating supply voltage 2.5 V to 6 V Low standby current Serial input/output via I2C-bus Address by 3 hardware address pins Sampling rate given by I2C-bus speed 4 analog inputs programmable as single-ended or Differential inputs Auto-incremented channel selection Analog voltage range from VSS to VDD On-chip track and hold circuit 8-bit successive approximation A/D conversion Multiplying DAC with one analog output.7. Figure 7.38 I2C is not only used on single boards.

The selection of a non-existing input channel results in the highest available channel number being allocated. control and data to and from the device are transferred serially via the two-line bidirectional I2C-busThe maximum conversion rate is given by the maximum speed of the I2C-bus. This allows the internal oscillator to run continuously. Three address pins A0. The upper nibble of the control register is used for enabling the analog output.4 : Address Byte in I2C 7. single-supply low power 8-bit CMOS data acquisition device with four analog inputs.7. The lower nibble selects one of the analog input channels defined by the upper nibble. The programmable part must be set according to the address pins A0. The address always has to be sent as the first byte after the start condition in the I2C-bus protocol.2 GENERAL DESCRIPTION OF PCF8591: The PCF8591 is a single-chip. A1 and A2. Address. The last bit of the address byte is the read/writebit which sets the direction of the following data transfer. A1 and A2 are used for programming the hardware address.7. The most significant bits of both nibbles are reserved for future functions and have to be set to 0. The analog output enable flag may be reset at other times to reduce quiescent power consumption. If the auto-increment mode is desired in applications where the internal oscillator is used. thereby preventing conversion errors resulting from oscillator start-up delay. and for programming the analog inputs as single-ended or differential inputs. one analog output and a serial I2C-bus interface. 7. Fig 7. allowing the use of up to eight devices connected to the I2C-bus without additional hardware. If the autoincrement flag is set the channel number is incremented automatically after each A/D conversion. The D/A converter and the oscillator are disabled for power saving. the next selected channel will be always channel 0. if the auto-increment flag is set.7. After a Power-on reset condition all bits of the control register are reset to 0. The address consists of a fixed part and a programmable part.39 7. the analog output enable flag in the control byte (bit 6) should be set. Therefore. The analog output is switched to a highimpedance state.3 Addressing: Each PCF8591 device in an I2C-bus system is activated by sending a valid address to the device. .4 Control byte: The second byte sent to a PCF8591 device will be stored in its control register and is required to control the device function.

. Inc. as well as the family of CPLDs. simulate a design's reaction to different stimuli. examine RTL diagrams. (NASDAQ: XLNX) is a supplier of programmable logic devices. The low-cost Spartan™ family of FPGAs is fully supported by this edition.S. It is known for inventing the field programmable gate array (FPGA) and as the first semiconductor company with a fabless manufacturing model. Singapore. This edition provides synthesis and programming for a limited number of Xilinx devices.3 VHDL: VHDL (VHSIC hardware description language ) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field- programmable gate arrays and integrated circuits. which is free and can be renewed an unlimited number of times. Ireland.1 Xilinx SOFTWARE : Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL designs. Japan. The 12. 8.02 GB. Xilinx.A. The company has corporate offices throughout North America. and Tokyo. the company is headquartered in San Jose. Dublin. perform timing analysis. In particular devices with lots of I/O and huge gate matrix are disabled. California. Founded in Silicon Valley in 1984. 8. and configure the target device with the programmer. meaning small developers and educational institutions have no overheads from the cost of development software.2 version released in 2010-07-23 has a size of 3. Asia and Europe.40 CHAPTER 8 DESIGN OF SYSTEM SOFTWARE 8. which enables the developer to synthesize ("compile") their designs. U.2 XilinX Web Edition: The Web Edition is a free version of Xilinx ISE that can be downloaded or delivered by mail for free.. License registration is required to use the Web Edition of Xilinx ISE.

4 Design Flow in VHDL : Figure 8. This collection of simulation models is commonly called a testbench. and can be used as a general-purpose language for text processing. there are many features of VHDL which are not found in Ada. VHDL also allows arrays to be indexed in either ascending or descending direction. VHDL is strongly typed and is not case sensitive. VHDL has constructs to handle the parallelism inherent in hardware designs.1 Design Flow in VHDL VHDL is commonly used to write text models that describe a logic circuit.41 8. but files are more commonly used by a simulation testbench for stimulus or . VHDL has file input and output capabilities. but these constructs (processes) differ in syntax from the parallel constructs in Ada ( tasks). Such a model is processed by a synthesis program. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. whereas in Ada and most programming languages only ascending indexing is available. In order to directly represent operations which are common in hardware. both conventions are used in hardware. such as an extended set of Boolean operators including nand and nor. only if it is part of the logic design. Like Ada.

Type tutorial in the Project Name field. 3. To generate an appropriate testbench for a particular circuit or VHDL code. and to compare results with those expected. it might be possible to use VHDL to write a testbench to verify the functionality of the design using files on the host computer to define stimuli. To create a new project: 1. 5. a loop process or an iterative statement is required. In this case.42 verification data.5 Creating a New project: Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board.. A tutorial subdirectory is created automatically. for clock input. the inputs have to be defined correctly. rather than the VHDL code being "executed" as if on some form of a processor chip. One particular pitfall is the accidental production of transparent latches rather than D-type flip-flops as storage elements. Click Next to move to the device properties page. After that. Fill in the properties in the table as shown below: ♦ Product Category: All . the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. 8. Altera Quartus. For example. and then it is the actual hardware being configured. Enter or browse to a location (directory path) for the new project. 4. 2. It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device. There are some VHDL compilers which build executable binaries. Select File > New Project.. A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA. most designers leave this job to the simulator. or is too large to be practical. One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx ISE. Verify that HDL is selected from the Top-Level Source Type list. Synopsys Synplify or Mentor Graphics HDL Designer) to produce the RTL schematic of the desired circuit. 6. However. The New Project Wizard appears. to interact with the user.

STD_LOGIC_UNSIGNED. led :out std_logic_vector(7 downto 0)). txd : out std_logic.x"06". .x"0c". use IEEE.ALL. end gsm_msg.x"80"). rxd1:in std_logic. rxd :in std_logic. entity gsm_msg is Port (clk : in std_logic. sclk : out std_logic. commands - -- LCD . diow : out std_logic. 8. architecture Behavioral of gsm_msg is type main1 is array(1 to 5) of std_logic_vector(7 downto 0). rs : out std_logic.ALL.ALL. signal state1:main1:=(x"38".---LCD cs : out std_logic.STD_LOGIC_1164. use IEEE. sda:inout std_logic.STD_LOGIC_ARITH.6 Program: --Project describes that SMS based device control --System Clock is 20 Mhz library IEEE.x"01".43 ♦ Family: Spartan3 ♦ Device: XC3S200 ♦ Package: FT256 ♦ Speed Grade: -4 ♦ Top-Level Source Type: HDL ♦ Synthesis Tool: XST (VHDL/Verilog) ♦ Simulator: ISE Simulator (VHDL/Verilog) ♦ Preferred Language: Verilog (or VHDL) ♦ Verify that Enable Enhanced Design Summary is selected. use IEEE. d : inout std_logic_vector(7 downto 0).

sign4 : std_logic_vector(25 downto 0) := "00000000000000000000000000".k5.del1.j1. type pcf is(set1.x"5f". signal data_disp2:data2:=( x"20". signal div_state : main_div. signal data_disp1:data1:=(x"56".x"20").s3.lcd6.x"20". signal state3:main3:=(x"61".x"53".j.x"72".system type rec_data is array (1 to 3) of std_logic_vector(7 downto 0).x"20".p. signal rx_buff : rec_data.adc_fb3: integer := 0.x"63". signal adc:pcf.x"5f".x"6c".k4. signal i:integer:=7.s4.x"20"). div1. signal state_lcd:main_lcd.x"63".x"69".x"61".x"20". type main_adc is (s1.p1.x"20".x"61".x"20".x"20". signal k1.44 type main3 is array(1 to 13) of std_logic_vector(7 downto 0).mul.x"3a".x"6e". ---. -.lcd3.s5).s2. --(1 0 0 1 A2 A1 A0 W) ADDRESS BYTE(for write W=0) constant a_byte_r:std_logic_vector(7 downto 0):="10010001". --CONTROL BYTE0 .x"73". signal sign1 : std_logic_vector(25 downto 0) := "00000000000000000000000000".x"69".x"68".g.s4).adc_fb. signal sig:std_logic_vector(4 downto 0). signal adc_out_int. s2).s3.lcd4.write1. --(1 0 0 1 A2 A1 A0 R) ADDRESS BYTE (for read R=1) constant c0_byte:std_logic_vector(7 downto 0) :="01000100".x"74". signal sign.k2. i1.lcd5.store Rx data type main_lcd is (s1.adc_fb1. ---.x"6d".x"65".x"65".x"3a".x"54".x"78". constant a_byte_w:std_logic_vector(7 downto 0):="10010000".lcd7.x"67").m:integer:=1.lcd8 : std_logic_vector(7 downto 0):=x"20".x"79". x"79".k3.adc_fb2. signal lcd1.vehicle tracking type data2 is array(1 to 11) of std_logic_vector(7 downto 0).x"6b ". signal state_adc:main_adc. lcd2.x"20".x"20".read1. type main_div is (s1.x"65".del. --a_x: a_y: (for lcd) type data1 is array(1 to 16) of std_logic_vector(7 downto 0).s2.division_255).

x"20". --Receive msg(device) --CONTROL BYTE1 --CONTROL BYTE2 --CONTROL BYTE3 .x"65".x"20".x"2c".x"31".x"52".x"31".x"2B".x"0a").x"0a").x"36".x"31".x"34". x"39". x"35". x"35". constant gsm_msg : gsm_msg_no := ( x"41".x"20".x"20". --AT+CMGD=1.x"20". -.x"47".x"4D".x"20".x"36".x"76". constant c2_byte:std_logic_vector(7 downto 0) :="01000110".x"44". constant gsm_cmd : gsm_command := x"41".x"69".x"54". x"0A").x"0a".x"3d".x"3d".x"20".x"53".x"0d".x"2B". x"22".x"43". x"54".x"4d".x"0d". x"36". --AT(Enter) type gsm_command is array (1 to 11) of std_logic_vector(7 downto 0).x"39". x"2B". constant gsm_del : gsm_delete := ( x"41".x"4D".sig_f3 : std_logic_vector(1 downto 0). signal disp_data_rx : disp.x"0d".sig_f1.x"63". constant gsm_cmd_id : gsm_command_id := ( x"41".x"2B".x"0d". x"30". signal div:std_logic_vector(15 downto 0).x" 65".x"43".x"43".Device is controlled type disp is array (53 to 79) of std_logic_vector(7 downto 0).x"54".45 constant c1_byte:std_logic_vector(7 downto 0) :="01000101".x"4D".x"46".sig_f2.x"0d". --AT+CMGF=1(Enter) type gsm_command_id is array (1 to 11) of std_logic_vector(7 downto 0).x"3d".x"54".x"20".x"20".x"20". x"35".x"0D".x"20".x"20".x"1a". x"30". signal sig_f5:std_logic_vector(5 downto 0):=(others =>'0').x"3d".x"20". signal clkdiv:std_logic.x"0d".x"20". signal flag_s :std_logic_vector(5 downto 0):="000000". ------------------------------gsm module---------------------------------------------type gsm_command_in is array (1 to 4) of std_logic_vector(7 downto 0). --AT+CMGR=1(Enter) type gsm_delete is array (1 to 13) of std_logic_vector(7 downto 0). signal sig_f.x"47".x"0a").x"44". constant gsm_cmd_in : gsm_command_in := ( x"41".x"47".x"0a"). --AT+CMGS="9566559600"Enter [To send Msg] type gsm_reply is array (1 to 29) of std_logic_vector(7 downto 0).x"20".x"43".x"20".x"54".4(Enter) type gsm_msg_no is array (1 to 22) of std_logic_vector(7 downto 0). constant gsm_ack : gsm_reply :=(x"20". constant c3_byte:std_logic_vector(7 downto 0) :="01000111".x"47".x"22".x"20".x"0a").

x"49".x"45".x"68".x"20".x"3a".x"20".x"20".x"3a".x"20".x"0d".x"45".s7.x"20".x"3a".x"0a".x"20".x"20".x"20".x"64". ---------------------------------gps module---------------------------------------------------------------------type main3_g is array(1 to 107) of std_logic_vector(7 downto 0).x"47".x"0d".s5.x"65".x"6c".x"3a".shift1 : std_logic_vector(7 downto 0).x"0d".x"49".x"20".x"0d".x"54". signal t1 : integer := 5.x"20".x"45".x"0d".s10. signal bitcnt_txx : std_logic_vector(3 downto 0) := (others => '0').x"20".x"63".s9.x"20".x"20".s1.flag1 : std_logic.s4. signal baud_clk: std_logic . signal d11 : integer := 55.x"20" .x"4c".x"3a".x"3a".x"0d".x"20". signal delay : std_logic_vector(11 downto 0) := (others => '0'). x"20".x"0d". signal lt1 : integer := 18.x"20".x"20".x"0a".x"20".x"20" .x"1a".x"44". x"3a".x"65". x"20".x"20".x"1a".x"20".x"20". --Receive +CMT (for check) type main_g is (s0.d1.x"20".x"44".x"3a".x"20".x"20" .x"20".x"20".x"20".x"20".x"54".x"20".x"20". constant cntone : std_logic_vector(3 downto 0) := "0001".x"20". x"54".x"20".x"20".x"20". ---TIME : .x"20".x"3a".x"20".x"0a".x"47". signal state3_g1 : main3_g1:= (x"20".x"69".x"20".x"20".x"63". signal buff_tx : std_logic_vector(7 downto 0) := (others => '0').x"20".x"20".x"0a".x"49". signal state_g:main_g.x"3a".x"20".x"20".x"20".x"20".x"4c".x"20".x"69".x"20 ".x"20".x"20".x"20".x"20".x"20".x"0a").x"20 ".x"4c".x"20".x"0a".x"54".x"4d".x"20".x"0d".x"0a".x"20". signal lg1 : integer := 30.x"63".x"4d".x"20".x"20".x"49". signal state3_g : main3_g := ( x"20".x"20".x"20".x"6e".x"20".x"20". signal bitcnt_rx1 : std_logic_vector(4 downto 0) := (others => '0'). signal t.s12.x"20".x"20".x"20".x"20".s11.x"41".x"20".x"74".lt.x"0d".x"20".x"20".x"20".x"3a".x"45".46 type ready is array (1 to 7) of std_logic_vector(7 downto 0). .lcd_delay :integer := 1.x"20".x"20". signal bitcnt_tx : std_logic_vector(3 downto 0) := (others => '0').x"20".x"4c".x"0d". signal bitcnt_rx : std_logic_vector(3 downto 0) := (others => '0'). x"54".ack.x"0d".x"64".x"2 0".x"54".x"41".x"20".x"20" .x"20".s8.x"20".x"20".x"20". signal ready_data_rx : ready.x"20".x"65".x"20".x"20".x"0a".x"20". signal shift. data_t.x"0a".lg.x"20".x"20".x"20".x"54".x"20".x"0a".x"0d".x"51".x"20".x"3a".x"20".x"20".x"20".s3.x"49".x"41".x"3a".x"56".x"20".x"20". signal flag_enable.x"49".x"20".time_delay.x"20".x"20".x"20".x"0a").x"54".x"65".x"41".x"20".s2.x"0a".x"20".x"20".x"41".x"3a".x"20". x"20".x"20".x"20".x"20".x"20".x"3a".x"20".x"20".x"51".x"20".x"20".x"20".x"3a".x"54".x"20".x"20" .x"20".x"54".s6.s13).- type main3_g1 is array(1 to 107) of std_logic_vector(7 downto 0).

begin if clkdiv'event and clkdiv='1' then case state_adc is .l.t_4. --------------------------------.l6. when "10" => clkdiv <= '0'.Temp value read process ------------------------------------------------------process(clkdiv) variable j.t_2. end if. signal data_time : main_time.l5. type main_lt is array (1 to 14) of std_logic_vector(7 downto 0).t_3. type main_d is array (1 to 12) of std_logic_vector(7 downto 0). signal data_lt: main_lt. end process. case div(15 downto 14) is when "00" => clkdiv <= '1'. type main_time is array (1 to 12) of std_logic_vector(7 downto 0).n:std_logic_vector(7 downto 0):="00000000". type main_lg is array (1 to 15) of std_logic_vector(7 downto 0). signal data_d : main_d.l2.47 signal l1. type ready1 is array (1 to 73) of std_logic_vector(7 downto 0).data_rx : ready1.t_1.m. type main_tx is array (1 to 74) of std_logic_vector(7 downto 0). signal data_lg:main_lg. begin --------------------------------clock divider-----------------------------------------process(clk) begin if clk'event and clk='1' then div <= div + 1.l4. signal gps_rx. when others => end case.t_6:std_logic_vector(7 downto 0):= x"20".l3.t_5. signal buff1_tx : main_tx.

case sig(3 downto 0) is --START CONDITION FOR WRITE CONVERSION when "0000"=> sclk <='1'.1. when "0010" => sda <= '1'. --CONTROL BYTE OPERATION when "1001"=> sda <=c0_byte(i). end if.1. when "0100"=> sclk<='0'. sclk <='1'. when "0110" => sclk<='0'. else sig(3 downto 0)<="0111". --ADDRESS BYTE FOR WRITE OPERATION when "0101" => sda <=a_byte_w(i). when "1010"=> if i > 0 then i <= i . sclk<='1'. i <= 7. when "1000" => sclk <='0'. when "0011"=> sda <='0'. i <= 7. if i > 0 then i <= i . sig(3 downto 0)<="0101".48 when s1 => case adc is when set1 => sig<=sig+1. when "0111"=> --ACKNOWLEDGEMENT sclk<='1'. .

sclk<='1'. when "0100"=> sclk<='0'. sclk <='0'. . when "0010" => sda <= '1'. end if. else sig(3 downto 0)<="1011". when "1100" => sclk <='0'. i <= 7. else sig(3 downto 0)<="0111". i <= 7.1. when others => end case. sig <= (others => '0'). sig(3 downto 0)<="0101". when "0011"=> sda <='0'. when "1011"=> --ACKNOWLEDGEMENT sclk<='1'. when "1101" => adc<=write1. when "0110"=> if i > 0 then i <= i .49 sig(3 downto 0)<="1001". end if. --ADDRESS BYTE FOR READ OPERATION when "0101" => sda <=a_byte_r(i). ----------------------------------------------------START CONDITION FOR A/D CONVERSION when write1 => sig<=sig+1. i <= 7. case sig(3 downto 0) is when "0000"=> sclk <='1'.

when "0110" => .50 sclk<='0'. when "0111"=> --ACKNOWLEDGEMENT sda <='Z'. l:=l(6 downto 0) & sda. sclk<='1'. when others => end case. sig(3 downto 0)<="0000". when "1001" => adc<=read1. when "0101" => sclk <='0'. when "0100" => sda <='1'. sda <='Z'. when "0010" => sda <='0'. when "1000" => sclk <='0'. end if. else sig(3 downto 0)<="0010". sclk <='0'. when "0001" => if i > 0 then i <= i . --FOR EXAMPLE case sig(3 downto 0) is --sda=11110101 when "0000" => sclk<='1'. --A/D READ OPERATION when read1 => sig<=sig+1. when "0011" => sclk <='1'. i <= 7.1. sig <= (others => '0').

-Integer Value of Corresponding Digital data when "0111" => data(0 to FF) into (0 to 99) by ((data*99)/255) mul <= adc_out_int * 99. sig <= (others => '0'). end if. --0 to 99 conversion data(adc data) state_adc <= s2. adc <= set1. i1 <= i1 + 1. div_state<=s1.DIVISION UNIT (divisin by 255) case div_state is when s1 => if (mul >= 255) then mul <= mul . when others => end case. -. i1 <= 0. when s2 => adc_fb <= div1. div_state <= s1. when others => end case. else if (mul < 127) then div1 <= i1. when others => end case. div_state <= s2. div_state <= s2.255.converting the Digital when division_255 => -. adc <= division_255. ------------------------adc ch1-------------------------when s2 => . else div1 <= i1 + 1.51 adc_out_int <= conv_integer(l). end if.

when "0111"=> --ACKNOWLEDGEMENT sclk<='1'.1. when "0011"=> sda <='0'. sig(3 downto 0)<="0101". --COTNTROL BYTE OPERATION when "1001"=> sda <=c1_byte(i). sclk <='1'. when "1000" => sclk <='0'. i <= 7. when "0110" => sclk<='0'. sclk<='1'. case sig(3 downto 0) is --START CONDITION FOR WRITE CONVERSION when "0000"=> sclk <='1'. --ADDRESS BYTE FOR WRITE OPERATION when "0101" => sda <=a_byte_w(i). else sig(3 downto 0)<="0111". .1. when "0100"=> sclk<='0'.52 case adc is when set1 => sig<=sig+1. i <= 7. end if. if i > 0 then i <= i . when "0010" => sda <= '1'. when "1010"=> if i > 0 then i <= i .

end if. when "0011"=> sda <='0'. when "0010" => sda <= '1'. --ADDRESS BYTE FOR READ OPERATION when "0101" => sda <=a_byte_r(i). sclk<='1'. when "0110"=> if i > 0 then i <= i . sclk <='0'. when "1011"=> --ACKNOWLEDGEMENT sclk<='1'. i <= 7. end if. . when "1100" => sclk <='0'. when others => end case. when "0100"=> sclk<='0'. ----------------------------------------------------START CONDITION FOR A/D CONVERSION when write1 => sig<=sig+1. else sig(3 downto 0)<="1011". when "1101" => adc<=write1.53 sig(3 downto 0)<="1001". case sig(3 downto 0) is when "0000"=> sclk <='1'. i <= 7. sig <= (others => '0').1. else sig(3 downto 0)<="0111". i <= 7. sig(3 downto 0)<="0101".

sig <= (others => '0'). --FOR EXAMPLE case sig(3 downto 0) is --sda=11110101 when "0000" => sclk<='1'. i <= 7. sclk <='0'. sda <='Z'. when "0111"=> --ACKNOWLEDGEMENT sda <='Z'. when "0101" => sclk <='0'. when "0001" => if i > 0 then i <= i . --A/D READ OPERATION when read1 => sig<=sig+1. when "0100" => sda <='1'. sclk<='1'. when "0110" => . j:=j(6 downto 0) & sda. when "0011" => sclk <='1'. else sig(3 downto 0)<="0010".54 sclk<='0'. when "1000" => sclk <='0'. when others => end case. end if. sig(3 downto 0)<="0000". when "1001" => adc<=read1. when "0010" => sda <='0'.1.

end if. div_state <= s2. end process.55 adc_out_int <= conv_integer(j). when others => end case. else if (mul < 127) then div1 <= i1. div_state <= s2. else div1 <= i1 + 1. <= div1.DIVISION UNIT (division by 255) case div_state is when s1 => if (mul >= 255) then mul <= mul . -Integer Value of Corresponding Digital data when "0111" => data(0 to FF) into (0 to 99) by ((data*99)/255) mul <= adc_out_int * 99. end if. when others => end case. end if. div_state<=s1.converting the Digital when division_255 => -. when others => end case. --0 to 99 conversion process(clk) . i1 <= 0. i1 <= i1 + 1. adc <= division_255. adc <= set1.255. when s2 => adc_fb1 data(adc data) state_adc<= s1. -. sig <= (others => '0'). div_state <= s1.

h4 := 0. begin if (clk'event and clk = '1') then sig_f1 <= sig_f1 + 1. when "01" => if (t2 >= 10) then h3 := h3 + 1. t2 := t2 . h4 : integer:=0. else h4 := t2. variable h31. end case. process(clk) variable t21 : integer := 0. variable h3. sig_f <= "10". begin if (clk'event and clk = '1') then sig_f <= sig_f + 1. end if. 8) + x"30". h41 : integer:=0. end if. h3 := 0. end process. --Display Control for ADC FeedBack when "10" => if h3>=0 and h3<=9 and h4>=0 and h4<=9 then lcd1 <= conv_std_logic_vector (h3.56 variable t2 : integer := 0. --Display Control for ADC FeedBack . case sig_f is when "00" => t2 := adc_fb. h31 := 0. when others => sig_f <= "00". --(For display the value in LCD (value + 30)) lcd2 <= conv_std_logic_vector (h4. 8) + x"30". sig_f <= "01". end if. case sig_f1 is when "00" => t21 := adc_fb1.10.

diow <= '0'.10. end if. else h41 := t21. sig_f1 <= "10". t21 := t21 . when others => sig_f1 <= "00". ---------------------------------------.LCD Display -------------------------------------------------process begin if clk'event and clk='1' then case state_lcd is when s1 => sign <= sign + 1. sig_f1 <= "01". 8) + x"30". end if. when "10" => if h31>=0 and h31<=9 and h41>=0 and h41<=9 then lcd3 <= conv_std_logic_vector (h31.57 h41 := 0. end case. end process. end if. --(For display the value in LCD (value + 30)) lcd4 <= conv_std_logic_vector (h41. if k1<=5 then sign(25 downto 20)<="000001". case sign(25 downto 20) is when "000000" => when "000001" => when "000010" => when "000011" => k1<=k1+1. d <= state1(k1). when "01" => if (t21 >= 10) then h31 := h31 + 1. cs <= '1'. . --(lcd command) rs <= '0'. cs <= '0'. 8) + x"30".

sign(25 downto 20)<="010000". <= x"c0". when "001000" => when "001001" => rs <= '0'. k3<=k3+1. cs <= '0'. rs <= '1'.58 else sign(25 downto 20)<="001000". end if. ---lcd secondline display when "001010" => when "001011" => when "001100" => when "001101" => when "001110" => when "001111" => k2<=k2+1. ---lcd secondline display ----lcd display of title d <= data_disp2(k3). diow <= '0'. if k2<16 then else cs <= '1'. cs <= '0'. d <= x"80". k2 <= 1. cs <= '0'. end if. when "010110" => cs <= '1'. . ------(temperature) --------lcd display of title sign(25 downto 20)<="001101". when "010000" => rs <= '0'. k3 <= 1. if k3<11 then sign(25 downto 20)<="010101". when "010001" => d when "010010" => when "010011" => when "010100" => when "010101" => cs <= '1'. when "010111" => cs <= '0'. else sign(25 downto 20)<="011000". rs <= '1'. d <= data_disp1(k2). diow <= '0'. cs <= '1'.

--(lcd command) rs <= '0'. else sign(25 downto 20)<="010000". rs <= '1'. diow <= '0'. diow <= '0'. case sign(25 downto 20) is when "000000" => when "000001" => when "000010" => when "000011" => k1<=k1+1. d <= state3(k2). cs <= '0'. when "001111" => cs <= '0'. d <= x"80". k1<=1. when "001010" => when "001011" => when "001100" => when "001101" => cs <= '1'. if k1<=5 then sign(25 downto 20)<="000001". end if. cs <= '0'. d <= state1(k1). cs <= '1'. else sign(25 downto 20)<="001000". ---------------------------------------------------------------------------------when s2 => sign <= sign + 1. state_lcd<= s2. k2 <= 1. when others => end case. when "001110" => cs <= '1'. . k2<=k2+1. end if.59 k1<=1. if k2<13 then sign(25 downto 20)<="001101". when "001000" => when "001001" => rs <= '0'.

when "001001" => cs <= '1'. when "000010" => cs <= '1'. when "000110" => cs <= '1'. when "000011" => cs <= '0'. when "001000" => d <= lcd2. when "000100" => rs <= '1'. when others => --Temperature Value .60 state_lcd<= s3. case sign1(25 downto 20) is when "000000" => rs <= '0'. end if. ----------------------------------------------------------when s3 => sign1<=sign1+1. diow <= '0'. when "000111" => cs <= '0'. when "000110" => cs <= '1'. end case. diow <= '0'. when "000010" => cs <= '1'. when "000 111" => cs <= '0'. when "000101" => d <= lcd1. when "000101" => d <= lcd3. case sign1(25 downto 20) is when "000000" => rs <= '0'. when others => end case. --Temperature Value when s4 => sign1<=sign1+1. when "001011"=> sign1(25 downto 20)<="000000". when "001000" => d <= lcd4. when "000100" => rs <= '1'. state_lcd <= s3. when "000001" => d <= x"8b". when "001010" => cs <= '0'. when "001010" => cs <= '0'. when "001011"=> state_lcd <= s4. when "000001" => d <= x"84". when others => sign1(25 downto 20)<="000000". when "000011" => cs <= '0'. when "001001" => cs <= '1'.

end process. when "010000010010" => -. case delay is when "000000000000" => -. end if. case flag_s(2 downto 0) is when "000" => if ( adc_fb>=32 and adc_fb<=34 and adc_fb1>=39 and adc_fb1<=40) then and adc_fb2>=33 and adc_fb2<=34 ) then flag_enable <= '0'. end if. end process.0 baud_clk <= '1'. when "100000100100" => -. delay <= (others => '0'). end if. ----------------------------------------------------------------------------------process(clk) begin if rising_edge(clk) then delay <= delay + 1. else flag_enable <= '1'. -- . flag_s(2 downto 0) <= "000".1042 baud_clk <= '0'. when others => end case.61 end case. ---------------------------flag_enable-----------------------------------process(clk) begin if (clk = '1' and clk'event) then flag_s <= flag_s + 1.2083 baud_clk <= '1'. when others => end case.

end if. when "01010"=> if (p<73) then bitcnt_rx1 <= "01100". end if. when "01001" => data_rx(p) <= shift1. bitcnt_rx1 <= "01010". when "01100"=> <= 1. else p bitcnt_rx1 <= "00000". else bitcnt_rx1 <= bitcnt_rx1 + cntone.62 when others => end case. when "00001" | "00010" | "00011" | "00100" | "00101" | "00110" | "00111" | "01000" => bitcnt_rx1 <= bitcnt_rx1 + cntone. process(baud_clk) begin if rising_edge(baud_clk) then ---------------------------------Receive GPS Data----------------------------------------case bitcnt_rx1 is when "00000" => if (RxD1 = '1') then -. bitcnt_rx1<= "00000". else p <= 1. end if. end process. end if. . if (p <73) then p <= p + 1.Start Bit bitcnt_rx1 <= "00000". shift1 <= RxD1 & shift1(7 downto 1).

end if. bitcnt_rx1 <= "00000". else p<= 1. else p<= 1. bitcnt_rx1<= "01111". bitcnt_rx1 <= "01110". ---$ else if (p<73)then p<=p+1. bitcnt_rx1 <= "00000". end if. when "01101"=> if (data_rx(p)=x"47") then ---G p<=p+1. led2<='1'. bitcnt_rx1 <= "01101". end if. when "01111"=> if (data_rx(p)=x"52") then ---R gps_rx(m)<=data_rx(p). m<=m+1. -- . when "01110" => if (data_rx(p)=x"50") then ---P p<=p+1. end if. led4<='1'. else p<= 1. bitcnt_rx1 <="01100". p<=p+1.63 if (data_rx(p)= x"24") then p<=p+1. bitcnt_rx1 <= "00000".

else p<= 1. m<=m+1. bitcnt_rx1 <= "00000". m<=m+1. end if. else p<= 1. when "10011" => data_time(t)<=gps_rx(t1). bitcnt_rx1<="10011". when "10010"=> gps_rx(m)<=data_rx(p). p<=p+1. if (p<73)then -------full data tx p<=p+1. when "10001"=> if (data_rx(p)=x"43") then ---c gps_rx(m)<=data_rx(p). bitcnt_rx1 <= "10010". m<=m+1. p<= 1. end if . when "10000"=> if (data_rx(p)=x"4D") then ----M gps_rx(m)<=data_rx(p). bitcnt_rx1 <= "00000". t<=1. bitcnt_rx1 <= "00000". else m<=1. end if.64 bitcnt_rx1 <= "10000". else p<= 1. end if. bitcnt_rx1 <= "10001". p<=p+1. . bitcnt_rx1 <= "10010".

bitcnt_rx1 <= "10011". -----date . bitcnt_rx1 <= "10100". ------latitude if (lt1<=27)then lt1<=lt1+1. else lt1<=18. end if . when "10100" => data_lt(lt)<=gps_rx(lt1). p<= 1. lt<=1. else lg1<=30. if (lg1<=40)then ----longitude lg1<=lg1+1. bitcnt_rx1<="10110". bitcnt_rx1<="10100". lg<=lg+1. t<=t+1. when "10110" => data_d(d1)<=gps_rx(d11). else t1<=5. p<= 1. bitcnt_rx1 <= "10101". lg<=1.65 -----time if (t1<=10)then t1<=t1+1. when "10101" => data_lg(lg)<=gps_rx(lg1). bitcnt_rx1<="10101". end if . end if . p<= 1. lt<=lt+1. t<=1.

d1<=d1+1. g <= 1.66 if (d11<=60)then d11<=d11+1.d11<=55. p<= 1. ----------------------------------------------process(baud_clk) begin if rising_edge(baud_clk) then case state_g is when s0 => case bitcnt_tx is when "0000" => led <= x"00". p<= 1. bitcnt_rx1 <= "10110". shift1 <= (others => '0'). else d11<=55 . bitcnt_rx1<="10111". when "10111"=> if (del1 <=3000) then del1 <= del1 + 1 .lg<=1. end process. t1<=5. end if.d1<=1. j <= 1. when others => end case. t<=1. end if. . else m<=1.lg1<=30. bitcnt_rx1<="10111". bitcnt_rx1<="00000".lt<=1. end if .lt1<=17. d1<=1.

else del <= 1. bitcnt_tx <= "1100". j <= j + 1. end if. when others => end case. bitcnt_tx <= "0001". when "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" => bitcnt_tx <= bitcnt_tx + cntone. when "1100" => bitcnt_tx <= "1100". when "0001" => buff_tx <= gsm_cmd_in(g). bitcnt_tx <= bitcnt_tx + cntone. else j <= 1. buff_tx <= '1' & buff_tx(7 downto 1). del <= del + 1. if (g < 4) then g <= g + 1. bitcnt_tx <= "0001". end if. when "1011" => if (j < 1) then if (del <= 10000) then bitcnt_tx <= "1011". end if. when s1 => if (del <= 30000) then ---AT setting . txd <= '0'. state_g <= s1. txd <= buff_tx(0).67 del <= 1. bitcnt_tx <= bitcnt_tx + cntone. when "1010" => txd <= '1'. else bitcnt_tx <= "1011". g <= 1.

<= 1. --text mode set txd <= '0'. txd <= buff_tx(0). end if.68 del else bitcnt_tx <= "0000". <= 1. when "1011" => if (j < 1) then if (del <= 0000) then bitcnt_tx <= "1011". bitcnt_tx <= "0001". buff_tx <= (others => '0'). end if. . bitcnt_tx <= bitcnt_tx + cntone. else bitcnt_tx <= "1011". when s2 => case bitcnt_tx is when "0000" => led <= x"01". del <= 1. bitcnt_tx <= bitcnt_tx + cntone. j <= 1. if (g < 11) then g <= g + 1. when "1010" => txd <= '1'. when "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" => bitcnt_tx <= bitcnt_tx + cntone. g <= 1. else del <= 1. when "0001" => buff_tx <= gsm_cmd(g). del <= del + 1. g <= 1. state_g <= s2. g j del <= 1. buff_tx <= '1' & buff_tx(7 downto 1). <= del + 1.

end if. when s4 => case bitcnt_tx is when "0000" => led <= x"0d" . shift <= (others => '0').69 j <= j + 1. else bitcnt_rx <= "0000". bitcnt_tx <= "0000". del <= 1. when "1100" => bitcnt_tx <= "1100". del <= 1. ----AT+CMGD=1. disp_data_rx <= (others => (others => '0')). end if. all msg deleting . ready_data_rx <= (others => (others => '0')). when s3 => if (del <= 30000) then del <= del + 1. else j <= 1. buff_tx <= (others => '0'). state_g <= s4. bitcnt_tx <= bitcnt_tx + cntone. state_g <= s3. g <= 1. p1 <= 1.. when "0001" => buff_tx <= gsm_del(g)..4.. bitcnt_tx <= "0001". j <= 1. j <= 1. when others => end case. bitcnt_tx <= "1100". end if. g <= 1.

when "0010" | "0011" | "0100" |"0101" | "0110" | "0111" | "1000" | "1001" => bitcnt_tx <= bitcnt_tx + cntone. else bitcnt_rx <= "0000". bitcnt_tx <= "1100". end if. if (g < 13) then g <= g + 1.70 txd <= '0'. del <= del + 1. bitcnt_tx <= bitcnt_tx + cntone. txd <= buff_tx(0). j <= j + 1. else g <= 1. bitcnt_tx <= "0001". end if. . when s5 => if (del <= 30000) then del <= del + 1. bitcnt_tx <= "1011". else j <= 1. when "1010" => txd <= '1'. when "1100" => bitcnt_tx <= "1100". when others => end case. state_g <= s5. buff_tx <= '1' & buff_tx(7 downto 1). end if. bitcnt_tx <= "0001". when "1011" => if (j < 1) then if (del <= 10000) then bitcnt_tx <= "1011". bitcnt_tx <= "0000". else del <= 1.

when "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" => bitcnt_rx <= bitcnt_rx + cntone. shift <= (others => '0'). p1 <= 1 .1 receiving when s6 => case bitcnt_rx is when "0000" => led <= x"02" . end if. state_g<=s9.71 disp_data_rx <= (others => (others => '0')). shift <= RxD & shift(7 downto 1). when "1001" => if (RxD = '1') then bitcnt_rx <= "1001". p1 <= p1 + 1. ------------send msg at this time------------+CMTI : "SM". else flag1<='0'. state_g <= s6. j <= 1. if (RxD = '1') then -. ready_data_rx <= (others => (others => '0')). del <= 1. else bitcnt_rx <= "1010". .Stop Bit flag1<='1'. bitcnt_tx<="0000". bitcnt_rx <= bitcnt_rx + cntone. end if. p1 <= 1. else if (p1 < 7) then bitcnt_rx <= "0001". g <= 1. buff_tx <= (others => '0').

when others => end case. p1 <= 1. when "0001" => buff_tx <= gsm_cmd_id(g). end if. p1 <= 1. . bitcnt_tx <= "0000".AT+CMGR=1 sending case bitcnt_tx is when "0000" => led <= x"04" . bitcnt_tx <= "0000". state_g <= s7. end if. j <= 1. txd <= '0'. shift<= (others => '0'). when "1010" => if ((ready_data_rx(3) = x"2b") and (ready_data_rx(4) = x"43") and (ready_data_rx(5) = x"4d") and (ready_data_rx(6) = x"54")) then led <= x"03" . end if. g <= 1. bitcnt_rx <= "1010". end if. else led <= x"0f" . if (p1 < 7) then ready_data_rx(p1) <= shift. bitcnt_tx <= bitcnt_tx + cntone. if (del <= 70000) then del <= del + 1.72 end if. else state_g <= s7. ready_data_rx <= (others => (others => '0')). when s7 => ----. ready_data_rx <= (others => (others => '0')). bitcnt_rx <= "0000". del <= 1.

else del <= 1. led<=x"08".73 bitcnt_tx <= bitcnt_tx + cntone. else bitcnt_rx <= bitcnt_rx + cntone. -- -. end if. if (RxD = '1') then bitcnt_rx <= "0000". when others => end case. bitcnt_tx <= "0001". txd <= buff_tx(0). end if. ----. bitcnt_rx<="0000". when "1100" => bitcnt_tx <= "1100". else j<= 1. del <= del + 1. bitcnt_tx <= "1011". j <= j + 1. when "1011" => if (j < 1) then if (del <= 10000) then bitcnt_tx <= "1011". bitcnt_tx <= "1100". when "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" => bitcnt_tx <= bitcnt_tx + cntone. end if. end if. if (g < 11) then g <= g + 1.AT+CMGR=1 RECEIVING case bitcnt_rx is when "0000" => led<=x"07". buff_tx <= '1' & buff_tx(7 downto 1).Stop Bit . else g <= 1. bitcnt_tx <= "0001". when "1010" => txd <= '1'.

if (j < 1) then if (del <= 50000) then bitcnt_rx <= "1011". else del <= 1. bitcnt_rx <= "0001". . del <= del + 1. end if. j <= j + 1. -. end if. if (p1 <78 ) then p1 <= p1 + 1. when "1011" => if ((disp_data_rx(75) = x"4c") and (disp_data_rx(76) = x"6f") and (disp_data_rx(77) = x"63") and (disp_data_rx(78) = x"74")) then led <= x"05" . led <= x"CC". shift <= RxD & shift(7 downto 1). bitcnt_rx <= "1011". bitcnt_rx <= "1100".motor on ack <= '1'.74 when "0001" | "0010" | "0011" |"0100" | "0101" | "0110" | "0111" | "1000" => bitcnt_rx <= bitcnt_rx + cntone. end if. when others => end case. state_g <= s8. else j <= 1. end if. when "1001" => if (p1 >=75) then disp_data_rx(p1) <= shift. when "1100" => bitcnt_rx <= "1100". bitcnt_rx <= "0000". end if. else ack <= '0'. else p1 <= 1.

. end if. else bitcnt_rx <= "0000". g <= 1. end if. bitcnt_rx <= "0000". bitcnt_tx <="0001". end if. j <= 1. del <= 1. bitcnt_tx <="0001". bitcnt_tx <= "0000". ready_data_rx <= (others => (others => '0')). when s9 => led <= x"06". buff_tx <= (others => '0'). else state_g<=s6.75 when s8 => if (del <= 30000) then del <= del + 1. shift <= (others => '0'). when "0001" => buff_tx <= gsm_msg(g). elsif (flag_enable ='1') then flag1 <='0'. case bitcnt_tx is when "0000" => if( ack= '1') then flag1 <='0'. disp_data_rx <= (others => (others => '0')). p1 <= 1. state_g <= s9. del<=1. else if( flag1 ='0') then state_g <= s11.

76 txd <= '0'; bitcnt_tx <= bitcnt_tx + cntone; when "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" => bitcnt_tx <= bitcnt_tx + cntone; txd <= buff_tx(0); buff_tx <= '1' & buff_tx(7 downto 1); when "1010" => txd <= '1'; if (g < 22) then g <= g + 1; bitcnt_tx <= "0001"; else bitcnt_tx <= "1011"; g <= 1; end if; when "1011" => if (j < 1) then if (del <= 50000) then bitcnt_tx <= "1011"; del <= del + 1; else del <= 1; j <= j + 1; bitcnt_tx <= "0001"; end if; else j <= 1; bitcnt_tx <= "1100"; end if; when "1100" => bitcnt_tx <= "1100"; state_g <= s10; when others => end case;

when s10=> case bitcnt_txx is when "0000" => g <= 1; j <= 1; del <= 1; bitcnt_txx <= bitcnt_txx + cntone; when "0001"=>

77 if (ack='1') then if (g = 17) then buff_tx <= l1; elsif (g = 18) then buff_tx <= l2; elsif (g = 20 ) then buff_tx <= l3; elsif (g = 21) then buff_tx <= l4; elsif (g = 23) then buff_tx <= l5; elsif (g = 24) then buff_tx <= l6; elsif (g = 35) then buff_tx elsif (g = 36) then buff_tx elsif (g = 38 ) then buff_tx elsif (g = 39) then buff_tx elsif (g = 41) then buff_tx elsif (g = 42) then buff_tx <= data_d(1); <= data_d(2); <= data_d(3); <= data_d(4); <= data_d(5); <= data_d(6);

elsif (g = 54) then buff_tx elsif (g = 55) then buff_tx elsif (g = 56 ) then buff_tx elsif (g = 57) then buff_tx elsif (g = 58) then buff_tx elsif (g = 59) then buff_tx elsif (g = 60) then buff_tx elsif (g = 61) then buff_tx elsif (g = 62) then buff_tx elsif (g = 63) then buff_tx elsif (g = 74) then buff_tx elsif (g = 75) then buff_tx elsif (g = 76) then buff_tx elsif (g = 77) then buff_tx elsif (g = 78) then buff_tx elsif (g = 79) then buff_tx elsif (g = 80) then buff_tx elsif (g = 81) then buff_tx elsif (g = 82) then buff_tx elsif (g = 83) then buff_tx else

<= data_lt(1); <= data_lt(2); <= data_lt(3); <= data_lt(4); <= data_lt(5); <= data_lt(6); <= data_lt(7); <= data_lt(8); <= data_lt(9); <= data_lt(10); <= data_lg(1); <= data_lg(2); <= data_lg(3); <= data_lg(4); <= data_lg(5); <= data_lg(6); <= data_lg(7); <= data_lg(8); <= data_lg(9); <= data_lg(10);

buff_tx <= state3_g1(g); end if; elsif( flag_enable ='1') then if (g = 17) then buff_tx <= l1;

78 elsif (g = 18) then buff_tx <= l2; elsif (g = 20 ) then buff_tx <= l3; elsif (g = 21) then buff_tx <= l4; elsif (g = 23) then buff_tx <= l5; elsif (g = 24) then buff_tx <= l6; elsif (g = 35) then buff_tx elsif (g = 36) then buff_tx elsif (g = 38 ) then buff_tx elsif (g = 39) then buff_tx elsif (g = 41) then buff_tx elsif (g = 42) then buff_tx <= data_d(1); <= data_d(2); <= data_d(3); <= data_d(4); <= data_d(5); <= data_d(6);

elsif (g = 54) then buff_tx elsif (g = 55) then buff_tx elsif (g = 56 ) then buff_tx elsif (g = 57) then buff_tx elsif (g = 58) then buff_tx elsif (g = 59) then buff_tx elsif (g = 60) then buff_tx elsif (g = 61) then buff_tx elsif (g = 62) then buff_tx elsif (g = 63) then buff_tx elsif (g = 74) then elsif (g = 75) then elsif (g = 76) then elsif (g = 77) then elsif (g = 78) then elsif (g = 79) then elsif (g = 80) then elsif (g = 81) then elsif (g = 82) then elsif (g = 83) then else buff_tx buff_tx buff_tx buff_tx buff_tx buff_tx buff_tx buff_tx buff_tx buff_tx

<= data_lt(1); <= data_lt(2); <= data_lt(3); <= data_lt(4); <= data_lt(5); <= data_lt(6); <= data_lt(7); <= data_lt(8); <= data_lt(9); <= data_lt(10); <= data_lg(1); <= data_lg(2); <= data_lg(3); <= data_lg(4); <= data_lg(5); <= data_lg(6); <= data_lg(7); <= data_lg(8); <= data_lg(9); <= data_lg(10);

buff_tx <= state3_g(g); end if; end if; bitcnt_txx <= bitcnt_txx + cntone; when "0010" => TxD <= '0'; bitcnt_txx <= bitcnt_txx + cntone;

bitcnt_txx <= "1110". del <= del + 1. TxD <= buff_tx(0). when "1110" => bitcnt_txx <= "1110". else g<= 1. state_g <= s11. j <= j + 1. bitcnt_txx <= "0001". end if. else del <= 1. end if. bitcnt_txx <= "1101". when "1100" => if g <107 then g <= g + 1. ack<='0'. buff_tx <= buff_tx(0) & buff_tx(7 downto 1). end if. when "1011" => TxD <= '1'. bitcnt_txx <= "0001". if (del <= 80000) then del <= del + 1. when s11 => led <= x"f0".79 when "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" | "1010" => bitcnt_txx <= bitcnt_txx + cntone. when others => end case. when "1101" => if (j < 1) then if (del <= 50000) then bitcnt_txx<= "1101". . else j <= 1. bitcnt_txx <= bitcnt_txx + cntone.

state_g <= s0. l5<= t_5 -6. else l6<=t_6. g <= 1. end if. when "000001" => ----------seconds--------if(t_6 >=x"30" and t_6<=x"39" and t_5>=x"30" and t_5<=x"35") then l6<=t_6. when others => end case.80 else bitcnt_tx <= "0000". end process. . l5<= t_5. case sig_f5 (5 downto 0) is when"000000" => t_1<= data_time(1)+0. t_6<= data_time(6)+0. t_4<= t_4+1. end if. sig_f5<="000001". j <= 1. del <= 1. t_2<= data_time(2)+5. t_3<= data_time(3)+3. bitcnt_txx<="0000". end if. -----------------------------------time convertion process----------------------process(clk) begin if clk'event and clk ='1' then sig_f5<=sig_f5+1. t_4<= data_time(4)+0. buff_tx <= (others => '0'). t_5<= data_time(5)+0.

t_2<= t_2+1. sig_f5 <="000100". sig_f5<="000011". else l4<= t_4. else l2<=t_2-4. elsif( t_2>=x"30" and t_2<=x"39" and t_1>=x"32") then if( t_2>=x"30" and t_2<=x"33" and t_1>=x"32") then l2<=t_2. end if. l1<=t_1. end if. l3<= t_3. end if. else l2<=t_2-10. . when "000100" => if(time_delay <= 5000) then time_delay <= time_delay+1. sig_f5<="000100". l3<= t_3 -6. l1<= t_1+1. when "000011" => -if(t_2>=x"30" and t_2<=x"39" and t_1>=x"30" and t_1<=x"31") then l2<=t_2. l1<=t_1-2.81 sig_f5<="000010". l1<= t_1. when "000010" => if(t_4>=x"30" and t_4<=x"39" and t_3>=x"30" and t_3<=x"35") then l4<=t_4.

82 else time_delay <= 1. end process. sig_f5<="000000". end if. . when others => end case. end Behavioral. end if.

the implementation of this equipment will ease the people. we can stop the vehicle and can reduce the impact of the accident. During the accident. Thus we can make use of the available technology to the benefit of the people by saving the lives of the people and helping the owners of the vehicle to keep track of their vehicles. This project can be enhanced in future by modifying in the program to find out the actual position of the vehicle and also in accident prevention. The processor should be connected to devices which can lock the brakes when triggered. whether it is severe or just a mild one. When public transport systems like bus. we can make it to send the position of the vehicle periodically to a subscribed mobile number so that companies can keep an eye on their vehicles. trains these are installed with this equipment. We can predict whether the vehicle is in normal position or upside down. By this enhancement. With the help of accelerometer sensor. it becomes severe as the drivers lose control and can‘t stop the vehicle. People can know the location of the vehicle and arrive in the stop in time. This can be used to prevent vehicle theft. In case of any theft. the accelerometer sensor will triggered due to vibrations which is received and processed by the Spartan processor. the owner can track the location of the vehicle. It doesn‘t tell the exact nature of the accident. In many accidents. This can also be enhanced by automatically locking all the brakes in case of accident. . In public transport system.83 CHAPTER 9 CONCLUSION This version of our project will send a reply when we send a SMS and also sends the position of the vehicle in terms of latitude and longitude when there is any accident. we can tell the exact position of the vehicle. Modifying the code.

Egypt. Souleiman Midani. Peter J.‘ Design Of Vehicle Position Tracking System Using Short Message Services And Its Implementation On FPGA‘. Proceedings of the 2005 Asia and South Pacific Design Automation Conference. Damaj.‘Principles and Applications of GSM‘. Prentice Hall PTR 6. Joseph E. ISBN:0-7803-8737-6 3.Mediterranean Microwave Symposium. Ziad A.‘Wireless Communication‘. Wilkes (October 1998). Ashenden (1995) . Prentice Hall PTR 1. Ain Shams University.‘The designer's guide to VHDL‘. 2. Osman. Zantout (July 24. Arias Tanti Hapsari Eniman Y Syamsudin Imron Pramana (2005) . Rached N. Rappaport (2008).84 REFERENCES 1. Cairo. ‗Implementation of a System for Offline Tracking using GPS‘ . Mazen Jrab. Zantout (May 2003). . 5. Proceedings of the world Congress on Engineering Vol I WCE 2. Yaqzan. Vijay Kumar Garg. and Rached N. Theodore S. 203-207. Issam W. Morgan Kaufmann Publishers. pp. 2008).‘ GPSBased Vehicle Tracking System-On-Chip‘. Adnan I. San Francisco 4.

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